Re: [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table

From	Thierry Reding <thierry.reding@gmail.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
Date	2016-11-07 13:40 +0100
Message-ID	<sARns-376-11@gated-at.bofh.it> (permalink)
References	<sANDb-tf-3@gated-at.bofh.it> <sANDb-tf-1@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Mon, Nov 07, 2016 at 09:30:00AM +0100, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
> 
> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
> is max rate.
> 
> The maximum rate value of 92 MHz is pulled from the downstream L4T
> kernel.
> 
> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
> Acked-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> 
> Changes in v2:
> - no changes
> 
> Changes in v3:
> - Added comment in commit message where I got the maximum rates from.
> 
> Changes in V4:
> - no changes

Applied, thanks.

Thierry

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[PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Mirza Krak <mirza.krak@gmail.com> - 2016-11-07 09:40 +0100
  Re: [PATCH V4 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table Thierry Reding <thierry.reding@gmail.com> - 2016-11-07 13:40 +0100

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