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| Started by | Bjorn Helgaas <helgaas@kernel.org> |
|---|---|
| First post | 2016-08-15 21:00 +0200 |
| Last post | 2016-08-16 03:30 +0200 |
| Articles | 2 — 2 participants |
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Re: [PATCH v6 0/3] PCI: Precision Time Measurement support Bjorn Helgaas <helgaas@kernel.org> - 2016-08-15 21:00 +0200
Re: [PATCH v6 0/3] PCI: Precision Time Measurement support "Yong, Jonathan" <jonathan.yong@intel.com> - 2016-08-16 03:30 +0200
| From | Bjorn Helgaas <helgaas@kernel.org> |
|---|---|
| Date | 2016-08-15 21:00 +0200 |
| Subject | Re: [PATCH v6 0/3] PCI: Precision Time Measurement support |
| Message-ID | <s6vh7-LT-1@gated-at.bofh.it> |
On Wed, Jul 20, 2016 at 07:49:21AM +0800, Yong, Jonathan wrote:
> On 07/20/2016 05:19, Bjorn Helgaas wrote:
> > On Mon, Jun 13, 2016 at 02:05:26PM -0500, Bjorn Helgaas wrote:
> >> This is a slightly different proposal for the PTM support Jonathan
> >> proposed here:
> >>
> >> http://lkml.kernel.org/r/1462956446-27361-2-git-send-email-jonathan.yong@intel.com
> >>
> >> I split this into three pieces mostly for ease in reviewing. They
> >> could all be squashed:
> >>
> >> - Enable PTM in root ports and switches automatically at boot
> >> - Enable PTM in endpoints when requested by driver
> >> - Add clock granularity information
> >>
> >> I have some open questions about how PTM works on Root Complex
> >> Integrated Endpoints and whether we should enable it automatically
> >> even without a driver request. And I probably left out some details
> >> of the clock granularity computation, so treat this as more of an RFC
> >> than anything.
> >>
> >
> > Jonathan, any comments?
> >
>
> I don't have any new information on how to configure integrated endpoints.
>
> This line:
> ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
>
> should also set the responder capable bit (7.32.2):
> If PTM Root Capable is Set, this bit must be Set to 1b.
The PTM Responder Capable bit (bit 1 in Table 7-145) is a HwInit bit
in the PTM Capability register, so it's read-only from the kernel's
perspective.
The line you mention ("ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT")
is turning on bits in the PTM Control register, not the Capability
register.
Bjorn
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| From | "Yong, Jonathan" <jonathan.yong@intel.com> |
|---|---|
| Date | 2016-08-16 03:30 +0200 |
| Message-ID | <s6Bmx-4Uu-1@gated-at.bofh.it> |
| In reply to | #1463094 |
On 08/16/2016 02:51, Bjorn Helgaas wrote:
>>
>> This line:
>> ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
>>
>> should also set the responder capable bit (7.32.2):
>> If PTM Root Capable is Set, this bit must be Set to 1b.
>
> The PTM Responder Capable bit (bit 1 in Table 7-145) is a HwInit bit
> in the PTM Capability register, so it's read-only from the kernel's
> perspective.
>
> The line you mention ("ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT")
> is turning on bits in the PTM Control register, not the Capability
> register.
>
My bad, there is no "responder enable" bit control, patch looks good.
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