Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1460959 > unrolled thread

Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write

Back to article view | Back to linux.kernel

This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by below is the oldest one visible, not the original post.

Contents

  Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write Wanpeng Li <kernellwp@gmail.com> - 2016-08-12 08:10 +0200
    Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on  MSR_IA32_APICBASE write Radim Krčmář <rkrcmar@redhat.com> - 2016-08-12 11:50 +0200
      Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write Wanpeng Li <kernellwp@gmail.com> - 2016-08-12 12:20 +0200
        Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on  MSR_IA32_APICBASE write Radim Krčmář <rkrcmar@redhat.com> - 2016-08-12 13:40 +0200
          Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write Wanpeng Li <kernellwp@gmail.com> - 2016-08-15 07:20 +0200
            Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on  MSR_IA32_APICBASE write Radim Krčmář <rkrcmar@redhat.com> - 2016-08-15 16:40 +0200

#1460959 — Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write

2016-08-09 2:16 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
> If vmcs12 does not intercept APIC_BASE writes, then KVM will handle the
> write with vmcs02 as the current VMCS.
> This will incorrectly apply modifications intended for vmcs01 to vmcs02
> and L2 can use it to gain access to L0's x2APIC registers by disabling
> virtualized x2APIC while using msr bitmap that assumes enabled.
>
> Postpone execution of vmx_set_virtual_x2apic_mode until vmcs01 is the
> current VMCS.  An alternative solution would temporarily make vmcs01 the
> current VMCS, but it requires more care.

There is a scenario both L1 and L2 are running on x2apic mode, L1
don't own the APIC_BASE writes, then L2 is intended to disable x2apic
mode, however, your logic will also disable x2apic mode for L1.

Regards,
Wanpeng Li

[toc] | [next] | [standalone]

#1461044 — Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write

2016-08-12 14:07+0800, Wanpeng Li:
> 2016-08-09 2:16 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>> If vmcs12 does not intercept APIC_BASE writes, then KVM will handle the
>> write with vmcs02 as the current VMCS.
>> This will incorrectly apply modifications intended for vmcs01 to vmcs02
>> and L2 can use it to gain access to L0's x2APIC registers by disabling
>> virtualized x2APIC while using msr bitmap that assumes enabled.
>>
>> Postpone execution of vmx_set_virtual_x2apic_mode until vmcs01 is the
>> current VMCS.  An alternative solution would temporarily make vmcs01 the
>> current VMCS, but it requires more care.
> 
> There is a scenario both L1 and L2 are running on x2apic mode, L1
> don't own the APIC_BASE writes, then L2 is intended to disable x2apic
> mode, however, your logic will also disable x2apic mode for L1.

You mean a case where L1 does intercept APIC_BASE?

That case is not affected, because it should cause a nested VM exit, so
vmx_set_virtual_x2apic_mode() won't be called in the first place.

[toc] | [prev] | [next] | [standalone]

#1461065

2016-08-12 17:44 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
> 2016-08-12 14:07+0800, Wanpeng Li:
>> 2016-08-09 2:16 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>>> If vmcs12 does not intercept APIC_BASE writes, then KVM will handle the
>>> write with vmcs02 as the current VMCS.
>>> This will incorrectly apply modifications intended for vmcs01 to vmcs02
>>> and L2 can use it to gain access to L0's x2APIC registers by disabling
>>> virtualized x2APIC while using msr bitmap that assumes enabled.
>>>
>>> Postpone execution of vmx_set_virtual_x2apic_mode until vmcs01 is the
>>> current VMCS.  An alternative solution would temporarily make vmcs01 the
>>> current VMCS, but it requires more care.
>>
>> There is a scenario both L1 and L2 are running on x2apic mode, L1
>> don't own the APIC_BASE writes, then L2 is intended to disable x2apic
>> mode, however, your logic will also disable x2apic mode for L1.
>
> You mean a case where L1 does intercept APIC_BASE?
>
> That case is not affected, because it should cause a nested VM exit, so
> vmx_set_virtual_x2apic_mode() won't be called in the first place.

I mean L1 doesn't intercept APIC_BASE.

Regards,
Wanpeng Li

[toc] | [prev] | [next] | [standalone]

#1461113 — Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write

2016-08-12 18:14+0800, Wanpeng Li:
> 2016-08-12 17:44 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>> 2016-08-12 14:07+0800, Wanpeng Li:
>>> 2016-08-09 2:16 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>>>> If vmcs12 does not intercept APIC_BASE writes, then KVM will handle the
>>>> write with vmcs02 as the current VMCS.
>>>> This will incorrectly apply modifications intended for vmcs01 to vmcs02
>>>> and L2 can use it to gain access to L0's x2APIC registers by disabling
>>>> virtualized x2APIC while using msr bitmap that assumes enabled.
>>>>
>>>> Postpone execution of vmx_set_virtual_x2apic_mode until vmcs01 is the
>>>> current VMCS.  An alternative solution would temporarily make vmcs01 the
>>>> current VMCS, but it requires more care.
>>>
>>> There is a scenario both L1 and L2 are running on x2apic mode, L1
>>> don't own the APIC_BASE writes, then L2 is intended to disable x2apic
>>> mode, however, your logic will also disable x2apic mode for L1.
>>
>> You mean a case where L1 does intercept APIC_BASE?
>>
>> That case is not affected, because it should cause a nested VM exit, so
>> vmx_set_virtual_x2apic_mode() won't be called in the first place.
> 
> I mean L1 doesn't intercept APIC_BASE.

Then L2's write to APIC_BASE should only affect L1.
L2 is buggy if it intended to disable its x2APIC with the write
or L1 set up intercepts incorrectly for the indented L2.

In the non-nested case, if we didn't intercept APIC_BASE in KVM, then
the guest wouldn't change either;  only the host would change, so I
think it is correct to disable x2APIC mode in L1 only.

[toc] | [prev] | [next] | [standalone]

#1462554

2016-08-12 19:39 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
> 2016-08-12 18:14+0800, Wanpeng Li:
>> 2016-08-12 17:44 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>>> 2016-08-12 14:07+0800, Wanpeng Li:
>>>> 2016-08-09 2:16 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>>>>> If vmcs12 does not intercept APIC_BASE writes, then KVM will handle the
>>>>> write with vmcs02 as the current VMCS.
>>>>> This will incorrectly apply modifications intended for vmcs01 to vmcs02
>>>>> and L2 can use it to gain access to L0's x2APIC registers by disabling
>>>>> virtualized x2APIC while using msr bitmap that assumes enabled.
>>>>>
>>>>> Postpone execution of vmx_set_virtual_x2apic_mode until vmcs01 is the
>>>>> current VMCS.  An alternative solution would temporarily make vmcs01 the
>>>>> current VMCS, but it requires more care.
>>>>
>>>> There is a scenario both L1 and L2 are running on x2apic mode, L1
>>>> don't own the APIC_BASE writes, then L2 is intended to disable x2apic
>>>> mode, however, your logic will also disable x2apic mode for L1.
>>>
>>> You mean a case where L1 does intercept APIC_BASE?
>>>
>>> That case is not affected, because it should cause a nested VM exit, so
>>> vmx_set_virtual_x2apic_mode() won't be called in the first place.
>>
>> I mean L1 doesn't intercept APIC_BASE.
>
> Then L2's write to APIC_BASE should only affect L1.
> L2 is buggy if it intended to disable its x2APIC with the write
> or L1 set up intercepts incorrectly for the indented L2.

Do you mean OS disable x2APIC during its running is buggy?

> In the non-nested case, if we didn't intercept APIC_BASE in KVM, then
> the guest wouldn't change either;  only the host would change, so I
> think it is correct to disable x2APIC mode in L1 only.

Agreed. :)

Regards,
Wanpeng Li

[toc] | [prev] | [next] | [standalone]

#1462831 — Re: [PATCH 2/2] KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write

2016-08-15 13:19+0800, Wanpeng Li:
> 2016-08-12 19:39 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>> 2016-08-12 18:14+0800, Wanpeng Li:
>>> 2016-08-12 17:44 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>>>> 2016-08-12 14:07+0800, Wanpeng Li:
>>>>> 2016-08-09 2:16 GMT+08:00 Radim Krčmář <rkrcmar@redhat.com>:
>>>>>> If vmcs12 does not intercept APIC_BASE writes, then KVM will handle the
>>>>>> write with vmcs02 as the current VMCS.
>>>>>> This will incorrectly apply modifications intended for vmcs01 to vmcs02
>>>>>> and L2 can use it to gain access to L0's x2APIC registers by disabling
>>>>>> virtualized x2APIC while using msr bitmap that assumes enabled.
>>>>>>
>>>>>> Postpone execution of vmx_set_virtual_x2apic_mode until vmcs01 is the
>>>>>> current VMCS.  An alternative solution would temporarily make vmcs01 the
>>>>>> current VMCS, but it requires more care.
>>>>>
>>>>> There is a scenario both L1 and L2 are running on x2apic mode, L1
>>>>> don't own the APIC_BASE writes, then L2 is intended to disable x2apic
>>>>> mode, however, your logic will also disable x2apic mode for L1.
>>>>
>>>> You mean a case where L1 does intercept APIC_BASE?
>>>>
>>>> That case is not affected, because it should cause a nested VM exit, so
>>>> vmx_set_virtual_x2apic_mode() won't be called in the first place.
>>>
>>> I mean L1 doesn't intercept APIC_BASE.
>>
>> Then L2's write to APIC_BASE should only affect L1.
>> L2 is buggy if it intended to disable its x2APIC with the write
>> or L1 set up intercepts incorrectly for the indented L2.
> 
> Do you mean OS disable x2APIC during its running is buggy?

Not in general, but if L1 doesn't intercept APIC_BASE and L2 writes to
it in order to disable its (L2's) x2APIC, then there is a bug in L2 or
L1.

If L1 intended to intercept, then it's a clear L1 bug, otherwise L2
should have known that L1 is a special hypervisor that doesn't intercept
APIC_BASE and the bug is on L2 side or on the user that ran unsuspecting
L2 on that L1.

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web