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[Urgent PATCH] arm64: dts: uniphier: fix IRQ trigger type of ARMv8 timer

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  [Urgent PATCH] arm64: dts: uniphier: fix IRQ trigger type of ARMv8 timer Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-08-01 10:20 +0200
    Re: [Urgent PATCH] arm64: dts: uniphier: fix IRQ trigger type of  ARMv8 timer Marc Zyngier <marc.zyngier@arm.com> - 2016-08-01 10:30 +0200
      Re: [Urgent PATCH] arm64: dts: uniphier: fix IRQ trigger type of  ARMv8 timer Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-08-01 10:40 +0200
    Re: [Urgent PATCH] arm64: dts: uniphier: fix IRQ trigger type of ARMv8 timer Arnd Bergmann <arnd@arndb.de> - 2016-08-10 23:00 +0200

#1453034 — [Urgent PATCH] arm64: dts: uniphier: fix IRQ trigger type of ARMv8 timer

Since commit 1e2a7d78499e ("irqdomain: Don't set type when mapping
an IRQ"), the interrupt type is strictly checked.  Without this
patch, this board would not boot any more.

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
says that the 3rd cell should be either 1 (edge) or 4 (level)
depending on the trigger type.  As the CA72 Generic Timer provides
active-low interrupts, the value of the 3rd cell should be 4.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
---
Arnd, Olof,

I guess you are about to send pull-reqs for v4.8 cycle.
Could you include this one in them?
After IRQ updates for 4.8 were merged, my board would not
boot at all.  I consulted experts and looks like my DT
was wrong.

I could do this after -rc1 is out because it is apparently a
bug fix, but in that case the for-next branch in ASOC will be
broken for me, which would make bisect-ability difficult for me.


 arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
index fd1af50..bafbcce 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
@@ -117,10 +117,7 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <1 13 0xf01>,
-			     <1 14 0xf01>,
-			     <1 11 0xf01>,
-			     <1 10 0xf01>;
+		interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>;
 	};
 
 	soc {
-- 
1.9.1

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#1453036 — Re: [Urgent PATCH] arm64: dts: uniphier: fix IRQ trigger type of ARMv8 timer

Please keep me cc-ed on this.

On 01/08/16 09:12, Masahiro Yamada wrote:
> Since commit 1e2a7d78499e ("irqdomain: Don't set type when mapping
> an IRQ"), the interrupt type is strictly checked.  Without this
> patch, this board would not boot any more.
> 
> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
> says that the 3rd cell should be either 1 (edge) or 4 (level)
> depending on the trigger type.  As the CA72 Generic Timer provides
> active-low interrupts, the value of the 3rd cell should be 4.
> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> Arnd, Olof,
> 
> I guess you are about to send pull-reqs for v4.8 cycle.
> Could you include this one in them?
> After IRQ updates for 4.8 were merged, my board would not
> boot at all.  I consulted experts and looks like my DT
> was wrong.
> 
> I could do this after -rc1 is out because it is apparently a
> bug fix, but in that case the for-next branch in ASOC will be
> broken for me, which would make bisect-ability difficult for me.

I have a patch that addresses all platforms in one go (there is really
no point in fixing one at a time for a bug that is so widespread).

I'll repost it later today.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

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#1453039 — Re: [Urgent PATCH] arm64: dts: uniphier: fix IRQ trigger type of ARMv8 timer

Hi Marc,

2016-08-01 17:18 GMT+09:00 Marc Zyngier <marc.zyngier@arm.com>:
> Please keep me cc-ed on this.

Sorry, I automate patch-posting, but scripts/get_maintainer.pl
did not pick you up.  Also, I forgot to cc you explicitly.


> On 01/08/16 09:12, Masahiro Yamada wrote:
>> Since commit 1e2a7d78499e ("irqdomain: Don't set type when mapping
>> an IRQ"), the interrupt type is strictly checked.  Without this
>> patch, this board would not boot any more.
>>
>> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
>> says that the 3rd cell should be either 1 (edge) or 4 (level)
>> depending on the trigger type.  As the CA72 Generic Timer provides
>> active-low interrupts, the value of the 3rd cell should be 4.
>>
>> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>> Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>> Arnd, Olof,
>>
>> I guess you are about to send pull-reqs for v4.8 cycle.
>> Could you include this one in them?
>> After IRQ updates for 4.8 were merged, my board would not
>> boot at all.  I consulted experts and looks like my DT
>> was wrong.
>>
>> I could do this after -rc1 is out because it is apparently a
>> bug fix, but in that case the for-next branch in ASOC will be
>> broken for me, which would make bisect-ability difficult for me.
>
> I have a patch that addresses all platforms in one go (there is really
> no point in fixing one at a time for a bug that is so widespread).
>
> I'll repost it later today.
>

That'll be fine.
Thank you!


Arnd, Olof:
Please disregard this one.




-- 
Best Regards
Masahiro Yamada

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#1459927

On Monday, August 1, 2016 5:12:20 PM CEST Masahiro Yamada wrote:
> Since commit 1e2a7d78499e ("irqdomain: Don't set type when mapping
> an IRQ"), the interrupt type is strictly checked.  Without this
> patch, this board would not boot any more.
> 
> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
> says that the 3rd cell should be either 1 (edge) or 4 (level)
> depending on the trigger type.  As the CA72 Generic Timer provides
> active-low interrupts, the value of the 3rd cell should be 4.
> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
> 

I've added it to the fixes branch now, sorry for the delay.

	Arnd

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