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Groups > linux.kernel > #1397915 > unrolled thread
| Started by | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| First post | 2016-05-10 12:00 +0200 |
| Last post | 2016-05-10 12:10 +0200 |
| Articles | 20 on this page of 21 — 2 participants |
Back to article view | Back to linux.kernel
[RFC PATCH 00/21] mfd, clock, reset: add UniPhier clock/reset driver support Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 14/21] reset: uniphier: add reset driver for UniPhier PH1-Pro4 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 11/21] clk: uniphier: add clock driver for Peripheral block on UniPhier SoCs Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 19/21] reset: uniphier: add reset driver for UniPhier PH1-LD20 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 21/21] reset: uniphier: add reset driver for Peripheral block on UniPhier SoCs Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 17/21] reset: uniphier: add reset driver for UniPhier ProXstream2/PH1-LD6b SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 05/21] clk: uniphier: add clock driver for UniPhier PH1-sLD8 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 02/21] clk: uniphier: add core support for UniPhier clock driver Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 10/21] clk: uniphier: add clock driver for Media I/O block on UniPhier SoCs Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 01/21] mfd: uniphier: add UniPhier MFD driver Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
Re: [RFC PATCH 01/21] mfd: uniphier: add UniPhier MFD driver Lee Jones <lee.jones@linaro.org> - 2016-05-10 13:30 +0200
Re: [RFC PATCH 01/21] mfd: uniphier: add UniPhier MFD driver Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-11 04:00 +0200
Re: [RFC PATCH 01/21] mfd: uniphier: add UniPhier MFD driver Lee Jones <lee.jones@linaro.org> - 2016-05-11 09:40 +0200
[RFC PATCH 07/21] clk: uniphier: add clock driver for UniPhier ProXstream2/PH1-LD6b SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 09/21] clk: uniphier: add clock driver for UniPhier PH1-LD20 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 06/21] clk: uniphier: add clock driver for UniPhier PH1-Pro5 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 15/21] reset: uniphier: add reset driver for UniPhier PH1-sLD8 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 16/21] reset: uniphier: add reset driver for UniPhier PH1-Pro5 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 18/21] reset: uniphier: add reset driver for UniPhier PH1-LD11 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 08/21] clk: uniphier: add clock driver for UniPhier PH1-LD11 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:00 +0200
[RFC PATCH 03/21] clk: uniphier: add clock driver for UniPhier PH1-LD4 SoC Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-05-10 12:10 +0200
Page 1 of 2 [1] 2 Next page →
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 00/21] mfd, clock, reset: add UniPhier clock/reset driver support |
| Message-ID | <rxcCl-8kL-3@gated-at.bofh.it> |
This series adds support for clock and reset (and MFD to populate them)
for UniPhier SoCs.
On UniPhier SoCs, one system control block contains various registers
for clock, reset, and others in it.
I consulted Arnd for better implementation for clock/reset drivers in such a case.
https://lkml.org/lkml/2016/4/18/605
After a while, I chose MFD approach and found it is a good fit in my case.
So, here I intentionally included clock, reset, MFD in one patch series
because they are related with one another.
I have not completed this series. Some known problems are:
- Binding document is missing
- I need to fill clock/reset tables a bit more.
Please do not apply this series.
But, this sereis should be enough for reviewing
if my basic approach is OK or not.
Your feedback is appreciated.
Masahiro Yamada (21):
mfd: uniphier: add UniPhier MFD driver
clk: uniphier: add core support for UniPhier clock driver
clk: uniphier: add clock driver for UniPhier PH1-LD4 SoC
clk: uniphier: add clock driver for UniPhier PH1-Pro4 SoC
clk: uniphier: add clock driver for UniPhier PH1-sLD8 SoC
clk: uniphier: add clock driver for UniPhier PH1-Pro5 SoC
clk: uniphier: add clock driver for UniPhier ProXstream2/PH1-LD6b SoC
clk: uniphier: add clock driver for UniPhier PH1-LD11 SoC
clk: uniphier: add clock driver for UniPhier PH1-LD20 SoC
clk: uniphier: add clock driver for Media I/O block on UniPhier SoCs
clk: uniphier: add clock driver for Peripheral block on UniPhier SoCs
reset: uniphier: add core support for UniPhier reset driver
reset: uniphier: add reset driver for UniPhier PH1-LD4 SoC
reset: uniphier: add reset driver for UniPhier PH1-Pro4 SoC
reset: uniphier: add reset driver for UniPhier PH1-sLD8 SoC
reset: uniphier: add reset driver for UniPhier PH1-Pro5 SoC
reset: uniphier: add reset driver for UniPhier ProXstream2/PH1-LD6b
SoC
reset: uniphier: add reset driver for UniPhier PH1-LD11 SoC
reset: uniphier: add reset driver for UniPhier PH1-LD20 SoC
reset: uniphier: add reset driver for Media I/O block on UniPhier SoCs
reset: uniphier: add reset driver for Peripheral block on UniPhier
SoCs
MAINTAINERS | 3 +
drivers/clk/uniphier/Kconfig | 45 +++++
drivers/clk/uniphier/Makefile | 16 ++
drivers/clk/uniphier/clk-uniphier-core.c | 99 +++++++++++
drivers/clk/uniphier/clk-uniphier-fixed-factor.c | 50 ++++++
drivers/clk/uniphier/clk-uniphier-fixed-rate.c | 49 ++++++
drivers/clk/uniphier/clk-uniphier-gate.c | 98 +++++++++++
drivers/clk/uniphier/clk-uniphier-ld11.c | 83 +++++++++
drivers/clk/uniphier/clk-uniphier-ld20.c | 83 +++++++++
drivers/clk/uniphier/clk-uniphier-ld4.c | 112 ++++++++++++
drivers/clk/uniphier/clk-uniphier-mio.c | 215 +++++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier-mux.c | 96 ++++++++++
drivers/clk/uniphier/clk-uniphier-peri.c | 133 ++++++++++++++
drivers/clk/uniphier/clk-uniphier-pro4.c | 112 ++++++++++++
drivers/clk/uniphier/clk-uniphier-pro5.c | 102 +++++++++++
drivers/clk/uniphier/clk-uniphier-pxs2.c | 83 +++++++++
drivers/clk/uniphier/clk-uniphier-sld8.c | 102 +++++++++++
drivers/clk/uniphier/clk-uniphier.h | 89 ++++++++++
drivers/mfd/Kconfig | 9 +
drivers/mfd/Makefile | 1 +
drivers/mfd/uniphier-mfd.c | 214 ++++++++++++++++++++++
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/uniphier/Kconfig | 45 +++++
drivers/reset/uniphier/Makefile | 12 ++
drivers/reset/uniphier/reset-uniphier-core.c | 151 ++++++++++++++++
drivers/reset/uniphier/reset-uniphier-ld11.c | 46 +++++
drivers/reset/uniphier/reset-uniphier-ld20.c | 46 +++++
drivers/reset/uniphier/reset-uniphier-ld4.c | 46 +++++
drivers/reset/uniphier/reset-uniphier-mio.c | 106 +++++++++++
drivers/reset/uniphier/reset-uniphier-peri.c | 101 +++++++++++
drivers/reset/uniphier/reset-uniphier-pro4.c | 46 +++++
drivers/reset/uniphier/reset-uniphier-pro5.c | 46 +++++
drivers/reset/uniphier/reset-uniphier-pxs2.c | 46 +++++
drivers/reset/uniphier/reset-uniphier-sld8.c | 46 +++++
drivers/reset/uniphier/reset-uniphier.h | 33 ++++
36 files changed, 2566 insertions(+)
create mode 100644 drivers/clk/uniphier/Kconfig
create mode 100644 drivers/clk/uniphier/Makefile
create mode 100644 drivers/clk/uniphier/clk-uniphier-core.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-fixed-factor.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-fixed-rate.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-gate.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-ld11.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-ld20.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-ld4.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-mux.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-pro4.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-pro5.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-pxs2.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-sld8.c
create mode 100644 drivers/clk/uniphier/clk-uniphier.h
create mode 100644 drivers/mfd/uniphier-mfd.c
create mode 100644 drivers/reset/uniphier/Kconfig
create mode 100644 drivers/reset/uniphier/Makefile
create mode 100644 drivers/reset/uniphier/reset-uniphier-core.c
create mode 100644 drivers/reset/uniphier/reset-uniphier-ld11.c
create mode 100644 drivers/reset/uniphier/reset-uniphier-ld20.c
create mode 100644 drivers/reset/uniphier/reset-uniphier-ld4.c
create mode 100644 drivers/reset/uniphier/reset-uniphier-mio.c
create mode 100644 drivers/reset/uniphier/reset-uniphier-peri.c
create mode 100644 drivers/reset/uniphier/reset-uniphier-pro4.c
create mode 100644 drivers/reset/uniphier/reset-uniphier-pro5.c
create mode 100644 drivers/reset/uniphier/reset-uniphier-pxs2.c
create mode 100644 drivers/reset/uniphier/reset-uniphier-sld8.c
create mode 100644 drivers/reset/uniphier/reset-uniphier.h
--
1.9.1
[toc] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 14/21] reset: uniphier: add reset driver for UniPhier PH1-Pro4 SoC |
| Message-ID | <rxcCm-8kL-19@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/reset/uniphier/Kconfig | 4 +++
drivers/reset/uniphier/Makefile | 1 +
drivers/reset/uniphier/reset-uniphier-pro4.c | 46 ++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
create mode 100644 drivers/reset/uniphier/reset-uniphier-pro4.c
diff --git a/drivers/reset/uniphier/Kconfig b/drivers/reset/uniphier/Kconfig
index 875afd9..1633093 100644
--- a/drivers/reset/uniphier/Kconfig
+++ b/drivers/reset/uniphier/Kconfig
@@ -10,4 +10,8 @@ config RESET_UNIPHIER_LD4
tristate "Reset driver for UniPhier PH1-LD4 SoC"
default ARM
+config RESET_UNIPHIER_PRO4
+ tristate "Reset driver for UniPhier PH1-Pro4 SoC"
+ default ARM
+
endif
diff --git a/drivers/reset/uniphier/Makefile b/drivers/reset/uniphier/Makefile
index c99a420..d496fe8 100644
--- a/drivers/reset/uniphier/Makefile
+++ b/drivers/reset/uniphier/Makefile
@@ -1,3 +1,4 @@
obj-y += reset-uniphier-core.o
obj-$(CONFIG_RESET_UNIPHIER_LD4) += reset-uniphier-ld4.o
+obj-$(CONFIG_RESET_UNIPHIER_PRO4) += reset-uniphier-pro4.o
diff --git a/drivers/reset/uniphier/reset-uniphier-pro4.c b/drivers/reset/uniphier/reset-uniphier-pro4.c
new file mode 100644
index 0000000..57ce253
--- /dev/null
+++ b/drivers/reset/uniphier/reset-uniphier-pro4.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "reset-uniphier.h"
+
+static const struct uniphier_reset_data uniphier_pro4_reset_data[] = {
+ {
+ .id = 7,
+ .reg = 0x2000,
+ .mask = BIT(10),
+ .deassert_val = BIT(10),
+ },
+ { .id = UNIPHIER_RESET_ID_END }
+};
+
+static int uniphier_pro4_reset_probe(struct platform_device *pdev)
+{
+ return uniphier_reset_probe(pdev, uniphier_pro4_reset_data);
+}
+
+static struct platform_driver uniphier_pro4_reset_driver = {
+ .probe = uniphier_pro4_reset_probe,
+ .driver = {
+ .name = "uniphier-pro4-reset",
+ },
+};
+module_platform_driver(uniphier_pro4_reset_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-Pro4 Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 11/21] clk: uniphier: add clock driver for Peripheral block on UniPhier SoCs |
| Message-ID | <rxcCm-8kL-25@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/clk/uniphier/Kconfig | 4 +
drivers/clk/uniphier/Makefile | 1 +
drivers/clk/uniphier/clk-uniphier-peri.c | 133 +++++++++++++++++++++++++++++++
3 files changed, 138 insertions(+)
create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index 895c4a0..08edaf8 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -38,4 +38,8 @@ config CLK_UNIPHIER_MIO
tristate "Clock driver for UniPhier Media I/O block"
default y
+config CLK_UNIPHIER_PERI
+ tristate "Clock driver for UniPhier Peripheral block"
+ default y
+
endif
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index ae71f04..a69d6fe 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_UNIPHIER_LD11) += clk-uniphier-ld11.o
obj-$(CONFIG_CLK_UNIPHIER_LD20) += clk-uniphier-ld20.o
obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o
+obj-$(CONFIG_CLK_UNIPHIER_PERI) += clk-uniphier-peri.o
diff --git a/drivers/clk/uniphier/clk-uniphier-peri.c b/drivers/clk/uniphier/clk-uniphier-peri.c
new file mode 100644
index 0000000..e5510f5
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-peri.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+#define UNIPHIER_PERI_CLK_UART(ch, index) \
+ { \
+ .name = "uart" #ch, \
+ .type = UNIPHIER_CLK_TYPE_GATE, \
+ .output_index = (index), \
+ .data.gate = { \
+ .parent_name = "uart", \
+ .reg = 0x24, \
+ .mask = BIT(19 + ch), \
+ .enable_val = BIT(19 + ch), \
+ }, \
+ }
+
+#define UNIPHIER_PERI_CLK_I2C_COMMON \
+ { \
+ .name = "i2c-common", \
+ .type = UNIPHIER_CLK_TYPE_GATE, \
+ .output_index = -1, \
+ .data.gate = { \
+ .parent_name = "i2c", \
+ .reg = 0x20, \
+ .mask = BIT(1), \
+ .enable_val = BIT(1), \
+ }, \
+ }
+
+#define UNIPHIER_PERI_CLK_I2C(ch, index) \
+ { \
+ .name = "i2c" #ch, \
+ .type = UNIPHIER_CLK_TYPE_GATE, \
+ .output_index = (index), \
+ .data.gate = { \
+ .parent_name = "i2c-common", \
+ .reg = 0x24, \
+ .mask = BIT(5 + ch), \
+ .enable_val = BIT(5 + ch), \
+ }, \
+ }
+
+#define UNIPHIER_PERI_CLK_FI2C(ch, index) \
+ { \
+ .name = "fi2c" #ch, \
+ .type = UNIPHIER_CLK_TYPE_GATE, \
+ .output_index = (index), \
+ .data.gate = { \
+ .parent_name = "fi2c", \
+ .reg = 0x24, \
+ .mask = BIT(24 + ch), \
+ .enable_val = BIT(24 + ch), \
+ }, \
+ }
+
+static const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
+ UNIPHIER_PERI_CLK_UART(0, 0),
+ UNIPHIER_PERI_CLK_UART(1, 1),
+ UNIPHIER_PERI_CLK_UART(2, 2),
+ UNIPHIER_PERI_CLK_UART(3, 3),
+ UNIPHIER_PERI_CLK_I2C_COMMON,
+ UNIPHIER_PERI_CLK_I2C(0, 4),
+ UNIPHIER_PERI_CLK_I2C(1, 5),
+ UNIPHIER_PERI_CLK_I2C(2, 6),
+ UNIPHIER_PERI_CLK_I2C(3, 7),
+ UNIPHIER_PERI_CLK_I2C(4, 8),
+ { /* sentinel */ }
+};
+
+static int uniphier_ld4_peri_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_ld4_peri_clk_data);
+}
+
+static struct platform_driver uniphier_ld4_peri_clk_driver = {
+ .probe = uniphier_ld4_peri_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-ld4-peri-clk",
+ },
+};
+module_platform_driver(uniphier_ld4_peri_clk_driver);
+
+static const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
+ UNIPHIER_PERI_CLK_UART(0, 0),
+ UNIPHIER_PERI_CLK_UART(1, 1),
+ UNIPHIER_PERI_CLK_UART(2, 2),
+ UNIPHIER_PERI_CLK_UART(3, 3),
+ UNIPHIER_PERI_CLK_FI2C(0, 4),
+ UNIPHIER_PERI_CLK_FI2C(1, 5),
+ UNIPHIER_PERI_CLK_FI2C(2, 6),
+ UNIPHIER_PERI_CLK_FI2C(3, 7),
+ UNIPHIER_PERI_CLK_FI2C(4, 8),
+ UNIPHIER_PERI_CLK_FI2C(5, 9),
+ UNIPHIER_PERI_CLK_FI2C(6, 10),
+ { /* sentinel */ }
+};
+
+static int uniphier_pro4_peri_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_pro4_peri_clk_data);
+}
+
+static struct platform_driver uniphier_pro4_peri_clk_driver = {
+ .probe = uniphier_pro4_peri_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-pro4-peri-clk",
+ },
+};
+module_platform_driver(uniphier_pro4_peri_clk_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier Peripheral Clock Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 19/21] reset: uniphier: add reset driver for UniPhier PH1-LD20 SoC |
| Message-ID | <rxcCm-8kL-27@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/reset/uniphier/Kconfig | 4 +++
drivers/reset/uniphier/Makefile | 1 +
drivers/reset/uniphier/reset-uniphier-ld20.c | 46 ++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
create mode 100644 drivers/reset/uniphier/reset-uniphier-ld20.c
diff --git a/drivers/reset/uniphier/Kconfig b/drivers/reset/uniphier/Kconfig
index d9a2123..8509e71 100644
--- a/drivers/reset/uniphier/Kconfig
+++ b/drivers/reset/uniphier/Kconfig
@@ -30,4 +30,8 @@ config RESET_UNIPHIER_LD11
tristate "Reset driver for UniPhier PH1-LD11 SoC"
default ARM
+config RESET_UNIPHIER_LD20
+ tristate "Reset driver for UniPhier PH1-LD20 SoC"
+ default ARM64
+
endif
diff --git a/drivers/reset/uniphier/Makefile b/drivers/reset/uniphier/Makefile
index f25f648..a33cb0a 100644
--- a/drivers/reset/uniphier/Makefile
+++ b/drivers/reset/uniphier/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_RESET_UNIPHIER_SLD8) += reset-uniphier-sld8.o
obj-$(CONFIG_RESET_UNIPHIER_PRO5) += reset-uniphier-pro5.o
obj-$(CONFIG_RESET_UNIPHIER_PXS2) += reset-uniphier-pxs2.o
obj-$(CONFIG_RESET_UNIPHIER_LD11) += reset-uniphier-ld11.o
+obj-$(CONFIG_RESET_UNIPHIER_LD20) += reset-uniphier-ld20.o
diff --git a/drivers/reset/uniphier/reset-uniphier-ld20.c b/drivers/reset/uniphier/reset-uniphier-ld20.c
new file mode 100644
index 0000000..8edda31
--- /dev/null
+++ b/drivers/reset/uniphier/reset-uniphier-ld20.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "reset-uniphier.h"
+
+static const struct uniphier_reset_data uniphier_ld20_reset_data[] = {
+ {
+ .id = 7,
+ .reg = 0x200c,
+ .mask = BIT(8),
+ .deassert_val = BIT(8),
+ },
+ { .id = UNIPHIER_RESET_ID_END }
+};
+
+static int uniphier_ld20_reset_probe(struct platform_device *pdev)
+{
+ return uniphier_reset_probe(pdev, uniphier_ld20_reset_data);
+}
+
+static struct platform_driver uniphier_ld20_reset_driver = {
+ .probe = uniphier_ld20_reset_probe,
+ .driver = {
+ .name = "uniphier-ld20-reset",
+ },
+};
+module_platform_driver(uniphier_ld20_reset_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-LD20 Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 21/21] reset: uniphier: add reset driver for Peripheral block on UniPhier SoCs |
| Message-ID | <rxcCn-8kL-35@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/reset/uniphier/Kconfig | 4 ++
drivers/reset/uniphier/Makefile | 1 +
drivers/reset/uniphier/reset-uniphier-peri.c | 101 +++++++++++++++++++++++++++
3 files changed, 106 insertions(+)
create mode 100644 drivers/reset/uniphier/reset-uniphier-peri.c
diff --git a/drivers/reset/uniphier/Kconfig b/drivers/reset/uniphier/Kconfig
index a582938..d3e629e 100644
--- a/drivers/reset/uniphier/Kconfig
+++ b/drivers/reset/uniphier/Kconfig
@@ -38,4 +38,8 @@ config RESET_UNIPHIER_MIO
tristate "Reset driver for UniPhier Media I/O block"
default y
+config RESET_UNIPHIER_PERI
+ tristate "Reset driver for UniPhier Peripheral block"
+ default y
+
endif
diff --git a/drivers/reset/uniphier/Makefile b/drivers/reset/uniphier/Makefile
index e83bd14..65e9d2d 100644
--- a/drivers/reset/uniphier/Makefile
+++ b/drivers/reset/uniphier/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_RESET_UNIPHIER_LD11) += reset-uniphier-ld11.o
obj-$(CONFIG_RESET_UNIPHIER_LD20) += reset-uniphier-ld20.o
obj-$(CONFIG_RESET_UNIPHIER_MIO) += reset-uniphier-mio.o
+obj-$(CONFIG_RESET_UNIPHIER_PERI) += reset-uniphier-peri.o
diff --git a/drivers/reset/uniphier/reset-uniphier-peri.c b/drivers/reset/uniphier/reset-uniphier-peri.c
new file mode 100644
index 0000000..1ec1c16
--- /dev/null
+++ b/drivers/reset/uniphier/reset-uniphier-peri.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "reset-uniphier.h"
+
+#define UNIPHIER_PERI_RESET_UART(ch, index) \
+ { \
+ .id = (index), \
+ .reg = 0x114, \
+ .mask = BIT(19 + ch), \
+ .deassert_val = BIT(19 + ch), \
+ }
+
+#define UNIPHIER_PERI_RESET_I2C(ch, index) \
+ { \
+ .id = (index), \
+ .reg = 0x114, \
+ .mask = BIT(5 + ch), \
+ .deassert_val = BIT(5 + ch), \
+ }
+
+#define UNIPHIER_PERI_RESET_FI2C(ch, index) \
+ { \
+ .id = (index), \
+ .reg = 0x114, \
+ .mask = BIT(24 + ch), \
+ .deassert_val = BIT(24 + ch), \
+ }
+
+static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = {
+ UNIPHIER_PERI_RESET_UART(0, 0),
+ UNIPHIER_PERI_RESET_UART(1, 1),
+ UNIPHIER_PERI_RESET_UART(2, 2),
+ UNIPHIER_PERI_RESET_UART(3, 3),
+ UNIPHIER_PERI_RESET_I2C(0, 4),
+ UNIPHIER_PERI_RESET_I2C(1, 5),
+ UNIPHIER_PERI_RESET_I2C(2, 6),
+ UNIPHIER_PERI_RESET_I2C(3, 7),
+ UNIPHIER_PERI_RESET_I2C(4, 8),
+ { .id = UNIPHIER_RESET_ID_END }
+};
+
+static int uniphier_ld4_peri_reset_probe(struct platform_device *pdev)
+{
+ return uniphier_reset_probe(pdev, uniphier_ld4_peri_reset_data);
+}
+
+static struct platform_driver uniphier_ld4_peri_reset_driver = {
+ .probe = uniphier_ld4_peri_reset_probe,
+ .driver = {
+ .name = "uniphier-ld4-peri-reset",
+ },
+};
+module_platform_driver(uniphier_ld4_peri_reset_driver);
+
+static const struct uniphier_reset_data uniphier_pro5_peri_reset_data[] = {
+ UNIPHIER_PERI_RESET_UART(0, 0),
+ UNIPHIER_PERI_RESET_UART(1, 1),
+ UNIPHIER_PERI_RESET_UART(2, 2),
+ UNIPHIER_PERI_RESET_UART(3, 3),
+ UNIPHIER_PERI_RESET_FI2C(0, 4),
+ UNIPHIER_PERI_RESET_FI2C(1, 5),
+ UNIPHIER_PERI_RESET_FI2C(2, 6),
+ UNIPHIER_PERI_RESET_FI2C(3, 7),
+ UNIPHIER_PERI_RESET_FI2C(4, 8),
+ UNIPHIER_PERI_RESET_FI2C(5, 9),
+ UNIPHIER_PERI_RESET_FI2C(6, 10),
+ { .id = UNIPHIER_RESET_ID_END }
+};
+
+static int uniphier_pro5_peri_reset_probe(struct platform_device *pdev)
+{
+ return uniphier_reset_probe(pdev, uniphier_pro5_peri_reset_data);
+}
+
+static struct platform_driver uniphier_pro5_peri_reset_driver = {
+ .probe = uniphier_pro5_peri_reset_probe,
+ .driver = {
+ .name = "uniphier-pro5-peri-reset",
+ },
+};
+module_platform_driver(uniphier_pro5_peri_reset_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier Peripheral Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 17/21] reset: uniphier: add reset driver for UniPhier ProXstream2/PH1-LD6b SoC |
| Message-ID | <rxcCn-8kL-39@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/reset/uniphier/Kconfig | 4 +++
drivers/reset/uniphier/Makefile | 1 +
drivers/reset/uniphier/reset-uniphier-pxs2.c | 46 ++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
create mode 100644 drivers/reset/uniphier/reset-uniphier-pxs2.c
diff --git a/drivers/reset/uniphier/Kconfig b/drivers/reset/uniphier/Kconfig
index 92d9a5f..022aef4 100644
--- a/drivers/reset/uniphier/Kconfig
+++ b/drivers/reset/uniphier/Kconfig
@@ -22,4 +22,8 @@ config RESET_UNIPHIER_PRO5
tristate "Reset driver for UniPhier PH1-Pro5 SoC"
default ARM
+config RESET_UNIPHIER_PXS2
+ tristate "Reset driver for UniPhier ProXstream2/PH1-LD6b SoC"
+ default ARM
+
endif
diff --git a/drivers/reset/uniphier/Makefile b/drivers/reset/uniphier/Makefile
index 537e3f8..50847db 100644
--- a/drivers/reset/uniphier/Makefile
+++ b/drivers/reset/uniphier/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_RESET_UNIPHIER_LD4) += reset-uniphier-ld4.o
obj-$(CONFIG_RESET_UNIPHIER_PRO4) += reset-uniphier-pro4.o
obj-$(CONFIG_RESET_UNIPHIER_SLD8) += reset-uniphier-sld8.o
obj-$(CONFIG_RESET_UNIPHIER_PRO5) += reset-uniphier-pro5.o
+obj-$(CONFIG_RESET_UNIPHIER_PXS2) += reset-uniphier-pxs2.o
diff --git a/drivers/reset/uniphier/reset-uniphier-pxs2.c b/drivers/reset/uniphier/reset-uniphier-pxs2.c
new file mode 100644
index 0000000..55d7273
--- /dev/null
+++ b/drivers/reset/uniphier/reset-uniphier-pxs2.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "reset-uniphier.h"
+
+static const struct uniphier_reset_data uniphier_pxs2_reset_data[] = {
+ {
+ .id = 7,
+ .reg = 0x2000,
+ .mask = BIT(10),
+ .deassert_val = BIT(10),
+ },
+ { .id = UNIPHIER_RESET_ID_END }
+};
+
+static int uniphier_pxs2_reset_probe(struct platform_device *pdev)
+{
+ return uniphier_reset_probe(pdev, uniphier_pxs2_reset_data);
+}
+
+static struct platform_driver uniphier_pxs2_reset_driver = {
+ .probe = uniphier_pxs2_reset_probe,
+ .driver = {
+ .name = "uniphier-pxs2-reset",
+ },
+};
+module_platform_driver(uniphier_pxs2_reset_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier ProXstream2 Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 05/21] clk: uniphier: add clock driver for UniPhier PH1-sLD8 SoC |
| Message-ID | <rxcCn-8kL-37@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/clk/uniphier/Kconfig | 4 ++
drivers/clk/uniphier/Makefile | 1 +
drivers/clk/uniphier/clk-uniphier-sld8.c | 102 +++++++++++++++++++++++++++++++
3 files changed, 107 insertions(+)
create mode 100644 drivers/clk/uniphier/clk-uniphier-sld8.c
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index d789e26..8e930c3 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -14,4 +14,8 @@ config CLK_UNIPHIER_PRO4
tristate "Clock driver for UniPhier PH1-Pro4 SoC"
default ARM
+config CLK_UNIPHIER_SLD8
+ tristate "Clock driver for UniPhier PH1-sLD8 SoC"
+ default ARM
+
endif
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index ceed615..c7a8390 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -6,3 +6,4 @@ obj-y += clk-uniphier-mux.o
obj-$(CONFIG_CLK_UNIPHIER_LD4) += clk-uniphier-ld4.o
obj-$(CONFIG_CLK_UNIPHIER_PRO4) += clk-uniphier-pro4.o
+obj-$(CONFIG_CLK_UNIPHIER_SLD8) += clk-uniphier-sld8.o
diff --git a/drivers/clk/uniphier/clk-uniphier-sld8.c b/drivers/clk/uniphier/clk-uniphier-sld8.c
new file mode 100644
index 0000000..74574ba
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-sld8.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+static const struct uniphier_clk_data uniphier_sld8_clk_data[] = {
+ {
+ .name = "spll",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "ref",
+ .mult = 64,
+ .div = 1,
+ },
+ },
+ {
+ .name = "upll",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "ref",
+ .mult = 288,
+ .div = 25,
+ },
+ },
+ {
+ .name = "uart",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 0,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 20,
+ },
+ },
+ {
+ .name = "i2c",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 1,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 16,
+ },
+ },
+ {
+ .name = "ehci",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 5,
+ .data.factor = {
+ .parent_name = "upll",
+ .mult = 1,
+ .div = 12,
+ },
+ },
+ {
+ .name = "stdmac",
+ .type = UNIPHIER_CLK_TYPE_GATE,
+ .output_index = 7,
+ .data.gate = {
+ .parent_name = NULL,
+ .reg = 0x2104,
+ .mask = BIT(10),
+ .enable_val = BIT(10),
+ },
+ },
+ { /* sentinel */ }
+};
+
+static int uniphier_sld8_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_sld8_clk_data);
+}
+
+static struct platform_driver uniphier_sld8_clk_driver = {
+ .probe = uniphier_sld8_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-sld8-clk",
+ },
+};
+module_platform_driver(uniphier_sld8_clk_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-sLD8 System Clock Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 02/21] clk: uniphier: add core support for UniPhier clock driver |
| Message-ID | <rxcCo-8kL-47@gated-at.bofh.it> |
| In reply to | #1397915 |
The core support for the clock drivers of all UniPhier SoCs.
This part is the update from the version 2.
https://lkml.org/lkml/2016/5/2/721
After discussing Stephen and Michael, I changed various things
in this version:
- Change to platform drivers instead of OF_CLK_DECLARE
- Split into a core part + SoC drivers
SoC drivers just consist of tables of SoC-specific data.
This allows reviewer to concentrate on the core-part
- Hard-code parent clock names for cascading
Another big change is that the clock drivers are populated
from the parent MFD.
On UniPhier SoCs, registers for clock, reset, and other system
controlling are mixed in one hardware block. It is difficult
to have one independent clock node.
So, I chose to use MFD from which clocks and resets (and
power in the future) are populated.
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
MAINTAINERS | 1 +
drivers/clk/uniphier/Kconfig | 9 +++
drivers/clk/uniphier/Makefile | 5 ++
drivers/clk/uniphier/clk-uniphier-core.c | 99 ++++++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier-fixed-factor.c | 50 ++++++++++++
drivers/clk/uniphier/clk-uniphier-fixed-rate.c | 49 ++++++++++++
drivers/clk/uniphier/clk-uniphier-gate.c | 98 +++++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier-mux.c | 96 +++++++++++++++++++++++
drivers/clk/uniphier/clk-uniphier.h | 89 +++++++++++++++++++++
9 files changed, 496 insertions(+)
create mode 100644 drivers/clk/uniphier/Kconfig
create mode 100644 drivers/clk/uniphier/Makefile
create mode 100644 drivers/clk/uniphier/clk-uniphier-core.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-fixed-factor.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-fixed-rate.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-gate.c
create mode 100644 drivers/clk/uniphier/clk-uniphier-mux.c
create mode 100644 drivers/clk/uniphier/clk-uniphier.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8c987ca..38c6bb5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1727,6 +1727,7 @@ F: arch/arm/mach-uniphier/
F: arch/arm/mm/cache-uniphier.c
F: arch/arm64/boot/dts/socionext/
F: drivers/bus/uniphier-system-bus.c
+F: drivers/clk/uniphier/
F: drivers/i2c/busses/i2c-uniphier*
F: drivers/mfd/uniphier-mfd.c
F: drivers/mmc/host/uniphier-sd.c
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
new file mode 100644
index 0000000..f36529a
--- /dev/null
+++ b/drivers/clk/uniphier/Kconfig
@@ -0,0 +1,9 @@
+menuconfig CLK_UNIPHIER
+ bool "Clock drivers for UniPhier SoCs"
+ depends on (ARCH_UNIPHIER && MFD_UNIPHIER) || COMPILE_TEST
+ depends on OF && MFD_CORE && MFD_SYSCON
+ default ARCH_UNIPHIER && MFD_UNIPHIER
+
+if CLK_UNIPHIER
+
+endif
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
new file mode 100644
index 0000000..4d6daa8
--- /dev/null
+++ b/drivers/clk/uniphier/Makefile
@@ -0,0 +1,5 @@
+obj-y += clk-uniphier-core.o
+obj-y += clk-uniphier-fixed-factor.o
+obj-y += clk-uniphier-fixed-rate.o
+obj-y += clk-uniphier-gate.o
+obj-y += clk-uniphier-mux.o
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
new file mode 100644
index 0000000..72953a0
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+static struct clk_hw *uniphier_clk_register(struct device *dev,
+ struct regmap *regmap,
+ const struct uniphier_clk_data *data)
+{
+ switch (data->type) {
+ case UNIPHIER_CLK_TYPE_FIXED_FACTOR:
+ return uniphier_clk_register_fixed_factor(dev, data->name,
+ &data->data.factor);
+ case UNIPHIER_CLK_TYPE_FIXED_RATE:
+ return uniphier_clk_register_fixed_rate(dev, data->name,
+ &data->data.rate);
+ case UNIPHIER_CLK_TYPE_GATE:
+ return uniphier_clk_register_gate(dev, regmap, data->name,
+ &data->data.gate);
+ case UNIPHIER_CLK_TYPE_MUX:
+ return uniphier_clk_register_mux(dev, regmap, data->name,
+ &data->data.mux);
+ default:
+ WARN(1, "unsupported clock type\n");
+ return ERR_PTR(-EINVAL);
+ }
+}
+
+int uniphier_clk_probe(struct platform_device *pdev,
+ const struct uniphier_clk_data *data)
+{
+ struct device *dev = &pdev->dev;
+ struct clk_hw_onecell_data *hw_data;
+ struct regmap *regmap;
+ const struct uniphier_clk_data *p;
+ int clk_num = 0;
+
+ /* parent should be MFD and syscon node */
+ regmap = syscon_node_to_regmap(dev->parent->of_node);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "failed to get regmap\n");
+ return PTR_ERR(regmap);
+ }
+
+ for (p = data; p->name; p++)
+ clk_num = max(clk_num, p->output_index + 1);
+
+ hw_data = devm_kzalloc(dev,
+ sizeof(*hw_data) + clk_num * sizeof(struct clk_hw *),
+ GFP_KERNEL);
+ if (!hw_data)
+ return -ENOMEM;
+
+ hw_data->num = clk_num;
+
+ for (p = data; p->name; p++) {
+ struct clk_hw *hw;
+
+ dev_dbg(dev, "register %s (index=%d)\n", p->name,
+ p->output_index);
+ hw = uniphier_clk_register(dev, regmap, p);
+ if (IS_ERR(hw)) {
+ dev_err(dev, "failed to register %s\n", p->name);
+ return PTR_ERR(hw);
+ }
+
+ if (p->output_index >= 0)
+ hw_data->hws[p->output_index] = hw;
+ }
+
+ return of_clk_add_hw_provider(dev->parent->of_node,
+ of_clk_hw_onecell_get, hw_data);
+}
+EXPORT_SYMBOL_GPL(uniphier_clk_probe);
+
+int uniphier_clk_remove(struct platform_device *pdev)
+{
+ of_clk_del_provider(pdev->dev.parent->of_node);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(uniphier_clk_remove);
diff --git a/drivers/clk/uniphier/clk-uniphier-fixed-factor.c b/drivers/clk/uniphier/clk-uniphier-fixed-factor.c
new file mode 100644
index 0000000..2a2d5bd
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-fixed-factor.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+
+#include "clk-uniphier.h"
+
+struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
+ const char *name,
+ const struct uniphier_clk_fixed_factor_data *data)
+{
+ struct clk_fixed_factor *fix;
+ struct clk_init_data init;
+ int ret;
+
+ fix = devm_kzalloc(dev, sizeof(*fix), GFP_KERNEL);
+ if (!fix)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_fixed_factor_ops;
+ init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
+ init.flags |= CLK_IS_BASIC;
+ init.parent_names = data->parent_name ? &data->parent_name : NULL;
+ init.num_parents = data->parent_name ? 1 : 0;
+
+ fix->mult = data->mult;
+ fix->div = data->div;
+ fix->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &fix->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &fix->hw;
+}
+EXPORT_SYMBOL_GPL(uniphier_clk_register_fixed_factor);
diff --git a/drivers/clk/uniphier/clk-uniphier-fixed-rate.c b/drivers/clk/uniphier/clk-uniphier-fixed-rate.c
new file mode 100644
index 0000000..1fc6258
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-fixed-rate.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+
+#include "clk-uniphier.h"
+
+struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
+ const char *name,
+ const struct uniphier_clk_fixed_rate_data *data)
+{
+ struct clk_fixed_rate *fixed;
+ struct clk_init_data init;
+ int ret;
+
+ /* allocate fixed-rate clock */
+ fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
+ if (!fixed)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &clk_fixed_rate_ops;
+ init.flags = CLK_IS_BASIC;
+ init.parent_names = NULL;
+ init.num_parents = 0;
+
+ fixed->fixed_rate = data->fixed_rate;
+ fixed->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &fixed->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &fixed->hw;
+}
+EXPORT_SYMBOL_GPL(uniphier_clk_register_fixed_rate);
diff --git a/drivers/clk/uniphier/clk-uniphier-gate.c b/drivers/clk/uniphier/clk-uniphier-gate.c
new file mode 100644
index 0000000..c42b0a8
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-gate.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+#include "clk-uniphier.h"
+
+struct uniphier_clk_gate {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ unsigned int reg;
+ unsigned int mask;
+ unsigned int enable_val;
+};
+
+#define to_uniphier_clk_gate(_hw) \
+ container_of(_hw, struct uniphier_clk_gate, hw)
+
+static int uniphier_clk_gate_enable(struct clk_hw *hw)
+{
+ struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
+
+ return regmap_write_bits(gate->regmap, gate->reg, gate->mask,
+ gate->enable_val);
+}
+
+static void uniphier_clk_gate_disable(struct clk_hw *hw)
+{
+ struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
+
+ if (regmap_write_bits(gate->regmap, gate->reg, gate->mask,
+ ~gate->enable_val) < 0)
+ pr_warn("regmap_write_bits failed. clk may not be disabled\n");
+}
+
+static int uniphier_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct uniphier_clk_gate *gate = to_uniphier_clk_gate(hw);
+ unsigned int val;
+
+ if (regmap_read(gate->regmap, gate->reg, &val) < 0)
+ pr_warn("regmap_read failed. is_enabled() may return wrong result\n");
+
+ return (val & gate->mask) == gate->enable_val;
+}
+
+static const struct clk_ops uniphier_clk_gate_ops = {
+ .enable = uniphier_clk_gate_enable,
+ .disable = uniphier_clk_gate_disable,
+ .is_enabled = uniphier_clk_gate_is_enabled,
+};
+
+struct clk_hw *uniphier_clk_register_gate(struct device *dev,
+ struct regmap *regmap,
+ const char *name,
+ const struct uniphier_clk_gate_data *data)
+{
+ struct uniphier_clk_gate *gate;
+ struct clk_init_data init;
+ int ret;
+
+ gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &uniphier_clk_gate_ops;
+ init.flags = data->parent_name ? CLK_SET_RATE_PARENT : 0;
+ init.parent_names = data->parent_name ? &data->parent_name : NULL;
+ init.num_parents = data->parent_name ? 1 : 0;
+
+ gate->regmap = regmap;
+ gate->reg = data->reg;
+ gate->mask = data->mask;
+ gate->enable_val = data->enable_val;
+ gate->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &gate->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &gate->hw;
+}
+EXPORT_SYMBOL_GPL(uniphier_clk_register_gate);
diff --git a/drivers/clk/uniphier/clk-uniphier-mux.c b/drivers/clk/uniphier/clk-uniphier-mux.c
new file mode 100644
index 0000000..e18d5d3
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-mux.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+#include "clk-uniphier.h"
+
+struct uniphier_clk_mux {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ unsigned int reg;
+ const unsigned int *masks;
+ const unsigned int *vals;
+};
+
+#define to_uniphier_clk_mux(_hw) container_of(_hw, struct uniphier_clk_mux, hw)
+
+static int uniphier_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
+
+ return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index],
+ mux->vals[index]);
+}
+
+static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
+ int num_parents = clk_hw_get_num_parents(hw);
+ int ret;
+ u32 val;
+ u8 i;
+
+ ret = regmap_read(mux->regmap, mux->reg, &val);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < num_parents; i++)
+ if ((mux->masks[i] & val) == mux->vals[i])
+ return i;
+
+ return -EINVAL;
+}
+
+static const struct clk_ops uniphier_clk_mux_ops = {
+ .determine_rate = __clk_mux_determine_rate,
+ .set_parent = uniphier_clk_mux_set_parent,
+ .get_parent = uniphier_clk_mux_get_parent,
+};
+
+struct clk_hw *uniphier_clk_register_mux(struct device *dev,
+ struct regmap *regmap,
+ const char *name,
+ const struct uniphier_clk_mux_data *data)
+{
+ struct uniphier_clk_mux *mux;
+ struct clk_init_data init;
+ int ret;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &uniphier_clk_mux_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.parent_names = data->parent_names;
+ init.num_parents = data->num_parents,
+
+ mux->regmap = regmap;
+ mux->reg = data->reg;
+ mux->masks = data->masks;
+ mux->vals = data->vals;
+ mux->hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &mux->hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return &mux->hw;
+}
+EXPORT_SYMBOL_GPL(uniphier_clk_register_mux);
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
new file mode 100644
index 0000000..d5f3948
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CLK_UNIPHIER_H__
+#define __CLK_UNIPHIER_H__
+
+struct clk_hw;
+struct device;
+struct platform_device;
+struct regmap;
+
+#define UNIPHIER_CLK_MUX_MAX_PARENTS 8
+
+enum uniphier_clk_type {
+ UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ UNIPHIER_CLK_TYPE_FIXED_RATE,
+ UNIPHIER_CLK_TYPE_GATE,
+ UNIPHIER_CLK_TYPE_MUX,
+};
+
+struct uniphier_clk_fixed_factor_data {
+ const char *parent_name;
+ unsigned int mult;
+ unsigned int div;
+};
+
+struct uniphier_clk_fixed_rate_data {
+ unsigned long fixed_rate;
+};
+
+struct uniphier_clk_gate_data {
+ const char *parent_name;
+ unsigned int reg;
+ unsigned int mask;
+ unsigned int enable_val;
+};
+
+struct uniphier_clk_mux_data {
+ const char *parent_names[UNIPHIER_CLK_MUX_MAX_PARENTS];
+ unsigned int num_parents;
+ unsigned int reg;
+ unsigned int masks[UNIPHIER_CLK_MUX_MAX_PARENTS];
+ unsigned int vals[UNIPHIER_CLK_MUX_MAX_PARENTS];
+};
+
+struct uniphier_clk_data {
+ const char *name;
+ enum uniphier_clk_type type;
+ int output_index;
+ union {
+ struct uniphier_clk_fixed_factor_data factor;
+ struct uniphier_clk_fixed_rate_data rate;
+ struct uniphier_clk_gate_data gate;
+ struct uniphier_clk_mux_data mux;
+ } data;
+};
+
+struct clk_hw *uniphier_clk_register_fixed_factor(struct device *dev,
+ const char *name,
+ const struct uniphier_clk_fixed_factor_data *data);
+struct clk_hw *uniphier_clk_register_fixed_rate(struct device *dev,
+ const char *name,
+ const struct uniphier_clk_fixed_rate_data *data);
+struct clk_hw *uniphier_clk_register_gate(struct device *dev,
+ struct regmap *regmap,
+ const char *name,
+ const struct uniphier_clk_gate_data *data);
+struct clk_hw *uniphier_clk_register_mux(struct device *dev,
+ struct regmap *regmap,
+ const char *name,
+ const struct uniphier_clk_mux_data *data);
+
+int uniphier_clk_probe(struct platform_device *pdev,
+ const struct uniphier_clk_data *data);
+int uniphier_clk_remove(struct platform_device *pdev);
+
+#endif /* __CLK_UNIPHIER_H__ */
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 10/21] clk: uniphier: add clock driver for Media I/O block on UniPhier SoCs |
| Message-ID | <rxcCo-8kL-53@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/clk/uniphier/Kconfig | 4 +
drivers/clk/uniphier/Makefile | 2 +
drivers/clk/uniphier/clk-uniphier-mio.c | 215 ++++++++++++++++++++++++++++++++
3 files changed, 221 insertions(+)
create mode 100644 drivers/clk/uniphier/clk-uniphier-mio.c
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index 6e0a311..895c4a0 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -34,4 +34,8 @@ config CLK_UNIPHIER_LD20
tristate "Clock driver for UniPhier PH1-LD20 SoC"
default ARM64
+config CLK_UNIPHIER_MIO
+ tristate "Clock driver for UniPhier Media I/O block"
+ default y
+
endif
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index 59272a6..ae71f04 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -11,3 +11,5 @@ obj-$(CONFIG_CLK_UNIPHIER_PRO5) += clk-uniphier-pro5.o
obj-$(CONFIG_CLK_UNIPHIER_PXS2) += clk-uniphier-pxs2.o
obj-$(CONFIG_CLK_UNIPHIER_LD11) += clk-uniphier-ld11.o
obj-$(CONFIG_CLK_UNIPHIER_LD20) += clk-uniphier-ld20.o
+
+obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
new file mode 100644
index 0000000..28691b7
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+#define UNIPHIER_MIO_CLK_SD_FIXED \
+ { \
+ .name = "sd-44m", \
+ .type = UNIPHIER_CLK_TYPE_FIXED_RATE, \
+ .output_index = -1, \
+ .data.rate = { \
+ .fixed_rate = 44444444, \
+ }, \
+ }, \
+ { \
+ .name = "sd-33m", \
+ .type = UNIPHIER_CLK_TYPE_FIXED_RATE, \
+ .output_index = -1, \
+ .data.rate = { \
+ .fixed_rate = 33333333, \
+ }, \
+ }, \
+ { \
+ .name = "sd-50m", \
+ .type = UNIPHIER_CLK_TYPE_FIXED_RATE, \
+ .output_index = -1, \
+ .data.rate = { \
+ .fixed_rate = 50000000, \
+ }, \
+ }, \
+ { \
+ .name = "sd-67m", \
+ .type = UNIPHIER_CLK_TYPE_FIXED_RATE, \
+ .output_index = -1, \
+ .data.rate = { \
+ .fixed_rate = 66666666, \
+ }, \
+ }, \
+ { \
+ .name = "sd-100m", \
+ .type = UNIPHIER_CLK_TYPE_FIXED_RATE, \
+ .output_index = -1, \
+ .data.rate = { \
+ .fixed_rate = 100000000, \
+ }, \
+ }, \
+ { \
+ .name = "sd-40m", \
+ .type = UNIPHIER_CLK_TYPE_FIXED_RATE, \
+ .output_index = -1, \
+ .data.rate = { \
+ .fixed_rate = 40000000, \
+ }, \
+ }, \
+ { \
+ .name = "sd-25m", \
+ .type = UNIPHIER_CLK_TYPE_FIXED_RATE, \
+ .output_index = -1, \
+ .data.rate = { \
+ .fixed_rate = 25000000, \
+ }, \
+ }, \
+ { \
+ .name = "sd-22m", \
+ .type = UNIPHIER_CLK_TYPE_FIXED_RATE, \
+ .output_index = -1, \
+ .data.rate = { \
+ .fixed_rate = 22222222, \
+ }, \
+ }
+
+#define UNIPHIER_MIO_CLK_SD(ch, index) \
+ { \
+ .name = "sd" #ch "-sel", \
+ .type = UNIPHIER_CLK_TYPE_MUX, \
+ .output_index = -1, \
+ .data.mux = { \
+ .parent_names = { \
+ "sd-44m", \
+ "sd-33m", \
+ "sd-50m", \
+ "sd-67m", \
+ "sd-100m", \
+ "sd-40m", \
+ "sd-25m", \
+ "sd-22m", \
+ }, \
+ .num_parents = 8, \
+ .reg = 0x30 + 0x200 * ch, \
+ .masks = { \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00031000, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ 0x00001300, \
+ }, \
+ .vals = { \
+ 0x00000000, \
+ 0x00010000, \
+ 0x00020000, \
+ 0x00030000, \
+ 0x00001000, \
+ 0x00001100, \
+ 0x00001200, \
+ 0x00001300, \
+ }, \
+ }, \
+ }, \
+ { \
+ .name = "sd" #ch, \
+ .type = UNIPHIER_CLK_TYPE_GATE, \
+ .output_index = (index), \
+ .data.gate = { \
+ .parent_name = "sd" #ch "-sel", \
+ .reg = 0x20 + 0x200 * ch, \
+ .mask = BIT(8), \
+ .enable_val = BIT(8), \
+ }, \
+ }
+
+#define UNIPHIER_MIO_CLK_EHCI(ch, index) \
+ { \
+ .name = "ehci" #ch, \
+ .type = UNIPHIER_CLK_TYPE_GATE, \
+ .output_index = (index), \
+ .data.gate = { \
+ .parent_name = "ehci", \
+ .reg = 0x20 + 0x200 * ch, \
+ .mask = BIT(29) | BIT(28), \
+ .enable_val = BIT(29) | BIT(28), \
+ }, \
+ }
+
+#define UNIPHIER_MIO_CLK_DMAC(index) \
+ { \
+ .name = "miodmac", \
+ .type = UNIPHIER_CLK_TYPE_GATE, \
+ .output_index = (index), \
+ .data.gate = { \
+ .parent_name = "stdmac", \
+ .reg = 0x20, \
+ .mask = BIT(25), \
+ .enable_val = BIT(25), \
+ }, \
+ }
+
+static const struct uniphier_clk_data uniphier_ld4_mio_clk_data[] = {
+ UNIPHIER_MIO_CLK_SD_FIXED,
+ UNIPHIER_MIO_CLK_SD(0, 0),
+ UNIPHIER_MIO_CLK_SD(1, 1),
+ UNIPHIER_MIO_CLK_SD(2, 2), /* for Pro4 */
+ UNIPHIER_MIO_CLK_DMAC(3),
+ UNIPHIER_MIO_CLK_EHCI(0, 4),
+ UNIPHIER_MIO_CLK_EHCI(1, 5),
+ UNIPHIER_MIO_CLK_EHCI(2, 6), /* for LD4/sLD8 */
+ { /* sentinel */ }
+};
+
+static int uniphier_ld4_mio_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_ld4_mio_clk_data);
+}
+
+static struct platform_driver uniphier_ld4_mio_clk_driver = {
+ .probe = uniphier_ld4_mio_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-ld4-mio-clk",
+ },
+};
+module_platform_driver(uniphier_ld4_mio_clk_driver);
+
+static const struct uniphier_clk_data uniphier_pro5_mio_clk_data[] = {
+ UNIPHIER_MIO_CLK_SD_FIXED,
+ UNIPHIER_MIO_CLK_SD(0, 0),
+ UNIPHIER_MIO_CLK_SD(1, 1),
+ { /* sentinel */ }
+};
+
+static int uniphier_pro5_mio_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_pro5_mio_clk_data);
+}
+
+static struct platform_driver uniphier_pro5_mio_clk_driver = {
+ .probe = uniphier_pro5_mio_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-pro5-mio-clk",
+ },
+};
+module_platform_driver(uniphier_pro5_mio_clk_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier Media I/O Clock Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 01/21] mfd: uniphier: add UniPhier MFD driver |
| Message-ID | <rxcCp-8kL-73@gated-at.bofh.it> |
| In reply to | #1397915 |
This MFD driver populates child devices such clock, reset, and other
system controlling blocks.
On UniPhier SoCs, one system control block contains various registers
for clock, reset, and others in it. So, it is not reasonable to have
separate DT nodes for different sub-systems.
This MFD approach modifies Device Tree source just once for adding
an MFD node.
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
MAINTAINERS | 1 +
drivers/mfd/Kconfig | 9 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/uniphier-mfd.c | 214 +++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 225 insertions(+)
create mode 100644 drivers/mfd/uniphier-mfd.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 87b2ddd..8c987ca 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1728,6 +1728,7 @@ F: arch/arm/mm/cache-uniphier.c
F: arch/arm64/boot/dts/socionext/
F: drivers/bus/uniphier-system-bus.c
F: drivers/i2c/busses/i2c-uniphier*
+F: drivers/mfd/uniphier-mfd.c
F: drivers/mmc/host/uniphier-sd.c
F: drivers/pinctrl/uniphier/
F: drivers/tty/serial/8250/8250_uniphier.c
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index eea61e3..ea85862 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -892,6 +892,15 @@ config MFD_SKY81452
This driver can also be built as a module. If so, the module
will be called sky81452.
+config MFD_UNIPHIER
+ tristate "Socionext UniPhier MFD"
+ depends on ARCH_UNIPHIER || COMPILE_TEST
+ default ARCH_UNIPHIER
+ select MFD_CORE
+ help
+ Support for the System Control Block, Media I/O Control Block,
+ Peripheral Control Block available on UniPhier SoCs.
+
config MFD_SMSC
bool "SMSC ECE1099 series chips"
depends on I2C=y
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 5eaa6465d..5e8c20c 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -198,6 +198,7 @@ obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
obj-$(CONFIG_MFD_DLN2) += dln2.o
obj-$(CONFIG_MFD_RT5033) += rt5033.o
obj-$(CONFIG_MFD_SKY81452) += sky81452.o
+obj-$(CONFIG_MFD_UNIPHIER) += uniphier-mfd.o
intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o
diff --git a/drivers/mfd/uniphier-mfd.c b/drivers/mfd/uniphier-mfd.c
new file mode 100644
index 0000000..7f01d64
--- /dev/null
+++ b/drivers/mfd/uniphier-mfd.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+static const struct mfd_cell uniphier_ld4_sysctrl_cells[] = {
+ { .name = "uniphier-ld4-clk" },
+ { .name = "uniphier-ld4-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_pro4_sysctrl_cells[] = {
+ { .name = "uniphier-pro4-clk" },
+ { .name = "uniphier-pro4-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_sld8_sysctrl_cells[] = {
+ { .name = "uniphier-sld8-clk" },
+ { .name = "uniphier-sld8-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_pro5_sysctrl_cells[] = {
+ { .name = "uniphier-pro5-clk" },
+ { .name = "uniphier-pro5-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_pxs2_sysctrl_cells[] = {
+ { .name = "uniphier-pxs2-clk" },
+ { .name = "uniphier-pxs2-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_ld11_sysctrl_cells[] = {
+ { .name = "uniphier-ld11-clk" },
+ { .name = "uniphier-ld11-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_ld20_sysctrl_cells[] = {
+ { .name = "uniphier-ld20-clk" },
+ { .name = "uniphier-ld20-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_ld4_mioctrl_cells[] = {
+ { .name = "uniphier-ld4-mio-clk" },
+ { .name = "uniphier-ld4-mio-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_pro5_mioctrl_cells[] = {
+ { .name = "uniphier-pro5-mio-clk" },
+ { .name = "uniphier-pro5-mio-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_ld4_perictrl_cells[] = {
+ { .name = "uniphier-ld4-peri-clk" },
+ { .name = "uniphier-ld4-peri-reset" },
+ { /* sentinel */ }
+};
+
+static const struct mfd_cell uniphier_pro4_perictrl_cells[] = {
+ { .name = "uniphier-pro4-peri-clk" },
+ { .name = "uniphier-pro4-peri-reset" },
+ { /* sentinel */ }
+};
+
+static const struct of_device_id uniphier_mfd_match[] = {
+ /* System Control */
+ {
+ .compatible = "socionext,uniphier-ld4-sysctrl",
+ .data = uniphier_ld4_sysctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-sysctrl",
+ .data = uniphier_pro4_sysctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-sysctrl",
+ .data = uniphier_sld8_sysctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-sysctrl",
+ .data = uniphier_pro5_sysctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-sysctrl",
+ .data = uniphier_pxs2_sysctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-sysctrl",
+ .data = uniphier_ld11_sysctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-sysctrl",
+ .data = uniphier_ld20_sysctrl_cells,
+ },
+ /* Media I/O */
+ {
+ .compatible = "socionext,uniphier-ld4-mioctrl",
+ .data = uniphier_ld4_mioctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-mioctrl",
+ .data = uniphier_ld4_mioctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-mioctrl",
+ .data = uniphier_ld4_mioctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-mioctrl",
+ .data = uniphier_pro5_mioctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-mioctrl",
+ .data = uniphier_pro5_mioctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-mioctrl",
+ .data = uniphier_ld4_mioctrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-mioctrl",
+ .data = uniphier_pro5_mioctrl_cells,
+ },
+ /* Peripheral Control */
+ {
+ .compatible = "socionext,uniphier-ld4-perictrl",
+ .data = uniphier_ld4_perictrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-sld8-perictrl",
+ .data = uniphier_ld4_perictrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-pro4-perictrl",
+ .data = uniphier_pro4_perictrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-pro5-perictrl",
+ .data = uniphier_pro4_perictrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-pxs2-perictrl",
+ .data = uniphier_pro4_perictrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-ld11-perictrl",
+ .data = uniphier_pro4_perictrl_cells,
+ },
+ {
+ .compatible = "socionext,uniphier-ld20-perictrl",
+ .data = uniphier_pro4_perictrl_cells,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, uniphier_mfd_match);
+
+static int uniphier_mfd_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ const struct mfd_cell *cell;
+ int ret;
+ int n_cells = 0;
+
+ match = of_match_node(uniphier_mfd_match, pdev->dev.of_node);
+ if (!match)
+ return -ENODEV;
+
+ cell = match->data;
+
+ for (; cell->name; cell++)
+ n_cells++;
+
+ ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, match->data,
+ n_cells, NULL, 0, NULL);
+ if (ret)
+ dev_err(&pdev->dev, "failed to add MFD devices\n");
+
+ return ret;
+}
+
+static struct platform_driver uniphier_mfd_driver = {
+ .probe = uniphier_mfd_probe,
+ .driver = {
+ .name = "uniphier-mfd",
+ .of_match_table = uniphier_mfd_match,
+ },
+};
+module_platform_driver(uniphier_mfd_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier SoC MFD Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-05-10 13:30 +0200 |
| Subject | Re: [RFC PATCH 01/21] mfd: uniphier: add UniPhier MFD driver |
| Message-ID | <rxe1s-1qz-13@gated-at.bofh.it> |
| In reply to | #1397927 |
On Tue, 10 May 2016, Masahiro Yamada wrote:
> This MFD driver populates child devices such clock, reset, and other
> system controlling blocks.
>
> On UniPhier SoCs, one system control block contains various registers
> for clock, reset, and others in it. So, it is not reasonable to have
> separate DT nodes for different sub-systems.
>
> This MFD approach modifies Device Tree source just once for adding
> an MFD node.
>
> This series is just for review.
> Please do not apply this patch.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
>
> MAINTAINERS | 1 +
> drivers/mfd/Kconfig | 9 ++
> drivers/mfd/Makefile | 1 +
> drivers/mfd/uniphier-mfd.c | 214 +++++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 225 insertions(+)
> create mode 100644 drivers/mfd/uniphier-mfd.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 87b2ddd..8c987ca 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1728,6 +1728,7 @@ F: arch/arm/mm/cache-uniphier.c
> F: arch/arm64/boot/dts/socionext/
> F: drivers/bus/uniphier-system-bus.c
> F: drivers/i2c/busses/i2c-uniphier*
> +F: drivers/mfd/uniphier-mfd.c
> F: drivers/mmc/host/uniphier-sd.c
> F: drivers/pinctrl/uniphier/
> F: drivers/tty/serial/8250/8250_uniphier.c
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index eea61e3..ea85862 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -892,6 +892,15 @@ config MFD_SKY81452
> This driver can also be built as a module. If so, the module
> will be called sky81452.
>
> +config MFD_UNIPHIER
> + tristate "Socionext UniPhier MFD"
> + depends on ARCH_UNIPHIER || COMPILE_TEST
> + default ARCH_UNIPHIER
> + select MFD_CORE
> + help
> + Support for the System Control Block, Media I/O Control Block,
> + Peripheral Control Block available on UniPhier SoCs.
> +
> config MFD_SMSC
> bool "SMSC ECE1099 series chips"
> depends on I2C=y
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 5eaa6465d..5e8c20c 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -198,6 +198,7 @@ obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
> obj-$(CONFIG_MFD_DLN2) += dln2.o
> obj-$(CONFIG_MFD_RT5033) += rt5033.o
> obj-$(CONFIG_MFD_SKY81452) += sky81452.o
> +obj-$(CONFIG_MFD_UNIPHIER) += uniphier-mfd.o
>
> intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
> intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o
> diff --git a/drivers/mfd/uniphier-mfd.c b/drivers/mfd/uniphier-mfd.c
> new file mode 100644
> index 0000000..7f01d64
> --- /dev/null
> +++ b/drivers/mfd/uniphier-mfd.c
> @@ -0,0 +1,214 @@
> +/*
> + * Copyright (C) 2016 Socionext Inc.
> + * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/mfd/core.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +static const struct mfd_cell uniphier_ld4_sysctrl_cells[] = {
> + { .name = "uniphier-ld4-clk" },
> + { .name = "uniphier-ld4-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_pro4_sysctrl_cells[] = {
> + { .name = "uniphier-pro4-clk" },
> + { .name = "uniphier-pro4-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_sld8_sysctrl_cells[] = {
> + { .name = "uniphier-sld8-clk" },
> + { .name = "uniphier-sld8-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_pro5_sysctrl_cells[] = {
> + { .name = "uniphier-pro5-clk" },
> + { .name = "uniphier-pro5-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_pxs2_sysctrl_cells[] = {
> + { .name = "uniphier-pxs2-clk" },
> + { .name = "uniphier-pxs2-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_ld11_sysctrl_cells[] = {
> + { .name = "uniphier-ld11-clk" },
> + { .name = "uniphier-ld11-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_ld20_sysctrl_cells[] = {
> + { .name = "uniphier-ld20-clk" },
> + { .name = "uniphier-ld20-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_ld4_mioctrl_cells[] = {
> + { .name = "uniphier-ld4-mio-clk" },
> + { .name = "uniphier-ld4-mio-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_pro5_mioctrl_cells[] = {
> + { .name = "uniphier-pro5-mio-clk" },
> + { .name = "uniphier-pro5-mio-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_ld4_perictrl_cells[] = {
> + { .name = "uniphier-ld4-peri-clk" },
> + { .name = "uniphier-ld4-peri-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct mfd_cell uniphier_pro4_perictrl_cells[] = {
> + { .name = "uniphier-pro4-peri-clk" },
> + { .name = "uniphier-pro4-peri-reset" },
> + { /* sentinel */ }
> +};
> +
> +static const struct of_device_id uniphier_mfd_match[] = {
> + /* System Control */
> + {
> + .compatible = "socionext,uniphier-ld4-sysctrl",
> + .data = uniphier_ld4_sysctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-pro4-sysctrl",
> + .data = uniphier_pro4_sysctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-sld8-sysctrl",
> + .data = uniphier_sld8_sysctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-pro5-sysctrl",
> + .data = uniphier_pro5_sysctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-pxs2-sysctrl",
> + .data = uniphier_pxs2_sysctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-ld11-sysctrl",
> + .data = uniphier_ld11_sysctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-ld20-sysctrl",
> + .data = uniphier_ld20_sysctrl_cells,
> + },
> + /* Media I/O */
> + {
> + .compatible = "socionext,uniphier-ld4-mioctrl",
> + .data = uniphier_ld4_mioctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-pro4-mioctrl",
> + .data = uniphier_ld4_mioctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-sld8-mioctrl",
> + .data = uniphier_ld4_mioctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-pro5-mioctrl",
> + .data = uniphier_pro5_mioctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-pxs2-mioctrl",
> + .data = uniphier_pro5_mioctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-ld11-mioctrl",
> + .data = uniphier_ld4_mioctrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-ld20-mioctrl",
> + .data = uniphier_pro5_mioctrl_cells,
> + },
> + /* Peripheral Control */
> + {
> + .compatible = "socionext,uniphier-ld4-perictrl",
> + .data = uniphier_ld4_perictrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-sld8-perictrl",
> + .data = uniphier_ld4_perictrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-pro4-perictrl",
> + .data = uniphier_pro4_perictrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-pro5-perictrl",
> + .data = uniphier_pro4_perictrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-pxs2-perictrl",
> + .data = uniphier_pro4_perictrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-ld11-perictrl",
> + .data = uniphier_pro4_perictrl_cells,
> + },
> + {
> + .compatible = "socionext,uniphier-ld20-perictrl",
> + .data = uniphier_pro4_perictrl_cells,
> + },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, uniphier_mfd_match);
NACK. Please do not mix MFD and DT registration.
> +static int uniphier_mfd_probe(struct platform_device *pdev)
> +{
> + const struct of_device_id *match;
> + const struct mfd_cell *cell;
> + int ret;
> + int n_cells = 0;
> +
> + match = of_match_node(uniphier_mfd_match, pdev->dev.of_node);
> + if (!match)
> + return -ENODEV;
> +
> + cell = match->data;
> +
> + for (; cell->name; cell++)
> + n_cells++;
> +
> + ret = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, match->data,
> + n_cells, NULL, 0, NULL);
> + if (ret)
> + dev_err(&pdev->dev, "failed to add MFD devices\n");
> +
> + return ret;
> +}
This driver is not required.
I think you just need to use "simple-mfd".
> +static struct platform_driver uniphier_mfd_driver = {
> + .probe = uniphier_mfd_probe,
> + .driver = {
> + .name = "uniphier-mfd",
> + .of_match_table = uniphier_mfd_match,
> + },
> +};
> +module_platform_driver(uniphier_mfd_driver);
> +
> +MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
> +MODULE_DESCRIPTION("UniPhier SoC MFD Driver");
> +MODULE_LICENSE("GPL");
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-11 04:00 +0200 |
| Subject | Re: [RFC PATCH 01/21] mfd: uniphier: add UniPhier MFD driver |
| Message-ID | <rxrBo-6tv-5@gated-at.bofh.it> |
| In reply to | #1398001 |
Hi Lee,
2016-05-10 20:26 GMT+09:00 Lee Jones <lee.jones@linaro.org>:
>> +};
>> +MODULE_DEVICE_TABLE(of, uniphier_mfd_match);
>
> NACK. Please do not mix MFD and DT registration.
OK, thanks for review.
My basic thought was:
- Add an MFD node to my DTS only once.
If I need to expand it in the future, I will just
need to modify drivers/mtd/uniphier-mfd.c.
It is just kernel-internal modification, so it does not
bother DT binding at all.
- Simplify the node topology of DTS.
--
Best Regards
Masahiro Yamada
[toc] | [prev] | [next] | [standalone]
| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2016-05-11 09:40 +0200 |
| Subject | Re: [RFC PATCH 01/21] mfd: uniphier: add UniPhier MFD driver |
| Message-ID | <rxwUp-3wW-1@gated-at.bofh.it> |
| In reply to | #1398629 |
On Wed, 11 May 2016, Masahiro Yamada wrote: > Hi Lee, > > 2016-05-10 20:26 GMT+09:00 Lee Jones <lee.jones@linaro.org>: > >> +}; > >> +MODULE_DEVICE_TABLE(of, uniphier_mfd_match); > > > > NACK. Please do not mix MFD and DT registration. > > OK, thanks for review. > > > My basic thought was: > > - Add an MFD node to my DTS only once. > If I need to expand it in the future, I will just > need to modify drivers/mtd/uniphier-mfd.c. > It is just kernel-internal modification, so it does not > bother DT binding at all. > > - Simplify the node topology of DTS. Just describe the hardware in DT. If you do so accurately, there should be no requirement to change it (in theory). -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 07/21] clk: uniphier: add clock driver for UniPhier ProXstream2/PH1-LD6b SoC |
| Message-ID | <rxcCp-8kL-75@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/clk/uniphier/Kconfig | 4 ++
drivers/clk/uniphier/Makefile | 1 +
drivers/clk/uniphier/clk-uniphier-pxs2.c | 83 ++++++++++++++++++++++++++++++++
3 files changed, 88 insertions(+)
create mode 100644 drivers/clk/uniphier/clk-uniphier-pxs2.c
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index de3fada..d4a3d55 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -22,4 +22,8 @@ config CLK_UNIPHIER_PRO5
tristate "Clock driver for UniPhier PH1-Pro5 SoC"
default ARM
+config CLK_UNIPHIER_PXS2
+ tristate "Clock driver for UniPhier ProXstream2/PH1-LD6b SoC"
+ default ARM
+
endif
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index d1edf30..20a274f 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_UNIPHIER_LD4) += clk-uniphier-ld4.o
obj-$(CONFIG_CLK_UNIPHIER_PRO4) += clk-uniphier-pro4.o
obj-$(CONFIG_CLK_UNIPHIER_SLD8) += clk-uniphier-sld8.o
obj-$(CONFIG_CLK_UNIPHIER_PRO5) += clk-uniphier-pro5.o
+obj-$(CONFIG_CLK_UNIPHIER_PXS2) += clk-uniphier-pxs2.o
diff --git a/drivers/clk/uniphier/clk-uniphier-pxs2.c b/drivers/clk/uniphier/clk-uniphier-pxs2.c
new file mode 100644
index 0000000..07f7969
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-pxs2.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+static const struct uniphier_clk_data uniphier_pxs2_clk_data[] = {
+ {
+ .name = "spll",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "ref",
+ .mult = 96,
+ .div = 1,
+ },
+ },
+ {
+ .name = "uart",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 0,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 27,
+ },
+ },
+ {
+ .name = "fi2c",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 1,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 48,
+ },
+ },
+ {
+ .name = "stdmac",
+ .type = UNIPHIER_CLK_TYPE_GATE,
+ .output_index = 7,
+ .data.gate = {
+ .parent_name = NULL,
+ .reg = 0x2104,
+ .mask = BIT(10),
+ .enable_val = BIT(10),
+ },
+ },
+ { /* sentinel */ }
+};
+
+static int uniphier_pxs2_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_pxs2_clk_data);
+}
+
+static struct platform_driver uniphier_pxs2_clk_driver = {
+ .probe = uniphier_pxs2_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-pxs2-clk",
+ },
+};
+module_platform_driver(uniphier_pxs2_clk_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier ProXstream2 System Clock Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 09/21] clk: uniphier: add clock driver for UniPhier PH1-LD20 SoC |
| Message-ID | <rxcCp-8kL-77@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/clk/uniphier/Kconfig | 4 ++
drivers/clk/uniphier/Makefile | 1 +
drivers/clk/uniphier/clk-uniphier-ld20.c | 83 ++++++++++++++++++++++++++++++++
3 files changed, 88 insertions(+)
create mode 100644 drivers/clk/uniphier/clk-uniphier-ld20.c
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index 1746aea..6e0a311 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -30,4 +30,8 @@ config CLK_UNIPHIER_LD11
tristate "Clock driver for UniPhier PH1-LD11 SoC"
default ARM64
+config CLK_UNIPHIER_LD20
+ tristate "Clock driver for UniPhier PH1-LD20 SoC"
+ default ARM64
+
endif
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index e056771..59272a6 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_UNIPHIER_SLD8) += clk-uniphier-sld8.o
obj-$(CONFIG_CLK_UNIPHIER_PRO5) += clk-uniphier-pro5.o
obj-$(CONFIG_CLK_UNIPHIER_PXS2) += clk-uniphier-pxs2.o
obj-$(CONFIG_CLK_UNIPHIER_LD11) += clk-uniphier-ld11.o
+obj-$(CONFIG_CLK_UNIPHIER_LD20) += clk-uniphier-ld20.o
diff --git a/drivers/clk/uniphier/clk-uniphier-ld20.c b/drivers/clk/uniphier/clk-uniphier-ld20.c
new file mode 100644
index 0000000..a15a59b
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-ld20.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+static const struct uniphier_clk_data uniphier_ld20_clk_data[] = {
+ {
+ .name = "spll",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "ref",
+ .mult = 80,
+ .div = 1,
+ },
+ },
+ {
+ .name = "uart",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 0,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 34,
+ },
+ },
+ {
+ .name = "fi2c",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 1,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 50,
+ },
+ },
+ {
+ .name = "stdmac",
+ .type = UNIPHIER_CLK_TYPE_GATE,
+ .output_index = 7,
+ .data.gate = {
+ .parent_name = NULL,
+ .reg = 0x200c,
+ .mask = BIT(8),
+ .enable_val = BIT(8),
+ },
+ },
+ { /* sentinel */ }
+};
+
+static int uniphier_ld20_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_ld20_clk_data);
+}
+
+static struct platform_driver uniphier_ld20_clk_driver = {
+ .probe = uniphier_ld20_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-ld20-clk",
+ },
+};
+module_platform_driver(uniphier_ld20_clk_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-LD20 System Clock Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 06/21] clk: uniphier: add clock driver for UniPhier PH1-Pro5 SoC |
| Message-ID | <rxcCq-8kL-79@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/clk/uniphier/Kconfig | 4 ++
drivers/clk/uniphier/Makefile | 1 +
drivers/clk/uniphier/clk-uniphier-pro5.c | 102 +++++++++++++++++++++++++++++++
3 files changed, 107 insertions(+)
create mode 100644 drivers/clk/uniphier/clk-uniphier-pro5.c
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index 8e930c3..de3fada 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -18,4 +18,8 @@ config CLK_UNIPHIER_SLD8
tristate "Clock driver for UniPhier PH1-sLD8 SoC"
default ARM
+config CLK_UNIPHIER_PRO5
+ tristate "Clock driver for UniPhier PH1-Pro5 SoC"
+ default ARM
+
endif
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index c7a8390..d1edf30 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -7,3 +7,4 @@ obj-y += clk-uniphier-mux.o
obj-$(CONFIG_CLK_UNIPHIER_LD4) += clk-uniphier-ld4.o
obj-$(CONFIG_CLK_UNIPHIER_PRO4) += clk-uniphier-pro4.o
obj-$(CONFIG_CLK_UNIPHIER_SLD8) += clk-uniphier-sld8.o
+obj-$(CONFIG_CLK_UNIPHIER_PRO5) += clk-uniphier-pro5.o
diff --git a/drivers/clk/uniphier/clk-uniphier-pro5.c b/drivers/clk/uniphier/clk-uniphier-pro5.c
new file mode 100644
index 0000000..5ce5fbc
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-pro5.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+static const struct uniphier_clk_data uniphier_pro5_clk_data[] = {
+ {
+ .name = "spll",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "ref",
+ .mult = 120,
+ .div = 1,
+ },
+ },
+ {
+ .name = "dapll1",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "ref",
+ .mult = 128,
+ .div = 125,
+ },
+ },
+ {
+ .name = "dapll2",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "upll",
+ .mult = 144,
+ .div = 5,
+ },
+ },
+ {
+ .name = "uart",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 0,
+ .data.factor = {
+ .parent_name = "dapll2",
+ .mult = 1,
+ .div = 8,
+ },
+ },
+ {
+ .name = "fi2c",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 1,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 48,
+ },
+ },
+ {
+ .name = "stdmac",
+ .type = UNIPHIER_CLK_TYPE_GATE,
+ .output_index = 7,
+ .data.gate = {
+ .parent_name = "stdmac-clken",
+ .reg = 0x2000,
+ .mask = BIT(10),
+ .enable_val = BIT(10),
+ },
+ },
+ { /* sentinel */ }
+};
+
+static int uniphier_pro5_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_pro5_clk_data);
+}
+
+static struct platform_driver uniphier_pro5_clk_driver = {
+ .probe = uniphier_pro5_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-pro5-clk",
+ },
+};
+module_platform_driver(uniphier_pro5_clk_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-Pro5 System Clock Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 15/21] reset: uniphier: add reset driver for UniPhier PH1-sLD8 SoC |
| Message-ID | <rxcCq-8kL-81@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/reset/uniphier/Kconfig | 4 +++
drivers/reset/uniphier/Makefile | 1 +
drivers/reset/uniphier/reset-uniphier-sld8.c | 46 ++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
create mode 100644 drivers/reset/uniphier/reset-uniphier-sld8.c
diff --git a/drivers/reset/uniphier/Kconfig b/drivers/reset/uniphier/Kconfig
index 1633093..307d563 100644
--- a/drivers/reset/uniphier/Kconfig
+++ b/drivers/reset/uniphier/Kconfig
@@ -14,4 +14,8 @@ config RESET_UNIPHIER_PRO4
tristate "Reset driver for UniPhier PH1-Pro4 SoC"
default ARM
+config RESET_UNIPHIER_SLD8
+ tristate "Reset driver for UniPhier PH1-sLD8 SoC"
+ default ARM
+
endif
diff --git a/drivers/reset/uniphier/Makefile b/drivers/reset/uniphier/Makefile
index d496fe8..e1001c6 100644
--- a/drivers/reset/uniphier/Makefile
+++ b/drivers/reset/uniphier/Makefile
@@ -2,3 +2,4 @@ obj-y += reset-uniphier-core.o
obj-$(CONFIG_RESET_UNIPHIER_LD4) += reset-uniphier-ld4.o
obj-$(CONFIG_RESET_UNIPHIER_PRO4) += reset-uniphier-pro4.o
+obj-$(CONFIG_RESET_UNIPHIER_SLD8) += reset-uniphier-sld8.o
diff --git a/drivers/reset/uniphier/reset-uniphier-sld8.c b/drivers/reset/uniphier/reset-uniphier-sld8.c
new file mode 100644
index 0000000..736abd0
--- /dev/null
+++ b/drivers/reset/uniphier/reset-uniphier-sld8.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "reset-uniphier.h"
+
+static const struct uniphier_reset_data uniphier_sld8_reset_data[] = {
+ {
+ .id = 7,
+ .reg = 0x2000,
+ .mask = BIT(10),
+ .deassert_val = BIT(10),
+ },
+ { .id = UNIPHIER_RESET_ID_END }
+};
+
+static int uniphier_sld8_reset_probe(struct platform_device *pdev)
+{
+ return uniphier_reset_probe(pdev, uniphier_sld8_reset_data);
+}
+
+static struct platform_driver uniphier_sld8_reset_driver = {
+ .probe = uniphier_sld8_reset_probe,
+ .driver = {
+ .name = "uniphier-sld8-reset",
+ },
+};
+module_platform_driver(uniphier_sld8_reset_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-sLD8 Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 16/21] reset: uniphier: add reset driver for UniPhier PH1-Pro5 SoC |
| Message-ID | <rxcCq-8kL-85@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/reset/uniphier/Kconfig | 4 +++
drivers/reset/uniphier/Makefile | 1 +
drivers/reset/uniphier/reset-uniphier-pro5.c | 46 ++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
create mode 100644 drivers/reset/uniphier/reset-uniphier-pro5.c
diff --git a/drivers/reset/uniphier/Kconfig b/drivers/reset/uniphier/Kconfig
index 307d563..92d9a5f 100644
--- a/drivers/reset/uniphier/Kconfig
+++ b/drivers/reset/uniphier/Kconfig
@@ -18,4 +18,8 @@ config RESET_UNIPHIER_SLD8
tristate "Reset driver for UniPhier PH1-sLD8 SoC"
default ARM
+config RESET_UNIPHIER_PRO5
+ tristate "Reset driver for UniPhier PH1-Pro5 SoC"
+ default ARM
+
endif
diff --git a/drivers/reset/uniphier/Makefile b/drivers/reset/uniphier/Makefile
index e1001c6..537e3f8 100644
--- a/drivers/reset/uniphier/Makefile
+++ b/drivers/reset/uniphier/Makefile
@@ -3,3 +3,4 @@ obj-y += reset-uniphier-core.o
obj-$(CONFIG_RESET_UNIPHIER_LD4) += reset-uniphier-ld4.o
obj-$(CONFIG_RESET_UNIPHIER_PRO4) += reset-uniphier-pro4.o
obj-$(CONFIG_RESET_UNIPHIER_SLD8) += reset-uniphier-sld8.o
+obj-$(CONFIG_RESET_UNIPHIER_PRO5) += reset-uniphier-pro5.o
diff --git a/drivers/reset/uniphier/reset-uniphier-pro5.c b/drivers/reset/uniphier/reset-uniphier-pro5.c
new file mode 100644
index 0000000..dae6f54
--- /dev/null
+++ b/drivers/reset/uniphier/reset-uniphier-pro5.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "reset-uniphier.h"
+
+static const struct uniphier_reset_data uniphier_pro5_reset_data[] = {
+ {
+ .id = 7,
+ .reg = 0x2000,
+ .mask = BIT(10),
+ .deassert_val = BIT(10),
+ },
+ { .id = UNIPHIER_RESET_ID_END }
+};
+
+static int uniphier_pro5_reset_probe(struct platform_device *pdev)
+{
+ return uniphier_reset_probe(pdev, uniphier_pro5_reset_data);
+}
+
+static struct platform_driver uniphier_pro5_reset_driver = {
+ .probe = uniphier_pro5_reset_probe,
+ .driver = {
+ .name = "uniphier-pro5-reset",
+ },
+};
+module_platform_driver(uniphier_pro5_reset_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-Pro5 Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
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| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 18/21] reset: uniphier: add reset driver for UniPhier PH1-LD11 SoC |
| Message-ID | <rxcCr-8kL-95@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/reset/uniphier/Kconfig | 4 +++
drivers/reset/uniphier/Makefile | 1 +
drivers/reset/uniphier/reset-uniphier-ld11.c | 46 ++++++++++++++++++++++++++++
3 files changed, 51 insertions(+)
create mode 100644 drivers/reset/uniphier/reset-uniphier-ld11.c
diff --git a/drivers/reset/uniphier/Kconfig b/drivers/reset/uniphier/Kconfig
index 022aef4..d9a2123 100644
--- a/drivers/reset/uniphier/Kconfig
+++ b/drivers/reset/uniphier/Kconfig
@@ -26,4 +26,8 @@ config RESET_UNIPHIER_PXS2
tristate "Reset driver for UniPhier ProXstream2/PH1-LD6b SoC"
default ARM
+config RESET_UNIPHIER_LD11
+ tristate "Reset driver for UniPhier PH1-LD11 SoC"
+ default ARM
+
endif
diff --git a/drivers/reset/uniphier/Makefile b/drivers/reset/uniphier/Makefile
index 50847db..f25f648 100644
--- a/drivers/reset/uniphier/Makefile
+++ b/drivers/reset/uniphier/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_RESET_UNIPHIER_PRO4) += reset-uniphier-pro4.o
obj-$(CONFIG_RESET_UNIPHIER_SLD8) += reset-uniphier-sld8.o
obj-$(CONFIG_RESET_UNIPHIER_PRO5) += reset-uniphier-pro5.o
obj-$(CONFIG_RESET_UNIPHIER_PXS2) += reset-uniphier-pxs2.o
+obj-$(CONFIG_RESET_UNIPHIER_LD11) += reset-uniphier-ld11.o
diff --git a/drivers/reset/uniphier/reset-uniphier-ld11.c b/drivers/reset/uniphier/reset-uniphier-ld11.c
new file mode 100644
index 0000000..75cb379
--- /dev/null
+++ b/drivers/reset/uniphier/reset-uniphier-ld11.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "reset-uniphier.h"
+
+static const struct uniphier_reset_data uniphier_ld11_reset_data[] = {
+ {
+ .id = 7,
+ .reg = 0x200c,
+ .mask = BIT(8),
+ .deassert_val = BIT(8),
+ },
+ { .id = UNIPHIER_RESET_ID_END }
+};
+
+static int uniphier_ld11_reset_probe(struct platform_device *pdev)
+{
+ return uniphier_reset_probe(pdev, uniphier_ld11_reset_data);
+}
+
+static struct platform_driver uniphier_ld11_reset_driver = {
+ .probe = uniphier_ld11_reset_probe,
+ .driver = {
+ .name = "uniphier-ld11-reset",
+ },
+};
+module_platform_driver(uniphier_ld11_reset_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-LD11 Reset Controller Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
[toc] | [prev] | [next] | [standalone]
| From | Masahiro Yamada <yamada.masahiro@socionext.com> |
|---|---|
| Date | 2016-05-10 12:00 +0200 |
| Subject | [RFC PATCH 08/21] clk: uniphier: add clock driver for UniPhier PH1-LD11 SoC |
| Message-ID | <rxcCr-8kL-97@gated-at.bofh.it> |
| In reply to | #1397915 |
This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/clk/uniphier/Kconfig | 4 ++
drivers/clk/uniphier/Makefile | 1 +
drivers/clk/uniphier/clk-uniphier-ld11.c | 83 ++++++++++++++++++++++++++++++++
3 files changed, 88 insertions(+)
create mode 100644 drivers/clk/uniphier/clk-uniphier-ld11.c
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index d4a3d55..1746aea 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -26,4 +26,8 @@ config CLK_UNIPHIER_PXS2
tristate "Clock driver for UniPhier ProXstream2/PH1-LD6b SoC"
default ARM
+config CLK_UNIPHIER_LD11
+ tristate "Clock driver for UniPhier PH1-LD11 SoC"
+ default ARM64
+
endif
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index 20a274f..e056771 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_CLK_UNIPHIER_PRO4) += clk-uniphier-pro4.o
obj-$(CONFIG_CLK_UNIPHIER_SLD8) += clk-uniphier-sld8.o
obj-$(CONFIG_CLK_UNIPHIER_PRO5) += clk-uniphier-pro5.o
obj-$(CONFIG_CLK_UNIPHIER_PXS2) += clk-uniphier-pxs2.o
+obj-$(CONFIG_CLK_UNIPHIER_LD11) += clk-uniphier-ld11.o
diff --git a/drivers/clk/uniphier/clk-uniphier-ld11.c b/drivers/clk/uniphier/clk-uniphier-ld11.c
new file mode 100644
index 0000000..5b8536a
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-ld11.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+static const struct uniphier_clk_data uniphier_ld11_clk_data[] = {
+ {
+ .name = "spll",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "ref",
+ .mult = 80,
+ .div = 1,
+ },
+ },
+ {
+ .name = "uart",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 0,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 34,
+ },
+ },
+ {
+ .name = "fi2c",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 1,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 50,
+ },
+ },
+ {
+ .name = "stdmac",
+ .type = UNIPHIER_CLK_TYPE_GATE,
+ .output_index = 7,
+ .data.gate = {
+ .parent_name = NULL,
+ .reg = 0x200c,
+ .mask = BIT(8),
+ .enable_val = BIT(8),
+ },
+ },
+ { /* sentinel */ }
+};
+
+static int uniphier_ld11_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_ld11_clk_data);
+}
+
+static struct platform_driver uniphier_ld11_clk_driver = {
+ .probe = uniphier_ld11_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-ld11-clk",
+ },
+};
+module_platform_driver(uniphier_ld11_clk_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-LD11 System Clock Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
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