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Groups > linux.kernel > #1388579 > unrolled thread
| Started by | Adam Borowski <kilobyte@angband.pl> |
|---|---|
| First post | 2016-04-27 03:30 +0200 |
| Last post | 2016-04-27 11:40 +0200 |
| Articles | 3 — 2 participants |
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[PATCH] perf/x86/amd: Explicitly define PERF_COUNT_HW_REF_CPU_CYCLES as undefined. Adam Borowski <kilobyte@angband.pl> - 2016-04-27 03:30 +0200
Re: [PATCH] perf/x86/amd: Explicitly define PERF_COUNT_HW_REF_CPU_CYCLES as undefined. Ingo Molnar <mingo@kernel.org> - 2016-04-27 10:10 +0200
Re: [PATCH] perf/x86/amd: Explicitly define PERF_COUNT_HW_REF_CPU_CYCLES as undefined. Adam Borowski <kilobyte@angband.pl> - 2016-04-27 11:40 +0200
| From | Adam Borowski <kilobyte@angband.pl> |
|---|---|
| Date | 2016-04-27 03:30 +0200 |
| Subject | [PATCH] perf/x86/amd: Explicitly define PERF_COUNT_HW_REF_CPU_CYCLES as undefined. |
| Message-ID | <rsmsG-WH-9@gated-at.bofh.it> |
filter_events() relies on the value of 0 to remove events that are not applicable, like this one. UBSAN: Undefined behaviour in arch/x86/events/amd/core.c:132:30 index 9 is out of range for type 'u64 [9]' UBSAN: Undefined behaviour in arch/x86/events/amd/core.c:132:9 load of address ffffffff81c021c8 with insufficient space for an object of type 'const u64' Signed-off-by: Adam Borowski <kilobyte@angband.pl> --- arch/x86/events/amd/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 86a9bec..5fa1b8e 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -125,6 +125,7 @@ static const u64 amd_perfmon_event_map[] = [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */ + [PERF_COUNT_HW_REF_CPU_CYCLES] = 0, }; static u64 amd_pmu_event_map(int hw_event) -- 2.8.1
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| From | Ingo Molnar <mingo@kernel.org> |
|---|---|
| Date | 2016-04-27 10:10 +0200 |
| Subject | Re: [PATCH] perf/x86/amd: Explicitly define PERF_COUNT_HW_REF_CPU_CYCLES as undefined. |
| Message-ID | <rssHN-6hy-41@gated-at.bofh.it> |
| In reply to | #1388579 |
* Adam Borowski <kilobyte@angband.pl> wrote: > filter_events() relies on the value of 0 to remove events that are not > applicable, like this one. > > UBSAN: Undefined behaviour in arch/x86/events/amd/core.c:132:30 > index 9 is out of range for type 'u64 [9]' > UBSAN: Undefined behaviour in arch/x86/events/amd/core.c:132:9 > load of address ffffffff81c021c8 with insufficient space > for an object of type 'const u64' > > Signed-off-by: Adam Borowski <kilobyte@angband.pl> > --- > arch/x86/events/amd/core.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c > index 86a9bec..5fa1b8e 100644 > --- a/arch/x86/events/amd/core.c > +++ b/arch/x86/events/amd/core.c > @@ -125,6 +125,7 @@ static const u64 amd_perfmon_event_map[] = > [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, > [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */ > [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */ > + [PERF_COUNT_HW_REF_CPU_CYCLES] = 0, > }; Hm, I think it would be cleaner and more robust to change this (and all other similar, if any) arrays to [PERF_COUNT_HW_MAX] instead. Thanks, Ingo
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| From | Adam Borowski <kilobyte@angband.pl> |
|---|---|
| Date | 2016-04-27 11:40 +0200 |
| Subject | Re: [PATCH] perf/x86/amd: Explicitly define PERF_COUNT_HW_REF_CPU_CYCLES as undefined. |
| Message-ID | <rsu6S-7lj-3@gated-at.bofh.it> |
| In reply to | #1388772 |
On Wed, Apr 27, 2016 at 10:03:45AM +0200, Ingo Molnar wrote: > * Adam Borowski <kilobyte@angband.pl> wrote: > > diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c > > index 86a9bec..5fa1b8e 100644 > > --- a/arch/x86/events/amd/core.c > > +++ b/arch/x86/events/amd/core.c > > @@ -125,6 +125,7 @@ static const u64 amd_perfmon_event_map[] = > > [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, > > [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */ > > [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */ > > + [PERF_COUNT_HW_REF_CPU_CYCLES] = 0, > > }; > > Hm, I think it would be cleaner and more robust to change this (and all other > similar, if any) arrays to [PERF_COUNT_HW_MAX] instead. Good idea! Both of Intel's copies (one for p4, one for core+) already set the size this way. -- A tit a day keeps the vet away.
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