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Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock

Started byStephen Boyd <sboyd@codeaurora.org>
First post2016-04-16 00:40 +0200
Last post2016-04-19 11:20 +0200
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  Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock Stephen Boyd <sboyd@codeaurora.org> - 2016-04-16 00:40 +0200
    Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-04-19 11:20 +0200

#1380348 — Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock

FromStephen Boyd <sboyd@codeaurora.org>
Date2016-04-16 00:40 +0200
SubjectRe: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock
Message-ID<rokz8-1OV-23@gated-at.bofh.it>
On 03/23, Maxime Ripard wrote:
> The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> PLL7, clocked from a 3MHz oscillator, that drives the display related
> clocks (GPU, display engine, TCON, etc.)
> 
> Add a driver for it.
> 
> Acked-by: Rob Herring <robh@kernel.org>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1382313

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2016-04-19 11:20 +0200
Message-ID<rpzZ8-4qx-11@gated-at.bofh.it>
In reply to#1380348

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On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote:
> On 03/23, Maxime Ripard wrote:
> > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> > PLL7, clocked from a 3MHz oscillator, that drives the display related
> > clocks (GPU, display engine, TCON, etc.)
> > 
> > Add a driver for it.
> > 
> > Acked-by: Rob Herring <robh@kernel.org>
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> 
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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