Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock

From	Stephen Boyd <sboyd@codeaurora.org>
Newsgroups	linux.kernel
Subject	Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock
Date	2016-04-16 00:40 +0200
Message-ID	<rokz8-1OV-23@gated-at.bofh.it> (permalink)
References	<rfTZ8-69G-21@gated-at.bofh.it> <rfTZ8-69G-19@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On 03/23, Maxime Ripard wrote:
> The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> PLL7, clocked from a 3MHz oscillator, that drives the display related
> clocks (GPU, display engine, TCON, etc.)
> 
> Add a driver for it.
> 
> Acked-by: Rob Herring <robh@kernel.org>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

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Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock Stephen Boyd <sboyd@codeaurora.org> - 2016-04-16 00:40 +0200
  Re: [PATCH v3 03/19] clk: sunxi: Add PLL3 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-04-19 11:20 +0200

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