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[PATCH 2/2] arm64: dts: uniphier: change release address of spin-table

Started byMasahiro Yamada <yamada.masahiro@socionext.com>
First post2016-04-15 12:40 +0200
Last post2016-04-16 16:50 +0200
Articles 5 — 3 participants

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  [PATCH 2/2] arm64: dts: uniphier: change release address of spin-table Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-04-15 12:40 +0200
    Re: [PATCH 2/2] arm64: dts: uniphier: change release address of  spin-table Mark Rutland <mark.rutland@arm.com> - 2016-04-15 15:10 +0200
      Re: [PATCH 2/2] arm64: dts: uniphier: change release address of spin-table Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-04-15 15:20 +0200
        Re: [PATCH 2/2] arm64: dts: uniphier: change release address of spin-table Arnd Bergmann <arnd@arndb.de> - 2016-04-15 20:50 +0200
          Re: [PATCH 2/2] arm64: dts: uniphier: change release address of spin-table Masahiro Yamada <yamada.masahiro@socionext.com> - 2016-04-16 16:50 +0200

#1379677 — [PATCH 2/2] arm64: dts: uniphier: change release address of spin-table

FromMasahiro Yamada <yamada.masahiro@socionext.com>
Date2016-04-15 12:40 +0200
Subject[PATCH 2/2] arm64: dts: uniphier: change release address of spin-table
Message-ID<ro9kl-1wo-13@gated-at.bofh.it>
The 8-byte register located at 0x59801200 on this SoC is dedicated
for waking up secondary CPUs.  We can use it and save normal memory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
index 651c9d9..f73b09e 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
@@ -77,7 +77,7 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x000>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x59801200>;
 		};
 
 		cpu1: cpu@1 {
@@ -85,7 +85,7 @@
 			compatible = "arm,cortex-a72", "arm,armv8";
 			reg = <0 0x001>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x59801200>;
 		};
 
 		cpu2: cpu@100 {
@@ -93,7 +93,7 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x100>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x59801200>;
 		};
 
 		cpu3: cpu@101 {
@@ -101,7 +101,7 @@
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0 0x101>;
 			enable-method = "spin-table";
-			cpu-release-addr = <0 0x80000100>;
+			cpu-release-addr = <0 0x59801200>;
 		};
 	};
 
-- 
1.9.1

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#1379800 — Re: [PATCH 2/2] arm64: dts: uniphier: change release address of spin-table

FromMark Rutland <mark.rutland@arm.com>
Date2016-04-15 15:10 +0200
SubjectRe: [PATCH 2/2] arm64: dts: uniphier: change release address of spin-table
Message-ID<robFv-3uA-3@gated-at.bofh.it>
In reply to#1379677
On Fri, Apr 15, 2016 at 07:30:47PM +0900, Masahiro Yamada wrote:
> The 8-byte register located at 0x59801200 on this SoC is dedicated
> for waking up secondary CPUs.  We can use it and save normal memory.

Generally, it is not safe to use MMIO registers to back spin-table. The
kernel maps the spin table location with cacheable attributes, so there
may be speculative accesses to any registes in the same (64K) page, and
a writeback may be larger than the 8-byte register width (which the
device might not accept, triggering an SError).

Given that, I do not think this is a good idea.

Thanks,
Mark.

> 
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> ---
> 
>  arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
> index 651c9d9..f73b09e 100644
> --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
> +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi
> @@ -77,7 +77,7 @@
>  			compatible = "arm,cortex-a72", "arm,armv8";
>  			reg = <0 0x000>;
>  			enable-method = "spin-table";
> -			cpu-release-addr = <0 0x80000100>;
> +			cpu-release-addr = <0 0x59801200>;
>  		};
>  
>  		cpu1: cpu@1 {
> @@ -85,7 +85,7 @@
>  			compatible = "arm,cortex-a72", "arm,armv8";
>  			reg = <0 0x001>;
>  			enable-method = "spin-table";
> -			cpu-release-addr = <0 0x80000100>;
> +			cpu-release-addr = <0 0x59801200>;
>  		};
>  
>  		cpu2: cpu@100 {
> @@ -93,7 +93,7 @@
>  			compatible = "arm,cortex-a53", "arm,armv8";
>  			reg = <0 0x100>;
>  			enable-method = "spin-table";
> -			cpu-release-addr = <0 0x80000100>;
> +			cpu-release-addr = <0 0x59801200>;
>  		};
>  
>  		cpu3: cpu@101 {
> @@ -101,7 +101,7 @@
>  			compatible = "arm,cortex-a53", "arm,armv8";
>  			reg = <0 0x101>;
>  			enable-method = "spin-table";
> -			cpu-release-addr = <0 0x80000100>;
> +			cpu-release-addr = <0 0x59801200>;
>  		};
>  	};
>  
> -- 
> 1.9.1
>

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#1379808

FromMasahiro Yamada <yamada.masahiro@socionext.com>
Date2016-04-15 15:20 +0200
Message-ID<robPc-3yU-25@gated-at.bofh.it>
In reply to#1379800
Hi Mark.

2016-04-15 22:05 GMT+09:00 Mark Rutland <mark.rutland@arm.com>:
> On Fri, Apr 15, 2016 at 07:30:47PM +0900, Masahiro Yamada wrote:
>> The 8-byte register located at 0x59801200 on this SoC is dedicated
>> for waking up secondary CPUs.  We can use it and save normal memory.
>
> Generally, it is not safe to use MMIO registers to back spin-table. The
> kernel maps the spin table location with cacheable attributes, so there
> may be speculative accesses to any registes in the same (64K) page, and
> a writeback may be larger than the 8-byte register width (which the
> device might not accept, triggering an SError).
>
> Given that, I do not think this is a good idea.

I did not know this.  Thanks for your advice!


Arnd, Olof

Please drop this patch.
(I think 1/2 is still OK.)



-- 
Best Regards
Masahiro Yamada

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#1380112

FromArnd Bergmann <arnd@arndb.de>
Date2016-04-15 20:50 +0200
Message-ID<rogYx-7wu-5@gated-at.bofh.it>
In reply to#1379808
On Friday 15 April 2016 22:13:55 Masahiro Yamada wrote:
> 2016-04-15 22:05 GMT+09:00 Mark Rutland <mark.rutland@arm.com>:
> > On Fri, Apr 15, 2016 at 07:30:47PM +0900, Masahiro Yamada wrote:
> >> The 8-byte register located at 0x59801200 on this SoC is dedicated
> >> for waking up secondary CPUs.  We can use it and save normal memory.
> >
> > Generally, it is not safe to use MMIO registers to back spin-table. The
> > kernel maps the spin table location with cacheable attributes, so there
> > may be speculative accesses to any registes in the same (64K) page, and
> > a writeback may be larger than the 8-byte register width (which the
> > device might not accept, triggering an SError).
> >
> > Given that, I do not think this is a good idea.
> 
> I did not know this.  Thanks for your advice!
> 
> 
> Arnd, Olof
> 
> Please drop this patch.
> (I think 1/2 is still OK.)
> 

Should patch 1 be applied as a bugfix for 4.6 instead?

	Arnd

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#1380558

FromMasahiro Yamada <yamada.masahiro@socionext.com>
Date2016-04-16 16:50 +0200
Message-ID<rozHQ-50s-15@gated-at.bofh.it>
In reply to#1380112
Hi Arnd,


2016-04-16 3:48 GMT+09:00 Arnd Bergmann <arnd@arndb.de>:
> On Friday 15 April 2016 22:13:55 Masahiro Yamada wrote:
>> 2016-04-15 22:05 GMT+09:00 Mark Rutland <mark.rutland@arm.com>:
>> > On Fri, Apr 15, 2016 at 07:30:47PM +0900, Masahiro Yamada wrote:
>> >> The 8-byte register located at 0x59801200 on this SoC is dedicated
>> >> for waking up secondary CPUs.  We can use it and save normal memory.
>> >
>> > Generally, it is not safe to use MMIO registers to back spin-table. The
>> > kernel maps the spin table location with cacheable attributes, so there
>> > may be speculative accesses to any registes in the same (64K) page, and
>> > a writeback may be larger than the 8-byte register width (which the
>> > device might not accept, triggering an SError).
>> >
>> > Given that, I do not think this is a good idea.
>>
>> I did not know this.  Thanks for your advice!
>>
>>
>> Arnd, Olof
>>
>> Please drop this patch.
>> (I think 1/2 is still OK.)
>>
>
> Should patch 1 be applied as a bugfix for 4.6 instead?
>

Yes, please!


-- 
Best Regards
Masahiro Yamada

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