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[PATCH 0/7] pinctrl: soc/tegra: Add support to configure IO rail voltage and pad power states

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  [PATCH 0/7] pinctrl: soc/tegra: Add support to configure IO rail voltage and pad power states Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
    [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
      Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Thierry Reding <thierry.reding@gmail.com> - 2016-04-12 17:30 +0200
        Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 19:20 +0200
          Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 20:10 +0200
          Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Jon Hunter <jonathanh@nvidia.com> - 2016-04-12 20:10 +0200
    [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
      Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-13 11:10 +0200
        Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-13 11:20 +0200
          Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-13 11:40 +0200
      Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 16:20 +0200
        Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 16:30 +0200
          Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 17:20 +0200
            Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 17:30 +0200
              Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 17:50 +0200
      Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Stephen Warren <swarren@wwwdotorg.org> - 2016-04-15 18:40 +0200
    [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
      Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 10:10 +0200
        Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 11:00 +0200
          Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 11:30 +0200
            Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 12:10 +0200
              Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 13:20 +0200
                Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 14:00 +0200
                  Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 16:10 +0200
                    Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 16:20 +0200
          Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and  power state of io pads Stephen Warren <swarren@wwwdotorg.org> - 2016-04-15 18:40 +0200
    [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field definition Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
      Re: [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field  definition Thierry Reding <thierry.reding@gmail.com> - 2016-04-12 17:30 +0200
        Re: [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field  definition Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 19:10 +0200
        Re: [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field definition Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 09:50 +0200

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#1376899 — [PATCH 0/7] pinctrl: soc/tegra: Add support to configure IO rail voltage and pad power states

NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
or 3.3V I/O voltage levels. Also the IO pads can be configured
for power down state if it is not used. SW needs to configure the
voltage level of IO pads based on IO rail voltage and its power
state based on platform usage.
    
The voltage rail configuration and pad power states are done in
Tegra PMC registers.

This series add the required interface in soc/tegra/pmc for required
configruations.  This series also add the pincontrol driver for tegra210
IO pads conifguration. This will helps to provide framework for IO pad
configurations via pincontrol DT support and pincontrol dynamic
configruations.

Laxman Dewangan (7):
  soc/tegra: pmc: Use BIT macro for register field definition
  soc/tegra: pmc: Add new Tegra210 IO rails
  soc/tegra: pmc: Add interface to get IO rail power status
  soc/tegra: pmc: Add interface to set voltage of IO rails
  soc/tegra: pmc: Register sub-devices of PMC
  pinctrl: tegra: Add DT binding for io pads control
  pinctrl: tegra: Add driver to configure voltage and power state of io
    pads

 .../bindings/pinctrl/nvidia,tegra210-io-pad.txt    | 102 +++++++
 drivers/pinctrl/tegra/Kconfig                      |  11 +
 drivers/pinctrl/tegra/Makefile                     |   1 +
 drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c    | 302 +++++++++++++++++++++
 drivers/soc/tegra/pmc.c                            | 159 +++++++++--
 .../dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h  |  24 ++
 include/soc/tegra/pmc.h                            |  52 ++++
 7 files changed, 630 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h

-- 
2.1.4

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#1376900 — [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails

NVIDIA Tegra210 has extended the IO rails for new IO pads
and added some new IO rails on top of its previous SoC.

Add all supported IO rails from Tegra210 to the Tegra PMC header.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 include/soc/tegra/pmc.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
index 07e332d..58fadc5 100644
--- a/include/soc/tegra/pmc.h
+++ b/include/soc/tegra/pmc.h
@@ -90,22 +90,36 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
 #define TEGRA_IO_RAIL_UART	14
 #define TEGRA_IO_RAIL_BB	15
 #define TEGRA_IO_RAIL_AUDIO	17
+#define TEGRA_IO_RAIL_USB3	18
 #define TEGRA_IO_RAIL_HSIC	19
 #define TEGRA_IO_RAIL_COMP	22
+#define TEGRA_IO_RAIL_DBG	25
+#define TEGRA_IO_RAIL_DBG_NONAO	26
+#define TEGRA_IO_RAIL_GPIO	27
 #define TEGRA_IO_RAIL_HDMI	28
 #define TEGRA_IO_RAIL_PEX_CNTRL	32
 #define TEGRA_IO_RAIL_SDMMC1	33
 #define TEGRA_IO_RAIL_SDMMC3	34
 #define TEGRA_IO_RAIL_SDMMC4	35
+#define TEGRA_IO_RAIL_EMMC	35
 #define TEGRA_IO_RAIL_CAM	36
 #define TEGRA_IO_RAIL_RES	37
+#define TEGRA_IO_RAIL_EMMC2	37
 #define TEGRA_IO_RAIL_HV	38
 #define TEGRA_IO_RAIL_DSIB	39
 #define TEGRA_IO_RAIL_DSIC	40
 #define TEGRA_IO_RAIL_DSID	41
+#define TEGRA_IO_RAIL_CSIC	42
+#define TEGRA_IO_RAIL_CSID	43
 #define TEGRA_IO_RAIL_CSIE	44
+#define TEGRA_IO_RAIL_CSIF	45
+#define TEGRA_IO_RAIL_SPI	46
+#define TEGRA_IO_RAIL_SPI_HV	47
+#define TEGRA_IO_RAIL_DMIC	50
+#define TEGRA_IO_RAIL_DP	51
 #define TEGRA_IO_RAIL_LVDS	57
 #define TEGRA_IO_RAIL_SYS_DDC	58
+#define TEGRA_IO_RAIL_AUDIO_HV	61
 
 #ifdef CONFIG_ARCH_TEGRA
 int tegra_powergate_is_powered(unsigned int id);
-- 
2.1.4

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#1376915 — Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails

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On Tue, Apr 12, 2016 at 08:26:42PM +0530, Laxman Dewangan wrote:
> NVIDIA Tegra210 has extended the IO rails for new IO pads
> and added some new IO rails on top of its previous SoC.
> 
> Add all supported IO rails from Tegra210 to the Tegra PMC header.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
>  include/soc/tegra/pmc.h | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
> index 07e332d..58fadc5 100644
> --- a/include/soc/tegra/pmc.h
> +++ b/include/soc/tegra/pmc.h
> @@ -90,22 +90,36 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
>  #define TEGRA_IO_RAIL_UART	14
>  #define TEGRA_IO_RAIL_BB	15
>  #define TEGRA_IO_RAIL_AUDIO	17
> +#define TEGRA_IO_RAIL_USB3	18
>  #define TEGRA_IO_RAIL_HSIC	19
>  #define TEGRA_IO_RAIL_COMP	22
> +#define TEGRA_IO_RAIL_DBG	25
> +#define TEGRA_IO_RAIL_DBG_NONAO	26
> +#define TEGRA_IO_RAIL_GPIO	27
>  #define TEGRA_IO_RAIL_HDMI	28
>  #define TEGRA_IO_RAIL_PEX_CNTRL	32
>  #define TEGRA_IO_RAIL_SDMMC1	33
>  #define TEGRA_IO_RAIL_SDMMC3	34
>  #define TEGRA_IO_RAIL_SDMMC4	35
> +#define TEGRA_IO_RAIL_EMMC	35
>  #define TEGRA_IO_RAIL_CAM	36
>  #define TEGRA_IO_RAIL_RES	37
> +#define TEGRA_IO_RAIL_EMMC2	37

We have a duplicate entry for 37 now. The _RES might have meant
"reserved", in which case maybe just replace it with the new symbolic
name?

Thierry

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#1377036 — Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails

On Tuesday 12 April 2016 08:58 PM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Tue, Apr 12, 2016 at 08:26:42PM +0530, Laxman Dewangan wrote:
>> NVIDIA Tegra210 has extended the IO rails for new IO pads
>> and added some new IO rails on top of its previous SoC.
>>
>> Add all supported IO rails from Tegra210 to the Tegra PMC header.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>> ---
>>   include/soc/tegra/pmc.h | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
>> index 07e332d..58fadc5 100644
>> --- a/include/soc/tegra/pmc.h
>> +++ b/include/soc/tegra/pmc.h
>> @@ -90,22 +90,36 @@ int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
>>   #define TEGRA_IO_RAIL_UART	14
>>   #define TEGRA_IO_RAIL_BB	15
>>   #define TEGRA_IO_RAIL_AUDIO	17
>> +#define TEGRA_IO_RAIL_USB3	18
>>   #define TEGRA_IO_RAIL_HSIC	19
>>   #define TEGRA_IO_RAIL_COMP	22
>> +#define TEGRA_IO_RAIL_DBG	25
>> +#define TEGRA_IO_RAIL_DBG_NONAO	26
>> +#define TEGRA_IO_RAIL_GPIO	27
>>   #define TEGRA_IO_RAIL_HDMI	28
>>   #define TEGRA_IO_RAIL_PEX_CNTRL	32
>>   #define TEGRA_IO_RAIL_SDMMC1	33
>>   #define TEGRA_IO_RAIL_SDMMC3	34
>>   #define TEGRA_IO_RAIL_SDMMC4	35
>> +#define TEGRA_IO_RAIL_EMMC	35
>>   #define TEGRA_IO_RAIL_CAM	36
>>   #define TEGRA_IO_RAIL_RES	37
>> +#define TEGRA_IO_RAIL_EMMC2	37
> We have a duplicate entry for 37 now. The _RES might have meant
> "reserved", in which case maybe just replace it with the new symbolic
> name?

OK, then make sense to replace RES with EMMC2.

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#1377073 — Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails

On Tuesday 12 April 2016 11:33 PM, Jon Hunter wrote:
> On 12/04/16 17:59, Laxman Dewangan wrote:
>> On Tuesday 12 April 2016 08:58 PM, Thierry Reding wrote:
>>> * PGP Signed by an unknown key
>>>
>>> On Tue, Apr 12, 2016 at 08:26:42PM +0530, Laxman Dewangan wrote:
>>>> +#define TEGRA_IO_RAIL_EMMC    35
>>>>    #define TEGRA_IO_RAIL_CAM    36
>>>>    #define TEGRA_IO_RAIL_RES    37
>>>> +#define TEGRA_IO_RAIL_EMMC2    37
>>> We have a duplicate entry for 37 now. The _RES might have meant
>>> "reserved", in which case maybe just replace it with the new symbolic
>>> name?
>> OK, then make sense to replace RES with EMMC2.
> Looking at the Tegra124 TRM it was reserved and so renaming makes sense
> here. However, that also prompts the question how do we check to ensure
> that the IO rail is valid for a given SoC?
>
> Should we define a 'valid' mask for IO_DPD_STATUS and IO_DPD2_STATUS
> registers in the SoC data so we can check if the rail is valid?
>

Yes, that is good idea.
Infact, we should decouple  RAIL_ID with the bit location of register.
This will help on mapping any rail ID to SoC specific bit location and 
need not to worry if bit location of rail get changed on any generation. 
Local lookup table from ID to bit location can make validation as well 
as the decoupling.

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#1377077 — Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails

On 12/04/16 17:59, Laxman Dewangan wrote:
> 
> On Tuesday 12 April 2016 08:58 PM, Thierry Reding wrote:
>> * PGP Signed by an unknown key
>>
>> On Tue, Apr 12, 2016 at 08:26:42PM +0530, Laxman Dewangan wrote:
>>> NVIDIA Tegra210 has extended the IO rails for new IO pads
>>> and added some new IO rails on top of its previous SoC.
>>>
>>> Add all supported IO rails from Tegra210 to the Tegra PMC header.
>>>
>>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>>> ---
>>>   include/soc/tegra/pmc.h | 14 ++++++++++++++
>>>   1 file changed, 14 insertions(+)
>>>
>>> diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
>>> index 07e332d..58fadc5 100644
>>> --- a/include/soc/tegra/pmc.h
>>> +++ b/include/soc/tegra/pmc.h
>>> @@ -90,22 +90,36 @@ int tegra_pmc_cpu_remove_clamping(unsigned int
>>> cpuid);
>>>   #define TEGRA_IO_RAIL_UART    14
>>>   #define TEGRA_IO_RAIL_BB    15
>>>   #define TEGRA_IO_RAIL_AUDIO    17
>>> +#define TEGRA_IO_RAIL_USB3    18
>>>   #define TEGRA_IO_RAIL_HSIC    19
>>>   #define TEGRA_IO_RAIL_COMP    22
>>> +#define TEGRA_IO_RAIL_DBG    25
>>> +#define TEGRA_IO_RAIL_DBG_NONAO    26
>>> +#define TEGRA_IO_RAIL_GPIO    27
>>>   #define TEGRA_IO_RAIL_HDMI    28
>>>   #define TEGRA_IO_RAIL_PEX_CNTRL    32
>>>   #define TEGRA_IO_RAIL_SDMMC1    33
>>>   #define TEGRA_IO_RAIL_SDMMC3    34
>>>   #define TEGRA_IO_RAIL_SDMMC4    35
>>> +#define TEGRA_IO_RAIL_EMMC    35
>>>   #define TEGRA_IO_RAIL_CAM    36
>>>   #define TEGRA_IO_RAIL_RES    37
>>> +#define TEGRA_IO_RAIL_EMMC2    37
>> We have a duplicate entry for 37 now. The _RES might have meant
>> "reserved", in which case maybe just replace it with the new symbolic
>> name?
> 
> OK, then make sense to replace RES with EMMC2.

Looking at the Tegra124 TRM it was reserved and so renaming makes sense
here. However, that also prompts the question how do we check to ensure
that the IO rail is valid for a given SoC?

Should we define a 'valid' mask for IO_DPD_STATUS and IO_DPD2_STATUS
registers in the SoC data so we can check if the rail is valid?

Cheers
Jon

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#1376904 — [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
or 3.3V I/O voltage levels. Also IO pads can be configured for
power down state if it is not in used. SW needs to configure the
voltage level of IO pads based on IO rail voltage and its power
state based on platform usage.

Add DT binding document for detailing the DT properties for
configuring IO pads voltage levels and its power state.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 .../bindings/pinctrl/nvidia,tegra210-io-pad.txt    | 102 +++++++++++++++++++++
 .../dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h  |  24 +++++
 2 files changed, 126 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
 create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h

diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
new file mode 100644
index 0000000..97cdd4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
@@ -0,0 +1,102 @@
+NVIDIA Tegra210 PMC IO pad controller
+
+NVIDIA Tegra210 supports IO pads which can operate at 1.8V or 3.3V I/O
+power rail voltages. SW needs to configure the voltage level of IO pads
+based on platform specific power tree.
+
+The voltage configurations of IO pads should be done in boot if it is not
+going to change other wise dynamically based on IO rail voltage on that
+IO pads.
+
+The node for the Tegra210 io-pad driver must be sub node of pmc@0,7000e400.
+
+Required properties:
+- compatible: "nvidia,tegra210-io-pad"
+
+Please refer to <pinctrl-bindings.txt> in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Tegra's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for an
+IO pads, or a list of IO pads. This configuration can include the voltage and
+power enable/disable control
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content. Each subnode only affects those
+parameters that are explicitly listed. Unspecified is represented as an absent
+property,
+
+See the TRM to determine which properties and values apply to each IO pads.
+Macro values for property values are defined in
+<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
+
+The voltage supported on the pads are 1.8V and 3.3V. The enums are defined as:
+	For 1.8V, use TEGRA210_IO_RAIL_1800000UV
+	For 3.3V, use TEGRA210_IO_RAIL_3300000UV
+
+Required subnode-properties:
+==========================
+- pins : An array of strings. Each string contains the name of an IO pads. Valid
+	 values for these names are listed below.
+
+Optional subnode-properties:
+==========================
+-nvidia,io-rail-voltage:	Integer. The voltage level of IO pads. The
+				valid values are 1.8V and 3.3V. Macros are
+				defined for these voltage levels in
+				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
+					Use TEGRA210_IO_RAIL_1800000UV for 1.8V
+					Use TEGRA210_IO_RAIL_3300000UV for 3.3V
+
+-nvidia,io-pad-deep-power-down: Integer, representing the deep power down state
+				of the IO pads. If this is enable then IO pads
+				will be in power down state and interface is not
+				enabled for any transaction. This is power
+				saving mode of the IO pads. The macros are
+				defined for enable/disable in
+				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
+				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE for
+					disable.
+				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE for
+					enable.
+Valid values for pin are:
+	audio, audio-hv, cam, csia, csib, csic, csid, csie, csif,
+	dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2,
+	gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2,
+	pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0,
+	usb1, usb2, usb3.
+
+All IO pads do not support the 1.8V/3.3V configurations. Valid values for
+nvidia,io-rail-voltage are:
+	audio-hv, dmic, gpio, sdmmc1, sdmmc3, spi-hv.
+
+All above IO pads supports the deep power down state.
+
+Example:
+	#include <dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
+	pmc@0,7000e400 {
+		pmc-pad-control {
+			compatible = "nvidia,tegra210-io-pad";
+			pinctrl-names = "default";
+			pinctrl-0 = <&tegra_io_pad_volt_default>;
+			tegra_io_pad_volt_default: common {
+				audio {
+					pins = "audio";
+					nvidia,io-pad-deep-power-down = <TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE>;
+				};
+				audio-hv {
+					pins = "audio-hv";
+					nvidia,io-rail-voltage = <TEGRA210_IO_RAIL_1800000UV>;
+				};
+				gpio {
+					pins = "gpio";
+					nvidia,io-rail-voltage = <TEGRA210_IO_RAIL_1800000UV>;
+				};
+				rest {
+					pins = "dmic", "sdmmc1", "sdmmc3";
+					nvidia,io-rail-voltage = <TEGRA210_IO_RAIL_1800000UV>;
+				};
+			};
+		};
+	};
diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h b/include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h
new file mode 100644
index 0000000..e32166b
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h
@@ -0,0 +1,24 @@
+/*
+ * This header provides constants for Tegra210 IO pads pinctrl bindings.
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_TEGRA210_IO_PAD_H
+#define _DT_BINDINGS_PINCTRL_TEGRA210_IO_PAD_H
+
+/* Voltage levels of Tegra210 IO rails. */
+#define TEGRA210_IO_RAIL_1800000UV		0
+#define TEGRA210_IO_RAIL_3300000UV		1
+
+/* Deep power down state enable/disable for Tegra210 IO pads */
+#define TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE	0
+#define TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE	1
+
+#endif
-- 
2.1.4

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#1377669 — Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

On 12/04/16 15:56, Laxman Dewangan wrote:
> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
> or 3.3V I/O voltage levels. Also IO pads can be configured for
> power down state if it is not in used. SW needs to configure the
> voltage level of IO pads based on IO rail voltage and its power
> state based on platform usage.
> 
> Add DT binding document for detailing the DT properties for
> configuring IO pads voltage levels and its power state.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
>  .../bindings/pinctrl/nvidia,tegra210-io-pad.txt    | 102 +++++++++++++++++++++
>  .../dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h  |  24 +++++
>  2 files changed, 126 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
>  create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
> new file mode 100644
> index 0000000..97cdd4f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
> @@ -0,0 +1,102 @@
> +NVIDIA Tegra210 PMC IO pad controller
> +
> +NVIDIA Tegra210 supports IO pads which can operate at 1.8V or 3.3V I/O
> +power rail voltages. SW needs to configure the voltage level of IO pads
> +based on platform specific power tree.
> +
> +The voltage configurations of IO pads should be done in boot if it is not
> +going to change other wise dynamically based on IO rail voltage on that
> +IO pads.
> +
> +The node for the Tegra210 io-pad driver must be sub node of pmc@0,7000e400.

This should be 'pmc@7000e400'. We were incorrectly adding the '0,'
previously.

> +
> +Required properties:
> +- compatible: "nvidia,tegra210-io-pad"

I think you have have "Must be ..." here. I am also wondering if the
pinctrl device should be registered by the pmc driver and so not a
separate driver to the PMC driver. In other words, the PMC driver calls
pinctrl_register() directly.

> +Please refer to <pinctrl-bindings.txt> in this directory for details of the
> +common pinctrl bindings used by client devices, including the meaning of the
> +phrase "pin configuration node".
> +
> +Tegra's pin configuration nodes act as a container for an arbitrary number of
> +subnodes. Each of these subnodes represents some desired configuration for an
> +IO pads, or a list of IO pads. This configuration can include the voltage and
> +power enable/disable control
> +
> +The name of each subnode is not important; all subnodes should be enumerated
> +and processed purely based on their content. Each subnode only affects those
> +parameters that are explicitly listed. Unspecified is represented as an absent
> +property,
> +
> +See the TRM to determine which properties and values apply to each IO pads.
> +Macro values for property values are defined in
> +<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
> +
> +The voltage supported on the pads are 1.8V and 3.3V. The enums are defined as:
> +	For 1.8V, use TEGRA210_IO_RAIL_1800000UV
> +	For 3.3V, use TEGRA210_IO_RAIL_3300000UV

You may consider just using integer values here like we do for regulators.

> +
> +Required subnode-properties:
> +==========================
> +- pins : An array of strings. Each string contains the name of an IO pads. Valid
> +	 values for these names are listed below.

Why are they not listed here? Array of strings sounds odd. Array/list of
pin names seems more appropriate.

> +Optional subnode-properties:
> +==========================
> +-nvidia,io-rail-voltage:	Integer. The voltage level of IO pads. The
> +				valid values are 1.8V and 3.3V. Macros are
> +				defined for these voltage levels in
> +				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
> +					Use TEGRA210_IO_RAIL_1800000UV for 1.8V
> +					Use TEGRA210_IO_RAIL_3300000UV for 3.3V
> +
> +-nvidia,io-pad-deep-power-down: Integer, representing the deep power down state
> +				of the IO pads. If this is enable then IO pads
> +				will be in power down state and interface is not
> +				enabled for any transaction. This is power
> +				saving mode of the IO pads. The macros are
> +				defined for enable/disable in
> +				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
> +				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE for
> +					disable.
> +				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE for
> +					enable.

Sounds like a boolean parameter. So may consider that if the property
'nvidia,io-pad-deep-power-down' is present then it means enable
deep-power-down and if not present then don't. Then you do not need to
assign a value to it.

> +Valid values for pin are:
> +	audio, audio-hv, cam, csia, csib, csic, csid, csie, csif,
> +	dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2,
> +	gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2,
> +	pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0,
> +	usb1, usb2, usb3.
> +
> +All IO pads do not support the 1.8V/3.3V configurations. Valid values for
> +nvidia,io-rail-voltage are:
> +	audio-hv, dmic, gpio, sdmmc1, sdmmc3, spi-hv.

May be this should be moved under the nvidia,io-rail-voltage description?

> +All above IO pads supports the deep power down state.

May be this should be moved under the nvidia,io-pad-deep-power-down
description?

> +Example:
> +	#include <dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
> +	pmc@0,7000e400 {
> +		pmc-pad-control {
> +			compatible = "nvidia,tegra210-io-pad";
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&tegra_io_pad_volt_default>;
> +			tegra_io_pad_volt_default: common {
> +				audio {
> +					pins = "audio";
> +					nvidia,io-pad-deep-power-down = <TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE>;
> +				};
> +				audio-hv {
> +					pins = "audio-hv";
> +					nvidia,io-rail-voltage = <TEGRA210_IO_RAIL_1800000UV>;
> +				};
> +				gpio {
> +					pins = "gpio";
> +					nvidia,io-rail-voltage = <TEGRA210_IO_RAIL_1800000UV>;
> +				};
> +				rest {
> +					pins = "dmic", "sdmmc1", "sdmmc3";
> +					nvidia,io-rail-voltage = <TEGRA210_IO_RAIL_1800000UV>;
> +				};

I know this is an example, but it does not make sense to me why audio-hv
and gpio and separated from 'rest' when they have the same configuration.

Cheers
Jon

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#1377679 — Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

On Wednesday 13 April 2016 02:34 PM, Jon Hunter wrote:
> On 12/04/16 15:56, Laxman Dewangan wrote:
>> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
>> or 3.3V I/O voltage levels. Also IO pads can be configured for
>> power down state if it is not in used. SW needs to configure the
>> voltage level of IO pads based on IO rail voltage and its power
>> state based on platform usage.
>>
>> Add DT binding document for detailing the DT properties for
>> configuring IO pads voltage levels and its power state.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>> ---
>>   .../bindings/pinctrl/nvidia,tegra210-io-pad.txt    | 102 +++++++++++++++++++++
>>   .../dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h  |  24 +++++
>>   2 files changed, 126 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
>>   create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
>> new file mode 100644
>> index 0000000..97cdd4f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-io-pad.txt
>> @@ -0,0 +1,102 @@
>> +NVIDIA Tegra210 PMC IO pad controller
>> +
>> +NVIDIA Tegra210 supports IO pads which can operate at 1.8V or 3.3V I/O
>> +power rail voltages. SW needs to configure the voltage level of IO pads
>> +based on platform specific power tree.
>> +
>> +The voltage configurations of IO pads should be done in boot if it is not
>> +going to change other wise dynamically based on IO rail voltage on that
>> +IO pads.
>> +
>> +The node for the Tegra210 io-pad driver must be sub node of pmc@0,7000e400.
> This should be 'pmc@7000e400'. We were incorrectly adding the '0,'
> previously.

For T210, 64 bit, it is
  tegra210.dtsi:    pmc: pmc@0,7000e400 {

For T124, it is

pmc@7000e400



>
>> +
>> +Required properties:
>> +- compatible: "nvidia,tegra210-io-pad"
> I think you have have "Must be ..." here. I am also wondering if the
> pinctrl device should be registered by the pmc driver and so not a
> separate driver to the PMC driver. In other words, the PMC driver calls
> pinctrl_register() directly.

I like to keep the pmc driver as main interface and other sub 
functionalities like pad control for voltage and power states, no 
iopower control etc as sub drivers. This will help in modular approach 
of the driver.


>
>> +The voltage supported on the pads are 1.8V and 3.3V. The enums are defined as:
>> +	For 1.8V, use TEGRA210_IO_RAIL_1800000UV
>> +	For 3.3V, use TEGRA210_IO_RAIL_3300000UV
> You may consider just using integer values here like we do for regulators.

We just support two values 1.8V and 3.3V only. I am fine with either way 
also.

>
>> +				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE for
>> +					disable.
>> +				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE for
>> +					enable.
> Sounds like a boolean parameter. So may consider that if the property
> 'nvidia,io-pad-deep-power-down' is present then it means enable
> deep-power-down and if not present then don't. Then you do not need to
> assign a value to it.

Three states, enable, disable and left default. So absent will be left 
default.

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#1377690 — Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

On 13/04/16 10:08, Laxman Dewangan wrote:

[snip]

> For T210, 64 bit, it is
>  tegra210.dtsi:    pmc: pmc@0,7000e400 {

Yes and this is wrong [0].

>>> +Required properties:
>>> +- compatible: "nvidia,tegra210-io-pad"
>> I think you have have "Must be ..." here. I am also wondering if the
>> pinctrl device should be registered by the pmc driver and so not a
>> separate driver to the PMC driver. In other words, the PMC driver calls
>> pinctrl_register() directly.
> 
> I like to keep the pmc driver as main interface and other sub
> functionalities like pad control for voltage and power states, no
> iopower control etc as sub drivers. This will help in modular approach
> of the driver.

OK, let's see what Thierry thinks about this.

>>> +The voltage supported on the pads are 1.8V and 3.3V. The enums are
>>> defined as:
>>> +    For 1.8V, use TEGRA210_IO_RAIL_1800000UV
>>> +    For 3.3V, use TEGRA210_IO_RAIL_3300000UV
>> You may consider just using integer values here like we do for
>> regulators.
> 
> We just support two values 1.8V and 3.3V only. I am fine with either way
> also.
> 
>>
>>> +                  TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE for
>>> +                    disable.
>>> +                  TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE for
>>> +                    enable.
>> Sounds like a boolean parameter. So may consider that if the property
>> 'nvidia,io-pad-deep-power-down' is present then it means enable
>> deep-power-down and if not present then don't. Then you do not need to
>> assign a value to it.
> 
> Three states, enable, disable and left default. So absent will be left
> default.

Fine with me.

Cheers
Jon

[0] http://marc.info/?l=linux-tegra&m=146038329109871&w=2

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#1379846 — Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

On 12/04/16 15:56, Laxman Dewangan wrote:
> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
> or 3.3V I/O voltage levels. Also IO pads can be configured for
> power down state if it is not in used. SW needs to configure the
> voltage level of IO pads based on IO rail voltage and its power
> state based on platform usage.
> 
> Add DT binding document for detailing the DT properties for
> configuring IO pads voltage levels and its power state.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

[snip]

> +Required subnode-properties:
> +==========================
> +- pins : An array of strings. Each string contains the name of an IO pads. Valid
> +	 values for these names are listed below.
> +
> +Optional subnode-properties:
> +==========================
> +-nvidia,io-rail-voltage:	Integer. The voltage level of IO pads. The
> +				valid values are 1.8V and 3.3V. Macros are
> +				defined for these voltage levels in
> +				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
> +					Use TEGRA210_IO_RAIL_1800000UV for 1.8V
> +					Use TEGRA210_IO_RAIL_3300000UV for 3.3V
> +
> +-nvidia,io-pad-deep-power-down: Integer, representing the deep power down state
> +				of the IO pads. If this is enable then IO pads
> +				will be in power down state and interface is not
> +				enabled for any transaction. This is power
> +				saving mode of the IO pads. The macros are
> +				defined for enable/disable in
> +				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
> +				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE for
> +					disable.
> +				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE for
> +					enable.
> +Valid values for pin are:
> +	audio, audio-hv, cam, csia, csib, csic, csid, csie, csif,
> +	dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2,
> +	gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2,
> +	pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0,
> +	usb1, usb2, usb3.

Thinking about this some more, the above are not IO pads but supply
pads, AFAICT. And these supply pads, are supplying the voltage to
various IO pads. I am not sure if these should be named vddio_xxx. The
'pins' properties says these are IO pads, but this does not seem correct.

We also need to think about how these supply pads are linked to the
actual IO pads. Or at least it seems they should be some how ...

Cheers
Jon

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#1379861 — Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

On Friday 15 April 2016 07:46 PM, Jon Hunter wrote:
> On 12/04/16 15:56, Laxman Dewangan wrote:
>> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
>> or 3.3V I/O voltage levels. Also IO pads can be configured for
>> power down state if it is not in used. SW needs to configure the
>> voltage level of IO pads based on IO rail voltage and its power
>> state based on platform usage.
>>
>> Add DT binding document for detailing the DT properties for
>> configuring IO pads voltage levels and its power state.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> [snip]
>
>> +Required subnode-properties:
>> +==========================
>> +- pins : An array of strings. Each string contains the name of an IO pads. Valid
>> +	 values for these names are listed below.
>> +
>> +Optional subnode-properties:
>> +==========================
>> +-nvidia,io-rail-voltage:	Integer. The voltage level of IO pads. The
>> +				valid values are 1.8V and 3.3V. Macros are
>> +				defined for these voltage levels in
>> +				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
>> +					Use TEGRA210_IO_RAIL_1800000UV for 1.8V
>> +					Use TEGRA210_IO_RAIL_3300000UV for 3.3V
>> +
>> +-nvidia,io-pad-deep-power-down: Integer, representing the deep power down state
>> +				of the IO pads. If this is enable then IO pads
>> +				will be in power down state and interface is not
>> +				enabled for any transaction. This is power
>> +				saving mode of the IO pads. The macros are
>> +				defined for enable/disable in
>> +				<dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
>> +				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE for
>> +					disable.
>> +				  TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE for
>> +					enable.
>> +Valid values for pin are:
>> +	audio, audio-hv, cam, csia, csib, csic, csid, csie, csif,
>> +	dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2,
>> +	gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2,
>> +	pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0,
>> +	usb1, usb2, usb3.
> Thinking about this some more, the above are not IO pads but supply
> pads, AFAICT. And these supply pads, are supplying the voltage to
> various IO pads. I am not sure if these should be named vddio_xxx. The
> 'pins' properties says these are IO pads, but this does not seem correct.

These are IO pads. One IO rail  have multiple sub pads to power down 
some of interface when not used. Like if CSIA is active, we can power 
down CSIB, CSIC etc.
All CSI pads are lined to single IO rail.

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#1379910 — Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

On 15/04/16 15:12, Laxman Dewangan wrote:
> 
> On Friday 15 April 2016 07:46 PM, Jon Hunter wrote:
>> On 12/04/16 15:56, Laxman Dewangan wrote:
>>> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
>>> or 3.3V I/O voltage levels. Also IO pads can be configured for
>>> power down state if it is not in used. SW needs to configure the
>>> voltage level of IO pads based on IO rail voltage and its power
>>> state based on platform usage.
>>>
>>> Add DT binding document for detailing the DT properties for
>>> configuring IO pads voltage levels and its power state.
>>>
>>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>> [snip]
>>
>>> +Required subnode-properties:
>>> +==========================
>>> +- pins : An array of strings. Each string contains the name of an IO
>>> pads. Valid
>>> +     values for these names are listed below.
>>> +
>>> +Optional subnode-properties:
>>> +==========================
>>> +-nvidia,io-rail-voltage:    Integer. The voltage level of IO pads. The
>>> +                valid values are 1.8V and 3.3V. Macros are
>>> +                defined for these voltage levels in
>>> +                <dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
>>> +                    Use TEGRA210_IO_RAIL_1800000UV for 1.8V
>>> +                    Use TEGRA210_IO_RAIL_3300000UV for 3.3V
>>> +
>>> +-nvidia,io-pad-deep-power-down: Integer, representing the deep power
>>> down state
>>> +                of the IO pads. If this is enable then IO pads
>>> +                will be in power down state and interface is not
>>> +                enabled for any transaction. This is power
>>> +                saving mode of the IO pads. The macros are
>>> +                defined for enable/disable in
>>> +                <dt-bindings/pinctrl/pinctrl-tegra210-io-pad.h>
>>> +                  TEGRA210_IO_PAD_DEEP_POWER_DOWN_DISABLE for
>>> +                    disable.
>>> +                  TEGRA210_IO_PAD_DEEP_POWER_DOWN_ENABLE for
>>> +                    enable.
>>> +Valid values for pin are:
>>> +    audio, audio-hv, cam, csia, csib, csic, csid, csie, csif,
>>> +    dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2,
>>> +    gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2,
>>> +    pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0,
>>> +    usb1, usb2, usb3.
>> Thinking about this some more, the above are not IO pads but supply
>> pads, AFAICT. And these supply pads, are supplying the voltage to
>> various IO pads. I am not sure if these should be named vddio_xxx. The
>> 'pins' properties says these are IO pads, but this does not seem correct.
> 
> These are IO pads. One IO rail  have multiple sub pads to power down
> some of interface when not used. Like if CSIA is active, we can power
> down CSIB, CSIC etc.

To me, 'IO rail' implies a supply rail, but this is not the same as an
IO pad (or pin/ball). And hence, I think the terminology here is confusing.

For example, audio_hv powers the following IO pads ...

DAP1_DIN
DAP1_DOUT
DAP1_FS
DAP1_SCLK
SPI2_MOSI
SPI2_MISO
SPI2_SCK
SPI2_CS0
SPI2_CS1

And sdmmc1 powers the following IO pads ...

SDMMC1_CLK
SDMMC1_CMD
SDMMC1_DAT0
SDMMC1_DAT1
SDMMC1_DAT2
SDMMC1_DAT3
SDMMC1_COMP

As for CSIA, I don't think this is a pin/pad at all, but a software
means to control the power down for the CSI_A_xxx pads. If CSIA is an IO
pad then what is the ball number for Tegra210? In the datasheet I only
see ...

CSI_A_CLK_N Y6
CSI_A_CLK_P Y7
CSI_A_D0_N Y4
CSI_A_D0_P Y5
CSI_A_D1_N Y1
CSI_A_D1_P AA1

> All CSI pads are lined to single IO rail.

I agree with this and from the data-sheet I see the rail that powers the
CSI (and DSI) interfaces is called AVDD_DSI_CSI. But again, in the DT
document you are referring to csia, csib, csic, csid, csie, csif as
pins, but these don't appear to be physical pins, and this appears to be
more of a software means to control power to the various csi_x pins.

It seems to me that each of the existing CSI_A_xxx pins/pads should be
mapped to or register with the appropriate power-down control and when
all pads are set to inactive this then triggers the power-down of all
the CSI_A_xxx pads.

Cheers
Jon

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#1379918 — Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

On Friday 15 April 2016 08:44 PM, Jon Hunter wrote:
> On 15/04/16 15:12, Laxman Dewangan wrote:
>>
>>
>> All CSI pads are lined to single IO rail.
> I agree with this and from the data-sheet I see the rail that powers the
> CSI (and DSI) interfaces is called AVDD_DSI_CSI. But again, in the DT
> document you are referring to csia, csib, csic, csid, csie, csif as
> pins, but these don't appear to be physical pins, and this appears to be
> more of a software means to control power to the various csi_x pins.
>
> It seems to me that each of the existing CSI_A_xxx pins/pads should be
> mapped to or register with the appropriate power-down control and when
> all pads are set to inactive this then triggers the power-down of all
> the CSI_A_xxx pads.

I used pins as this is the property from pincon generic so that I can 
use the generic implementation.

Here, I will not go to the pin level control as HW does not support pin 
level control.

I will say the unit should be interface level. Should we say 
IO_GROUP_CSIA, IO_GROUP_CSIB etc?


>

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#1379937 — Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

On 15/04/16 16:14, Laxman Dewangan wrote:
> On Friday 15 April 2016 08:44 PM, Jon Hunter wrote:
>> On 15/04/16 15:12, Laxman Dewangan wrote:
>>>
>>>
>>> All CSI pads are lined to single IO rail.
>> I agree with this and from the data-sheet I see the rail that powers the
>> CSI (and DSI) interfaces is called AVDD_DSI_CSI. But again, in the DT
>> document you are referring to csia, csib, csic, csid, csie, csif as
>> pins, but these don't appear to be physical pins, and this appears to be
>> more of a software means to control power to the various csi_x pins.
>>
>> It seems to me that each of the existing CSI_A_xxx pins/pads should be
>> mapped to or register with the appropriate power-down control and when
>> all pads are set to inactive this then triggers the power-down of all
>> the CSI_A_xxx pads.
>
> I used pins as this is the property from pincon generic so that I can
> use the generic implementation.
> 
> Here, I will not go to the pin level control as HW does not support pin
> level control.
> 
> I will say the unit should be interface level. Should we say
> IO_GROUP_CSIA, IO_GROUP_CSIB etc?

So we need to reflect the hardware in device-tree and although yes the
power-down for the CSI_x_xxx pads are all controlled together as a
single group, it does not feel right that we add a pseudo pin called
csix to represent these.

The CSI_x_xxx pads are already in device-tree and so why not add a
property to each of these pads which has the IO rail information for
power-down and voltage-select?

Cheers
Jon

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#1379996 — Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control

On 04/12/2016 08:56 AM, Laxman Dewangan wrote:
> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
> or 3.3V I/O voltage levels. Also IO pads can be configured for
> power down state if it is not in used. SW needs to configure the
> voltage level of IO pads based on IO rail voltage and its power
> state based on platform usage.
>
> Add DT binding document for detailing the DT properties for
> configuring IO pads voltage levels and its power state.

I hope that we only intend to use this in the case where Linux must make 
dynamic changes to the IO voltage (e.g. SD cards switching between speeds).

All static settings, and good boot defaults, should be set up by system 
FW. Perhaps not all FW does this on Tegra210 platforms:-( I hope that on 
future chips, the same FW that sets up the static pinmux sets up the 
static IO voltage configuration, in exactly the same way.

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#1376906 — [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads

NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
or 3.3V I/O voltage levels. Also the IO pads can be configured
for power down state if it is not used. SW needs to configure the
voltage level of IO pads based on IO rail voltage and its power
state based on platform usage.

The voltage and power state configurations of pads are provided
through pin control frameworks. Add pin control driver for Tegra's
IO pads' voltage and power state configurations.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
 drivers/pinctrl/tegra/Kconfig                   |  11 +
 drivers/pinctrl/tegra/Makefile                  |   1 +
 drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c | 302 ++++++++++++++++++++++++
 3 files changed, 314 insertions(+)
 create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c

diff --git a/drivers/pinctrl/tegra/Kconfig b/drivers/pinctrl/tegra/Kconfig
index 24e20cc..37b85d7 100644
--- a/drivers/pinctrl/tegra/Kconfig
+++ b/drivers/pinctrl/tegra/Kconfig
@@ -23,6 +23,17 @@ config PINCTRL_TEGRA210
 	bool
 	select PINCTRL_TEGRA
 
+config PINCTRL_TEGRA210_IO_PAD
+	bool "Tegra210 IO pad Control Driver"
+	depends on ARCH_TEGRA
+	select PINCONF
+	select PINMUX
+	help
+	  NVIDIA Tegra210 SoC has IO pads which supports mult-voltage level
+	  of interfacing. The voltage of IO pads are SW configurable based
+	  on IO rail of that pads. This driver provides the interface to
+	  change IO pad voltage and power state via pincontrol interface.
+
 config PINCTRL_TEGRA_XUSB
 	def_bool y if ARCH_TEGRA
 	select GENERIC_PHY
diff --git a/drivers/pinctrl/tegra/Makefile b/drivers/pinctrl/tegra/Makefile
index a927379..90f4000 100644
--- a/drivers/pinctrl/tegra/Makefile
+++ b/drivers/pinctrl/tegra/Makefile
@@ -4,4 +4,5 @@ obj-$(CONFIG_PINCTRL_TEGRA30)		+= pinctrl-tegra30.o
 obj-$(CONFIG_PINCTRL_TEGRA114)		+= pinctrl-tegra114.o
 obj-$(CONFIG_PINCTRL_TEGRA124)		+= pinctrl-tegra124.o
 obj-$(CONFIG_PINCTRL_TEGRA210)		+= pinctrl-tegra210.o
+obj-$(CONFIG_PINCTRL_TEGRA210_IO_PAD)	+= pinctrl-tegra210-io-pad.o
 obj-$(CONFIG_PINCTRL_TEGRA_XUSB)	+= pinctrl-tegra-xusb.o
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c b/drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c
new file mode 100644
index 0000000..4959c19
--- /dev/null
+++ b/drivers/pinctrl/tegra/pinctrl-tegra210-io-pad.c
@@ -0,0 +1,302 @@
+/*
+ * Generic ADC thermal driver
+ *
+ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <soc/tegra/pmc.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinctrl-utils.h"
+
+enum tegra_io_rail_pads_params {
+	TEGRA_IO_RAIL_VOLTAGE = PIN_CONFIG_END + 1,
+	TEGRA_IO_PAD_DEEP_POWER_DOWN,
+};
+
+static const struct pinconf_generic_params tegra_io_pads_cfg_params[] = {
+	{
+		.property = "nvidia,io-rail-voltage",
+		.param = TEGRA_IO_RAIL_VOLTAGE,
+	}, {
+		.property = "nvidia,io-pad-deep-power-down",
+		.param = TEGRA_IO_PAD_DEEP_POWER_DOWN,
+	},
+};
+
+struct tegra_io_pads_cfg_info {
+	const char *name;
+	const unsigned int pins[1];
+	int io_rail_id;
+};
+
+#define TEGRA210_PAD_INFO_TABLE(_entry_)		\
+	_entry_(0, "audio", AUDIO),			\
+	_entry_(1, "audio-hv", AUDIO_HV),	\
+	_entry_(2, "cam", CAM),			\
+	_entry_(3, "csia", CSIA),			\
+	_entry_(4, "csib", CSIB),			\
+	_entry_(5, "csic", CSIC),			\
+	_entry_(6, "csid", CSID),			\
+	_entry_(7, "csie", CSIE),			\
+	_entry_(8, "csif", CSIF),			\
+	_entry_(9, "dbg", DBG),			\
+	_entry_(10, "debug-nonao", DBG_NONAO), \
+	_entry_(11, "dmic", DMIC),			\
+	_entry_(12, "dp", DP),				\
+	_entry_(13, "dsi", DSI),			\
+	_entry_(14, "dsib", DSIB),			\
+	_entry_(15, "dsic", DSIC),			\
+	_entry_(16, "dsid", DSID),			\
+	_entry_(17, "emmc", SDMMC4),			\
+	_entry_(18, "emmc2", EMMC2),			\
+	_entry_(19, "gpio", GPIO),			\
+	_entry_(20, "hdmi", HDMI),			\
+	_entry_(21, "hsic", HSIC),			\
+	_entry_(22, "lvds", LVDS),			\
+	_entry_(23, "mipi-bias", MIPI_BIAS),	\
+	_entry_(24, "pex-bias", PEX_BIAS),	\
+	_entry_(25, "pex-clk1", PEX_CLK1),	\
+	_entry_(26, "pex-clk2", PEX_CLK2),	\
+	_entry_(27, "pex-ctrl", PEX_CNTRL),	\
+	_entry_(28, "sdmmc1", SDMMC1),		\
+	_entry_(29, "sdmmc3", SDMMC3),		\
+	_entry_(30, "spi", SPI),			\
+	_entry_(31, "spi-hv", SPI_HV),		\
+	_entry_(32, "uart", UART),			\
+	_entry_(33, "usb-bias", USB_BIAS),	\
+	_entry_(34, "usb0", USB0),			\
+	_entry_(35, "usb1", USB1),			\
+	_entry_(36, "usb2", USB2),			\
+	_entry_(37, "usb3", USB3)
+
+#define TEGRA_IO_PAD_INFO(_id, _name, _io_rail_id)			\
+	{								\
+		.name = _name,						\
+		.pins = {(_id)},					\
+		.io_rail_id = TEGRA_IO_RAIL_##_io_rail_id,		\
+	}
+
+static struct tegra_io_pads_cfg_info tegra210_io_pads_cfg_info[] = {
+	TEGRA210_PAD_INFO_TABLE(TEGRA_IO_PAD_INFO),
+};
+
+#define TEGRA_IO_PAD_DESC(_id, _name, _io_rail_id)			\
+	PINCTRL_PIN(_id, _name)
+
+static const struct pinctrl_pin_desc tegra210_io_pads_pinctrl_desc[] = {
+	TEGRA210_PAD_INFO_TABLE(TEGRA_IO_PAD_DESC),
+};
+
+struct tegra_io_pads_info {
+	struct device *dev;
+	struct pinctrl_dev *pctl;
+	struct tegra_io_pads_cfg_info *pads_cfg;
+	unsigned int num_pads_cfg;
+};
+
+static int tegra_iop_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+
+	return tiopi->num_pads_cfg;
+}
+
+static const char *tegra_iop_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+						    unsigned int group)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+
+	return tiopi->pads_cfg[group].name;
+}
+
+static int tegra_iop_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+					    unsigned int group,
+					    const unsigned int **pins,
+					    unsigned int *num_pins)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+
+	*pins = tiopi->pads_cfg[group].pins;
+	*num_pins = 1;
+
+	return 0;
+}
+
+static const struct pinctrl_ops tegra_iop_pinctrl_ops = {
+	.get_groups_count = tegra_iop_pinctrl_get_groups_count,
+	.get_group_name = tegra_iop_pinctrl_get_group_name,
+	.get_group_pins = tegra_iop_pinctrl_get_group_pins,
+	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+	.dt_free_map = pinctrl_utils_dt_free_map,
+};
+
+static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctldev,
+				    unsigned int pin, unsigned long *config)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+	int param = pinconf_to_config_param(*config);
+	struct tegra_io_pads_cfg_info *pad_cfg = &tiopi->pads_cfg[pin];
+	int io_rail_id = pad_cfg->io_rail_id;
+	int arg = 0;
+	int ret;
+
+	switch (param) {
+	case TEGRA_IO_RAIL_VOLTAGE:
+		ret = tegra_io_rail_voltage_get(io_rail_id);
+		if (ret < 0)
+			return ret;
+		arg = ret;
+		break;
+
+	case TEGRA_IO_PAD_DEEP_POWER_DOWN:
+		ret = tegra_io_rail_power_get_status(io_rail_id);
+		if (ret < 0)
+			return ret;
+		arg = !ret;
+		break;
+
+	default:
+		dev_err(tiopi->dev, "The parameter %d not supported\n", param);
+		return -EINVAL;
+	}
+
+	*config = pinconf_to_config_packed(param, (u16)arg);
+	return 0;
+}
+
+static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctldev,
+				    unsigned int pin, unsigned long *configs,
+				    unsigned int num_configs)
+{
+	struct tegra_io_pads_info *tiopi = pinctrl_dev_get_drvdata(pctldev);
+	struct tegra_io_pads_cfg_info *pad_cfg = &tiopi->pads_cfg[pin];
+	int io_rail_id = pad_cfg->io_rail_id;
+	int param;
+	u16 param_val;
+	int ret;
+	int i;
+
+	for (i = 0; i < num_configs; i++) {
+		param = pinconf_to_config_param(configs[i]);
+		param_val = pinconf_to_config_argument(configs[i]);
+
+		switch (param) {
+		case TEGRA_IO_RAIL_VOLTAGE:
+			ret = tegra_io_rail_voltage_set(io_rail_id, param_val);
+			if (ret < 0) {
+				dev_err(tiopi->dev,
+					"Failed to set voltage %d of pin %u: %d\n",
+					param_val, pin, ret);
+				return ret;
+			}
+			break;
+
+		case TEGRA_IO_PAD_DEEP_POWER_DOWN:
+			if (param_val)
+				ret = tegra_io_rail_power_off(io_rail_id);
+			else
+				ret = tegra_io_rail_power_on(io_rail_id);
+			if (ret < 0) {
+				dev_err(tiopi->dev,
+					"Failed to set DPD %d of pin %u: %d\n",
+					param_val, pin, ret);
+				return ret;
+			}
+			break;
+
+		default:
+			dev_err(tiopi->dev, "The parameter %d not supported\n",
+				param);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
+	.pin_config_get = tegra_io_pad_pinconf_get,
+	.pin_config_set = tegra_io_pad_pinconf_set,
+};
+
+static struct pinctrl_desc tegra_iop_pinctrl_desc = {
+	.name = "pinctrl-tegra-io-pads",
+	.pctlops = &tegra_iop_pinctrl_ops,
+	.confops = &tegra_io_pad_pinconf_ops,
+	.pins = tegra210_io_pads_pinctrl_desc,
+	.npins = ARRAY_SIZE(tegra210_io_pads_pinctrl_desc),
+	.custom_params = tegra_io_pads_cfg_params,
+	.num_custom_params = ARRAY_SIZE(tegra_io_pads_cfg_params),
+};
+
+static int tegra_iop_pinctrl_probe(struct platform_device *pdev)
+{
+	struct tegra_io_pads_info *tiopi;
+	struct device *dev = &pdev->dev;
+
+	tiopi = devm_kzalloc(&pdev->dev, sizeof(*tiopi), GFP_KERNEL);
+	if (!tiopi)
+		return -ENOMEM;
+
+	tiopi->dev = &pdev->dev;
+	tiopi->dev->of_node = pdev->dev.of_node;
+	tiopi->pads_cfg = tegra210_io_pads_cfg_info;
+	tiopi->num_pads_cfg = ARRAY_SIZE(tegra210_io_pads_cfg_info);
+
+	platform_set_drvdata(pdev, tiopi);
+
+	tiopi->pctl = pinctrl_register(&tegra_iop_pinctrl_desc, dev, tiopi);
+	if (IS_ERR(tiopi->pctl)) {
+		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+		return PTR_ERR(tiopi->pctl);
+	}
+
+	return 0;
+}
+
+static int tegra_iop_pinctrl_remove(struct platform_device *pdev)
+{
+	struct tegra_io_pads_info *tiopi = platform_get_drvdata(pdev);
+
+	pinctrl_unregister(tiopi->pctl);
+
+	return 0;
+}
+
+static const struct of_device_id tegra_io_pads_of_match[] = {
+	{ .compatible = "nvidia,tegra210-io-pad", },
+	{},
+};
+MODULE_DEVICE_TABLE(platform, tegra_iop_pinctrl_devtype);
+
+static struct platform_driver tegra_iop_pinctrl_driver = {
+	.driver = {
+		.name = "pinctrl-tegra-io-pad",
+		.of_match_table = tegra_io_pads_of_match,
+	},
+	.probe = tegra_iop_pinctrl_probe,
+	.remove = tegra_iop_pinctrl_remove,
+};
+
+module_platform_driver(tegra_iop_pinctrl_driver);
+
+MODULE_DESCRIPTION("NVIDIA TEGRA IO pad Control Driver");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_ALIAS("platform:pinctrl-tegra-io-pads");
+MODULE_LICENSE("GPL v2");
-- 
2.1.4

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#1379527 — Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads

On Tue, Apr 12, 2016 at 4:56 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:

> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
> or 3.3V I/O voltage levels. Also the IO pads can be configured
> for power down state if it is not used. SW needs to configure the
> voltage level of IO pads based on IO rail voltage and its power
> state based on platform usage.
>
> The voltage and power state configurations of pads are provided
> through pin control frameworks. Add pin control driver for Tegra's
> IO pads' voltage and power state configurations.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

(...)
> +config PINCTRL_TEGRA210_IO_PAD

Why does this need its own Kconfig option?
Can't you just unconditionally compile it in if
PINCTRL_TEGRA210 is selected, you seem to say
it is there on all these platforms anyway.

> +static const struct pinconf_generic_params tegra_io_pads_cfg_params[] = {
> +       {
> +               .property = "nvidia,io-rail-voltage",
> +               .param = TEGRA_IO_RAIL_VOLTAGE,
> +       }, {

What's so nvidia-specific about this?
We have power-source in
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
which takes a custom argument. This is obviously what you
are doing (selecting one of two rails), so use that binding.

> +               .property = "nvidia,io-pad-deep-power-down",
> +               .param = TEGRA_IO_PAD_DEEP_POWER_DOWN,
> +       },

Likewise the generic bindings have low-power-enable and
low-power-disable, this seems like a copy of low-power-enable;
Even if it needs a new binding, it doesn't seem very nVidia-specific
so then propose something to the generic bindings.

Even if Tegra is not using the generic code for handling the
standard bindings (GENERIC_PINCONF) it doesn't stop
you from using the generic bindings and contributing to them.

Historically you have a few custom bindings like these:

nvidia,pins
nvidia,function
nvidia,pull
nvidia,tristate

etc etc, but that is just unfortunate and due to preceding the
generic bindings. I would appreciate if you started to support
the generic bindings in parallel, but I'm not gonna push that issue.
However for *new* stuff, I don't want the custom bindings
to proliferate. Use the generic stuff, I'm trying to keep the weirdness
in one place, and the generic stuff is needed for standardization
across platforms going forward.

Yours,
Linus Walleij

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#1379558 — Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads

On Friday 15 April 2016 01:38 PM, Linus Walleij wrote:
> On Tue, Apr 12, 2016 at 4:56 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote:
>
>> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V
>> or 3.3V I/O voltage levels. Also the IO pads can be configured
>> for power down state if it is not used. SW needs to configure the
>> voltage level of IO pads based on IO rail voltage and its power
>> state based on platform usage.
>>
>> The voltage and power state configurations of pads are provided
>> through pin control frameworks. Add pin control driver for Tegra's
>> IO pads' voltage and power state configurations.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> (...)
>> +config PINCTRL_TEGRA210_IO_PAD
> Why does this need its own Kconfig option?
> Can't you just unconditionally compile it in if
> PINCTRL_TEGRA210 is selected, you seem to say
> it is there on all these platforms anyway.

Yes, it can be done. The reason I kept is that this driver needed T210 
onwards and not for older generation of SoC.

May be we can select from T210 pincontrol.


>
>> +static const struct pinconf_generic_params tegra_io_pads_cfg_params[] = {
>> +       {
>> +               .property = "nvidia,io-rail-voltage",
>> +               .param = TEGRA_IO_RAIL_VOLTAGE,
>> +       }, {
> What's so nvidia-specific about this?
> We have power-source in
> Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> which takes a custom argument. This is obviously what you
> are doing (selecting one of two rails), so use that binding.

Yes, I looked for the common property but did not found anything near to 
this.
My understating for power-source is that selecting the source of supply, 
not the voltages.
I am looking something  power-source-voltage-level.
Should we add this?




>
>> +               .property = "nvidia,io-pad-deep-power-down",
>> +               .param = TEGRA_IO_PAD_DEEP_POWER_DOWN,
>> +       },
> Likewise the generic bindings have low-power-enable and
> low-power-disable, this seems like a copy of low-power-enable;
When writing, I considered this property but was not able to fully 
convinced myself to use this but I think now I am fine to use this as 
you suggested.



>
> Even if Tegra is not using the generic code for handling the
> standard bindings (GENERIC_PINCONF) it doesn't stop
> you from using the generic bindings and contributing to them.
>
> Historically you have a few custom bindings like these:
>
> nvidia,pins
> nvidia,function
> nvidia,pull
> nvidia,tristate
>
> etc etc, but that is just unfortunate and due to preceding the
> generic bindings. I would appreciate if you started to support
> the generic bindings in parallel, but I'm not gonna push that issue.

Yaah, these are in my plate to cleanup. Let me work with Stephen, what 
he think here.

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#1379626 — Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads

On Fri, Apr 15, 2016 at 10:39 AM, Laxman Dewangan <ldewangan@nvidia.com> wrote:
> On Friday 15 April 2016 01:38 PM, Linus Walleij wrote:
>> On Tue, Apr 12, 2016 at 4:56 PM, Laxman Dewangan <ldewangan@nvidia.com>
>> wrote:

>>> +static const struct pinconf_generic_params tegra_io_pads_cfg_params[] =
>>> {
>>> +       {
>>> +               .property = "nvidia,io-rail-voltage",
>>> +               .param = TEGRA_IO_RAIL_VOLTAGE,
>>> +       }, {
>>
>> What's so nvidia-specific about this?
>> We have power-source in
>> Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
>> which takes a custom argument. This is obviously what you
>> are doing (selecting one of two rails), so use that binding.
>
> Yes, I looked for the common property but did not found anything near to
> this.
> My understating for power-source is that selecting the source of supply, not
> the voltages.

Well in a comment to the previous patch you just said that the
hardware actually does not regulate voltages. Isn't the actual case
that there are two rails with two different voltages, and you select one
of the rails for the pin?

That is not really selecting a voltage, that is selecting a power
rail.

> I am looking something  power-source-voltage-level.
> Should we add this?

If the pin could actually set a voltage level it would have a regulator.
I don't believe that. I think it is selecting one of two rails which
could theoretically hold two totally different voltages.

And that is what power-source is about.

>>> +               .property = "nvidia,io-pad-deep-power-down",
>>> +               .param = TEGRA_IO_PAD_DEEP_POWER_DOWN,
>>> +       },
>>
>> Likewise the generic bindings have low-power-enable and
>> low-power-disable, this seems like a copy of low-power-enable;
>
> When writing, I considered this property but was not able to fully convinced
> myself to use this but I think now I am fine to use this as you suggested.

Thanks.

>> Even if Tegra is not using the generic code for handling the
>> standard bindings (GENERIC_PINCONF) it doesn't stop
>> you from using the generic bindings and contributing to them.
>>
>> Historically you have a few custom bindings like these:
>>
>> nvidia,pins
>> nvidia,function
>> nvidia,pull
>> nvidia,tristate
>>
>> etc etc, but that is just unfortunate and due to preceding the
>> generic bindings. I would appreciate if you started to support
>> the generic bindings in parallel, but I'm not gonna push that issue.
>
> Yaah, these are in my plate to cleanup. Let me work with Stephen, what he
> think here.

Much appreciated, thanks!

Yours,
Linus Walleij

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