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Groups > linux.kernel > #1367137 > unrolled thread
| Started by | Jisheng Zhang <jszhang@marvell.com> |
|---|---|
| First post | 2016-03-30 14:00 +0200 |
| Last post | 2016-04-01 09:20 +0200 |
| Articles | 5 — 3 participants |
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[PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES Jisheng Zhang <jszhang@marvell.com> - 2016-03-30 14:00 +0200
Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES David Miller <davem@davemloft.net> - 2016-03-31 21:20 +0200
Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - 2016-03-31 22:40 +0200
Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES David Miller <davem@davemloft.net> - 2016-03-31 22:50 +0200
Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES Jisheng Zhang <jszhang@marvell.com> - 2016-04-01 09:20 +0200
| From | Jisheng Zhang <jszhang@marvell.com> |
|---|---|
| Date | 2016-03-30 14:00 +0200 |
| Subject | [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES |
| Message-ID | <rimX0-4NR-3@gated-at.bofh.it> |
The mvneta is also used in some Marvell berlin family SoCs which may have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE usage with L1_CACHE_BYTES. And since dma_alloc_coherent() is always cacheline size aligned, so remove the align checks. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> --- drivers/net/ethernet/marvell/mvneta.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index 577f7ca..5880871 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -260,7 +260,6 @@ #define MVNETA_VLAN_TAG_LEN 4 -#define MVNETA_CPU_D_CACHE_LINE_SIZE 32 #define MVNETA_TX_CSUM_DEF_SIZE 1600 #define MVNETA_TX_CSUM_MAX_SIZE 9800 #define MVNETA_ACC_MODE_EXT1 1 @@ -300,7 +299,7 @@ #define MVNETA_RX_PKT_SIZE(mtu) \ ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ ETH_HLEN + ETH_FCS_LEN, \ - MVNETA_CPU_D_CACHE_LINE_SIZE) + L1_CACHE_BYTES) #define IS_TSO_HEADER(txq, addr) \ ((addr >= txq->tso_hdrs_phys) && \ @@ -2764,9 +2763,6 @@ static int mvneta_rxq_init(struct mvneta_port *pp, if (rxq->descs == NULL) return -ENOMEM; - BUG_ON(rxq->descs != - PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); - rxq->last_desc = rxq->size - 1; /* Set Rx descriptors queue starting address */ @@ -2837,10 +2833,6 @@ static int mvneta_txq_init(struct mvneta_port *pp, if (txq->descs == NULL) return -ENOMEM; - /* Make sure descriptor address is cache line size aligned */ - BUG_ON(txq->descs != - PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); - txq->last_desc = txq->size - 1; /* Set maximum bandwidth for enabled TXQs */ -- 2.8.0.rc3
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| From | David Miller <davem@davemloft.net> |
|---|---|
| Date | 2016-03-31 21:20 +0200 |
| Subject | Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES |
| Message-ID | <riQil-1co-5@gated-at.bofh.it> |
| In reply to | #1367137 |
From: Jisheng Zhang <jszhang@marvell.com> Date: Wed, 30 Mar 2016 19:55:21 +0800 > The mvneta is also used in some Marvell berlin family SoCs which may > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE > usage with L1_CACHE_BYTES. > > And since dma_alloc_coherent() is always cacheline size aligned, so > remove the align checks. > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Applied.
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| From | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
|---|---|
| Date | 2016-03-31 22:40 +0200 |
| Subject | Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES |
| Message-ID | <riRxN-20c-27@gated-at.bofh.it> |
| In reply to | #1368562 |
Hello, On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote: > From: Jisheng Zhang <jszhang@marvell.com> > Date: Wed, 30 Mar 2016 19:55:21 +0800 > > > The mvneta is also used in some Marvell berlin family SoCs which may > > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE > > usage with L1_CACHE_BYTES. > > > > And since dma_alloc_coherent() is always cacheline size aligned, so > > remove the align checks. > > > > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> > > Applied. A new version of the patch was sent, which more rightfully uses cache_line_size(), see: "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size" Best regards, Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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| From | David Miller <davem@davemloft.net> |
|---|---|
| Date | 2016-03-31 22:50 +0200 |
| Subject | Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES |
| Message-ID | <riRHs-25a-7@gated-at.bofh.it> |
| In reply to | #1368653 |
From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Thu, 31 Mar 2016 22:37:35 +0200 > Hello, > > On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote: >> From: Jisheng Zhang <jszhang@marvell.com> >> Date: Wed, 30 Mar 2016 19:55:21 +0800 >> >> > The mvneta is also used in some Marvell berlin family SoCs which may >> > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE >> > usage with L1_CACHE_BYTES. >> > >> > And since dma_alloc_coherent() is always cacheline size aligned, so >> > remove the align checks. >> > >> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> >> >> Applied. > > A new version of the patch was sent, which more rightfully uses > cache_line_size(), see: > > "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size" Sorry about that. Send me a realtive fixup patch if you like. Thanks.
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| From | Jisheng Zhang <jszhang@marvell.com> |
|---|---|
| Date | 2016-04-01 09:20 +0200 |
| Subject | Re: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with L1_CACHE_BYTES |
| Message-ID | <rj1x8-Xr-27@gated-at.bofh.it> |
| In reply to | #1368680 |
Hi David, Thomas, On Thu, 31 Mar 2016 16:47:10 -0400 David Miller wrote: > From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > Date: Thu, 31 Mar 2016 22:37:35 +0200 > > > Hello, > > > > On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote: > >> From: Jisheng Zhang <jszhang@marvell.com> > >> Date: Wed, 30 Mar 2016 19:55:21 +0800 > >> > >> > The mvneta is also used in some Marvell berlin family SoCs which may > >> > have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE > >> > usage with L1_CACHE_BYTES. > >> > > >> > And since dma_alloc_coherent() is always cacheline size aligned, so > >> > remove the align checks. > >> > > >> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> > >> > >> Applied. > > > > A new version of the patch was sent, which more rightfully uses > > cache_line_size(), see: > > > > "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size" > > Sorry about that. > > Send me a realtive fixup patch if you like. > Sorry about inconvenience, I'll send out fixup patch. Thanks, Jisheng
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