Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1359894 > unrolled thread

[PATCH 00/15] Add support for Tegra210 AGIC

Back to article view | Back to linux.kernel

Contents

  [PATCH 00/15] Add support for Tegra210 AGIC Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
    [PATCH 05/15] irqchip: Mask the non-type/sense bits when translating an IRQ Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
    [PATCH 09/15] irqchip/gic: Don't initialise chip if mapping IO space fails Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
    [PATCH 02/15] ARM: OMAP: Correct interrupt type for ARM TWD Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
      Re: [PATCH 02/15] ARM: OMAP: Correct interrupt type for ARM TWD Grygorii Strashko <grygorii.strashko@ti.com> - 2016-03-18 16:50 +0100
        Re: [PATCH 02/15] ARM: OMAP: Correct interrupt type for ARM TWD Jon Hunter <jonathanh@nvidia.com> - 2016-03-29 16:10 +0200
          Re: [PATCH 02/15] ARM: OMAP: Correct interrupt type for ARM TWD Tony Lindgren <tony@atomide.com> - 2016-03-30 23:30 +0200
    [PATCH 10/15] irqchip/gic: Remove static irq_chip definition for eoimode1 Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
      Re: [PATCH 10/15] irqchip/gic: Remove static irq_chip definition for eoimode1 Linus Walleij <linus.walleij@linaro.org> - 2016-03-22 12:50 +0100
    [PATCH 08/15] genirq: Add runtime power management support for IRQ chips Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
      Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Marc Zyngier <marc.zyngier@arm.com> - 2016-03-17 16:10 +0100
        Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 16:20 +0100
          Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Marc Zyngier <marc.zyngier@arm.com> - 2016-03-17 16:30 +0100
            Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Linus Walleij <linus.walleij@linaro.org> - 2016-03-22 12:50 +0100
      Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Thomas Gleixner <tglx@linutronix.de> - 2016-03-17 16:10 +0100
        Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 16:50 +0100
      Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Grygorii Strashko <grygorii.strashko@ti.com> - 2016-03-18 12:20 +0100
        Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Jon Hunter <jonathanh@nvidia.com> - 2016-03-18 13:30 +0100
          Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Grygorii Strashko <grygorii.strashko@ti.com> - 2016-03-18 15:30 +0100
            Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Jon Hunter <jonathanh@nvidia.com> - 2016-03-18 15:50 +0100
              Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Jon Hunter <jonathanh@nvidia.com> - 2016-03-18 16:00 +0100
                Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Grygorii Strashko <grygorii.strashko@ti.com> - 2016-03-18 19:00 +0100
                  Re: [PATCH 08/15] genirq: Add runtime power management support for  IRQ chips Jon Hunter <jonathanh@nvidia.com> - 2016-03-21 11:10 +0100
    [PATCH 12/15] irqchip/gic: Pass GIC pointer to save/restore functions Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
    [PATCH 13/15] irqchip/gic: Prepare for adding platform driver Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
      Re: [PATCH 13/15] irqchip/gic: Prepare for adding platform driver Geert Uytterhoeven <geert@linux-m68k.org> - 2016-03-29 15:10 +0200
        Re: [PATCH 13/15] irqchip/gic: Prepare for adding platform driver Jon Hunter <jonathanh@nvidia.com> - 2016-03-29 16:00 +0200
    [PATCH 04/15] irqchip/gic: WARN if setting the interrupt type fails Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
      Re: [PATCH 04/15] irqchip/gic: WARN if setting the interrupt type  fails Thomas Gleixner <tglx@linutronix.de> - 2016-03-17 16:00 +0100
        Re: [PATCH 04/15] irqchip/gic: WARN if setting the interrupt type  fails Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 16:10 +0100
          Re: [PATCH 04/15] irqchip/gic: WARN if setting the interrupt type  fails Jason Cooper <jason@lakedaemon.net> - 2016-03-17 16:20 +0100
            Re: [PATCH 04/15] irqchip/gic: WARN if setting the interrupt type  fails Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 17:30 +0100
              Re: [PATCH 04/15] irqchip/gic: WARN if setting the interrupt type fails Geert Uytterhoeven <geert@linux-m68k.org> - 2016-03-18 10:30 +0100
                Re: [PATCH 04/15] irqchip/gic: WARN if setting the interrupt type  fails Jon Hunter <jonathanh@nvidia.com> - 2016-03-18 11:00 +0100
                  Re: [PATCH 04/15] irqchip/gic: WARN if setting the interrupt type fails Geert Uytterhoeven <geert@linux-m68k.org> - 2016-03-18 11:30 +0100
    [PATCH 03/15] irqchip/gic: Don't unnecessarily write the IRQ configuration Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
    [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
      Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Rob Herring <robh+dt@kernel.org> - 2016-03-17 21:20 +0100
        Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Jon Hunter <jonathanh@nvidia.com> - 2016-03-18 09:40 +0100
      Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Geert Uytterhoeven <geert@linux-m68k.org> - 2016-03-18 10:20 +0100
        Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Jon Hunter <jonathanh@nvidia.com> - 2016-03-18 11:20 +0100
          Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Geert Uytterhoeven <geert@linux-m68k.org> - 2016-03-18 12:00 +0100
            Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Jon Hunter <jonathanh@nvidia.com> - 2016-03-18 12:00 +0100
              Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Geert Uytterhoeven <geert@linux-m68k.org> - 2016-03-18 13:10 +0100
                Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Grygorii Strashko <grygorii.strashko@ti.com> - 2016-03-18 13:50 +0100
                  Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Geert Uytterhoeven <geert@linux-m68k.org> - 2016-03-18 14:10 +0100
                    Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Grygorii Strashko <grygorii.strashko@ti.com> - 2016-03-18 19:40 +0100
                Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from  binding document Jon Hunter <jonathanh@nvidia.com> - 2016-03-18 13:50 +0100
    [PATCH 11/15] irqchip/gic: Return an error if GIC initialisation fails Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100
    [PATCH 15/15] irqchip/gic: Add support for tegra AGIC interrupt controller Jon Hunter <jonathanh@nvidia.com> - 2016-03-17 15:30 +0100

Page 3 of 3 — ← Prev page 1 2 [3]

#1360497 — Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document

On 18/03/16 09:13, Geert Uytterhoeven wrote:
> Hi Jon,
> 
> On Thu, Mar 17, 2016 at 3:19 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
>> Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power
>> Domain properties") documented optional clock and power-dmoain properties
>> for the ARM GIC. Currently, there are no users of these and for the
>> Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a
>> functional clock and interface clock, that need to be enabled.
> 
> The reason that there are no users for this is twofold:
>   1. The GIC driver doesn't have Runtime PM support yet,
>   2. There was no clean way to prevent the GIC's clock from being disabled.
> Due to this, adding the clocks to the DTSes would mean that they will be
> disabled during boot up as unused clocks, leading to a system lock-up.
> 
> I had hoped your series would fix part 1. I gave it a try on r8a7791/koelsch,
> but unfortunately it seems the platform driver only supports non-root
> controllers, while the r8a7791 GIC is the primary one...

Can you try making the following change ...

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9e7cf7abf757..2e971e600036 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -1372,7 +1372,7 @@ static int gic_probe(struct platform_device *pdev)
        void __iomem *dist_base;
        void __iomem *cpu_base;
        u32 percpu_offset;
-       int ret, irq;
+       int ret, irq = 0;
 
        if (dev->of_node == NULL)
                return -EINVAL;
@@ -1393,11 +1393,8 @@ static int gic_probe(struct platform_device *pdev)
        if (ret < 0)
                goto rpm_disable;
 
-       irq = irq_of_parse_and_map(dev->of_node, 0);
-       if (!irq) {
-               ret = -EINVAL;
-               goto rpm_put;
-       }
+       if (of_irq_count(dev->of_node) > 0)
+               irq = irq_of_parse_and_map(dev->of_node, 0);
 
        ret = gic_of_setup(dev->of_node, &dist_base, &cpu_base, &percpu_offset);
        if (ret)
@@ -1411,7 +1408,8 @@ static int gic_probe(struct platform_device *pdev)
 
        gic->chip.parent = dev;
 
-       irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, gic);
+       if (irq)
+               irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, gic);
 
        pm_runtime_put(dev);
 
@@ -1424,7 +1422,6 @@ gic_unmap:
        iounmap(cpu_base);
 irq_dispose:
        irq_dispose_mapping(irq);
-rpm_put:
        pm_runtime_put_sync(dev);
 rpm_disable:
        pm_runtime_disable(dev);

 
> Alternatively, part 2 can to be fixed by "clk: introduce CLK_ENABLE_HAND_OFF
> flag", combined with the clock driver setting the flag when needed.
> Unfortunately that patch is not yet upstream, and not even in -next.
> Note that drivers/clk/renesas/renesas-cpg-mssr.c already handles
> CLK_ENABLE_HAND_OFF if present, and else just ignores the clock.
> So I could already add the clock to r8a7795.dtsi, which uses that driver.
> 
> For older SoCs, the module clocks are described in the dtsi, and I would need a
> crude hack to enable CLK_ENABLE_HAND_OFF in the clock driver.
> 
>> To allow flexibility, drop the 'clock-names' from the GIC binding and
>> just provide a list of clocks which the driver can parse. It is assumed
>> that any clocks that are listed, need to be enabled in order to access
>> the GIC.
> 
> Originally I just wanted to have "clocks", and let the details be handled by
> SoC-specific code. However, Mark Rutland insisted on using the clock naming
> from the GIC TRMs, as the number of clocks and their names depend on the
> GIC variant.
> 
> Apparently they also depend on the SoC...

Yes this case is a little different because the GIC is a 2nd level GIC.

Cheers
Jon

[toc] | [prev] | [next] | [standalone]

#1360524 — Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document

Hi Jon,

On Fri, Mar 18, 2016 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
> On 18/03/16 09:13, Geert Uytterhoeven wrote:
>> On Thu, Mar 17, 2016 at 3:19 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>> Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power
>>> Domain properties") documented optional clock and power-dmoain properties
>>> for the ARM GIC. Currently, there are no users of these and for the
>>> Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a
>>> functional clock and interface clock, that need to be enabled.
>>
>> The reason that there are no users for this is twofold:
>>   1. The GIC driver doesn't have Runtime PM support yet,
>>   2. There was no clean way to prevent the GIC's clock from being disabled.
>> Due to this, adding the clocks to the DTSes would mean that they will be
>> disabled during boot up as unused clocks, leading to a system lock-up.
>>
>> I had hoped your series would fix part 1. I gave it a try on r8a7791/koelsch,
>> but unfortunately it seems the platform driver only supports non-root
>> controllers, while the r8a7791 GIC is the primary one...
>
> Can you try making the following change ...

Thanks! I gave it a try, but no difference.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[toc] | [prev] | [next] | [standalone]

#1360525 — Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document

On 18/03/16 10:52, Geert Uytterhoeven wrote:
> Hi Jon,
> 
> On Fri, Mar 18, 2016 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>> On 18/03/16 09:13, Geert Uytterhoeven wrote:
>>> On Thu, Mar 17, 2016 at 3:19 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>> Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power
>>>> Domain properties") documented optional clock and power-dmoain properties
>>>> for the ARM GIC. Currently, there are no users of these and for the
>>>> Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a
>>>> functional clock and interface clock, that need to be enabled.
>>>
>>> The reason that there are no users for this is twofold:
>>>   1. The GIC driver doesn't have Runtime PM support yet,
>>>   2. There was no clean way to prevent the GIC's clock from being disabled.
>>> Due to this, adding the clocks to the DTSes would mean that they will be
>>> disabled during boot up as unused clocks, leading to a system lock-up.
>>>
>>> I had hoped your series would fix part 1. I gave it a try on r8a7791/koelsch,
>>> but unfortunately it seems the platform driver only supports non-root
>>> controllers, while the r8a7791 GIC is the primary one...
>>
>> Can you try making the following change ...
> 
> Thanks! I gave it a try, but no difference.

I assume you added the appropriate compatible flag? Any more details you
can share about why it is not working? Is it not registered early enough?

Jon

[toc] | [prev] | [next] | [standalone]

#1360556 — Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document

Hi Jon,

On Fri, Mar 18, 2016 at 11:56 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
> On 18/03/16 10:52, Geert Uytterhoeven wrote:
>> On Fri, Mar 18, 2016 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>> On 18/03/16 09:13, Geert Uytterhoeven wrote:
>>>> On Thu, Mar 17, 2016 at 3:19 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>> Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power
>>>>> Domain properties") documented optional clock and power-dmoain properties
>>>>> for the ARM GIC. Currently, there are no users of these and for the
>>>>> Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a
>>>>> functional clock and interface clock, that need to be enabled.
>>>>
>>>> The reason that there are no users for this is twofold:
>>>>   1. The GIC driver doesn't have Runtime PM support yet,
>>>>   2. There was no clean way to prevent the GIC's clock from being disabled.
>>>> Due to this, adding the clocks to the DTSes would mean that they will be
>>>> disabled during boot up as unused clocks, leading to a system lock-up.
>>>>
>>>> I had hoped your series would fix part 1. I gave it a try on r8a7791/koelsch,
>>>> but unfortunately it seems the platform driver only supports non-root
>>>> controllers, while the r8a7791 GIC is the primary one...
>>>
>>> Can you try making the following change ...
>>
>> Thanks! I gave it a try, but no difference.
>
> I assume you added the appropriate compatible flag? Any more details you

Doh... bad assumption... Silly me.

> can share about why it is not working? Is it not registered early enough?

With

+       { .compatible = "arm,gic-400", },

the kernel no longer crashes due to accessing the GIC registers while the
GIC module clock is disabled.

However, the system doesn't boot completely, and time outs on SPI transfers
make me believe interrupts are not working.
Both with and without "the following change".

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[toc] | [prev] | [next] | [standalone]

#1360581 — Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document

On 03/18/2016 02:05 PM, Geert Uytterhoeven wrote:
> Hi Jon,
> 
> On Fri, Mar 18, 2016 at 11:56 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>> On 18/03/16 10:52, Geert Uytterhoeven wrote:
>>> On Fri, Mar 18, 2016 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>> On 18/03/16 09:13, Geert Uytterhoeven wrote:
>>>>> On Thu, Mar 17, 2016 at 3:19 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>>> Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power
>>>>>> Domain properties") documented optional clock and power-dmoain properties
>>>>>> for the ARM GIC. Currently, there are no users of these and for the
>>>>>> Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a
>>>>>> functional clock and interface clock, that need to be enabled.
>>>>>
>>>>> The reason that there are no users for this is twofold:
>>>>>    1. The GIC driver doesn't have Runtime PM support yet,
>>>>>    2. There was no clean way to prevent the GIC's clock from being disabled.
>>>>> Due to this, adding the clocks to the DTSes would mean that they will be
>>>>> disabled during boot up as unused clocks, leading to a system lock-up.
>>>>>
>>>>> I had hoped your series would fix part 1. I gave it a try on r8a7791/koelsch,
>>>>> but unfortunately it seems the platform driver only supports non-root
>>>>> controllers, while the r8a7791 GIC is the primary one...
>>>>
>>>> Can you try making the following change ...
>>>
>>> Thanks! I gave it a try, but no difference.
>>
>> I assume you added the appropriate compatible flag? Any more details you
> 
> Doh... bad assumption... Silly me.
> 
>> can share about why it is not working? Is it not registered early enough?
> 
> With
> 
> +       { .compatible = "arm,gic-400", },
> 
> the kernel no longer crashes due to accessing the GIC registers while the
> GIC module clock is disabled.
> 
> However, the system doesn't boot completely, and time outs on SPI transfers
> make me believe interrupts are not working.
> Both with and without "the following change".
> 

Is my assumption correct that you are trying to enable RPM for primary GIC controller?


If yes it may help to take a look on clocksource drivers which use early_platform_device/driver
sh_cmt.c sh_mtu2.c sh_tmu.c

The primary interrupt controller is initialized very early init_IRQ->irqchip_init->of_irq_init()
(IRQCHIP_DECLARE) and, at least as i can see from st_xxx code, the same case is valid for 
clocksource devices and it was solved using early_platform_device/drive staff.


-- 
regards,
-grygorii

[toc] | [prev] | [next] | [standalone]

#1360602 — Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document

Hi Grygorii,

On Fri, Mar 18, 2016 at 1:47 PM, Grygorii Strashko
<grygorii.strashko@ti.com> wrote:
> On 03/18/2016 02:05 PM, Geert Uytterhoeven wrote:
>> On Fri, Mar 18, 2016 at 11:56 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>> On 18/03/16 10:52, Geert Uytterhoeven wrote:
>>>> On Fri, Mar 18, 2016 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>> On 18/03/16 09:13, Geert Uytterhoeven wrote:
>>>>>> On Thu, Mar 17, 2016 at 3:19 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>>>> Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power
>>>>>>> Domain properties") documented optional clock and power-dmoain properties
>>>>>>> for the ARM GIC. Currently, there are no users of these and for the
>>>>>>> Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a
>>>>>>> functional clock and interface clock, that need to be enabled.
>>>>>>
>>>>>> The reason that there are no users for this is twofold:
>>>>>>    1. The GIC driver doesn't have Runtime PM support yet,
>>>>>>    2. There was no clean way to prevent the GIC's clock from being disabled.
>>>>>> Due to this, adding the clocks to the DTSes would mean that they will be
>>>>>> disabled during boot up as unused clocks, leading to a system lock-up.
>>>>>>
>>>>>> I had hoped your series would fix part 1. I gave it a try on r8a7791/koelsch,
>>>>>> but unfortunately it seems the platform driver only supports non-root
>>>>>> controllers, while the r8a7791 GIC is the primary one...
>>>>>
>>>>> Can you try making the following change ...
>>>>
>>>> Thanks! I gave it a try, but no difference.
>>>
>>> I assume you added the appropriate compatible flag? Any more details you
>>
>> Doh... bad assumption... Silly me.
>>
>>> can share about why it is not working? Is it not registered early enough?
>>
>> With
>>
>> +       { .compatible = "arm,gic-400", },
>>
>> the kernel no longer crashes due to accessing the GIC registers while the
>> GIC module clock is disabled.
>>
>> However, the system doesn't boot completely, and time outs on SPI transfers
>> make me believe interrupts are not working.
>> Both with and without "the following change".
>>
>
> Is my assumption correct that you are trying to enable RPM for primary GIC controller?

That's correct.

> If yes it may help to take a look on clocksource drivers which use early_platform_device/driver
> sh_cmt.c sh_mtu2.c sh_tmu.c
>
> The primary interrupt controller is initialized very early init_IRQ->irqchip_init->of_irq_init()
> (IRQCHIP_DECLARE) and, at least as i can see from st_xxx code, the same case is valid for
> clocksource devices and it was solved using early_platform_device/drive staff.

The GIC now depends on the clock driver, which may be a real platform driver,
not initialized from CLK_OF_DECLARE().

Or do you mean to make the clock driver an early platform driver?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[toc] | [prev] | [next] | [standalone]

#1360863 — Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document

On 03/18/2016 03:02 PM, Geert Uytterhoeven wrote:
> Hi Grygorii,
> 
> On Fri, Mar 18, 2016 at 1:47 PM, Grygorii Strashko
> <grygorii.strashko@ti.com> wrote:
>> On 03/18/2016 02:05 PM, Geert Uytterhoeven wrote:
>>> On Fri, Mar 18, 2016 at 11:56 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>> On 18/03/16 10:52, Geert Uytterhoeven wrote:
>>>>> On Fri, Mar 18, 2016 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>>> On 18/03/16 09:13, Geert Uytterhoeven wrote:
>>>>>>> On Thu, Mar 17, 2016 at 3:19 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>>>>> Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power
>>>>>>>> Domain properties") documented optional clock and power-dmoain properties
>>>>>>>> for the ARM GIC. Currently, there are no users of these and for the
>>>>>>>> Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a
>>>>>>>> functional clock and interface clock, that need to be enabled.
>>>>>>>
>>>>>>> The reason that there are no users for this is twofold:
>>>>>>>     1. The GIC driver doesn't have Runtime PM support yet,
>>>>>>>     2. There was no clean way to prevent the GIC's clock from being disabled.
>>>>>>> Due to this, adding the clocks to the DTSes would mean that they will be
>>>>>>> disabled during boot up as unused clocks, leading to a system lock-up.
>>>>>>>
>>>>>>> I had hoped your series would fix part 1. I gave it a try on r8a7791/koelsch,
>>>>>>> but unfortunately it seems the platform driver only supports non-root
>>>>>>> controllers, while the r8a7791 GIC is the primary one...
>>>>>>
>>>>>> Can you try making the following change ...
>>>>>
>>>>> Thanks! I gave it a try, but no difference.
>>>>
>>>> I assume you added the appropriate compatible flag? Any more details you
>>>
>>> Doh... bad assumption... Silly me.
>>>
>>>> can share about why it is not working? Is it not registered early enough?
>>>
>>> With
>>>
>>> +       { .compatible = "arm,gic-400", },
>>>
>>> the kernel no longer crashes due to accessing the GIC registers while the
>>> GIC module clock is disabled.
>>>
>>> However, the system doesn't boot completely, and time outs on SPI transfers
>>> make me believe interrupts are not working.
>>> Both with and without "the following change".
>>>
>>
>> Is my assumption correct that you are trying to enable RPM for primary GIC controller?
> 
> That's correct.
> 
>> If yes it may help to take a look on clocksource drivers which use early_platform_device/driver
>> sh_cmt.c sh_mtu2.c sh_tmu.c
>>
>> The primary interrupt controller is initialized very early init_IRQ->irqchip_init->of_irq_init()
>> (IRQCHIP_DECLARE) and, at least as i can see from st_xxx code, the same case is valid for
>> clocksource devices and it was solved using early_platform_device/drive staff.
> 
> The GIC now depends on the clock driver, which may be a real platform driver,
> not initialized from CLK_OF_DECLARE().

Clock need to be accessible, but, seems, there is another issue -
if you will try to use gic_driver by just adding compatible string then,
most probably, gic_init_bases() will be called twice:
1: init_IRQ->irqchip_init->of_irq_init()->__gic_init_bases()->gic_init_bases()
2: gic_probe->gic_init_bases()


And GIC data will be replaced on the fly ;P

> 
> Or do you mean to make the clock driver an early platform driver?

I can't say definitely - I've just studied it some time ago, but did not try it by myself.



-- 
regards,
-grygorii

[toc] | [prev] | [next] | [standalone]

#1360583 — Re: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document

On 18/03/16 12:05, Geert Uytterhoeven wrote:
> Hi Jon,
> 
> On Fri, Mar 18, 2016 at 11:56 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>> On 18/03/16 10:52, Geert Uytterhoeven wrote:
>>> On Fri, Mar 18, 2016 at 11:13 AM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>> On 18/03/16 09:13, Geert Uytterhoeven wrote:
>>>>> On Thu, Mar 17, 2016 at 3:19 PM, Jon Hunter <jonathanh@nvidia.com> wrote:
>>>>>> Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power
>>>>>> Domain properties") documented optional clock and power-dmoain properties
>>>>>> for the ARM GIC. Currently, there are no users of these and for the
>>>>>> Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a
>>>>>> functional clock and interface clock, that need to be enabled.
>>>>>
>>>>> The reason that there are no users for this is twofold:
>>>>>   1. The GIC driver doesn't have Runtime PM support yet,
>>>>>   2. There was no clean way to prevent the GIC's clock from being disabled.
>>>>> Due to this, adding the clocks to the DTSes would mean that they will be
>>>>> disabled during boot up as unused clocks, leading to a system lock-up.
>>>>>
>>>>> I had hoped your series would fix part 1. I gave it a try on r8a7791/koelsch,
>>>>> but unfortunately it seems the platform driver only supports non-root
>>>>> controllers, while the r8a7791 GIC is the primary one...
>>>>
>>>> Can you try making the following change ...
>>>
>>> Thanks! I gave it a try, but no difference.
>>
>> I assume you added the appropriate compatible flag? Any more details you
> 
> Doh... bad assumption... Silly me.
> 
>> can share about why it is not working? Is it not registered early enough?
> 
> With
> 
> +       { .compatible = "arm,gic-400", },
> 
> the kernel no longer crashes due to accessing the GIC registers while the
> GIC module clock is disabled.
> 
> However, the system doesn't boot completely, and time outs on SPI transfers
> make me believe interrupts are not working.
> Both with and without "the following change".

Yes, I recall now why I did not support primary controllers and it is
because you need to call set_smp_cross_call() (for SMP) and
set_handle_irq(). Both of which are located in the __init section and
need to be called early during boot. So to make this work for primary
controllers, more work would need to be done.

Jon

[toc] | [prev] | [next] | [standalone]

#1359907 — [PATCH 11/15] irqchip/gic: Return an error if GIC initialisation fails

If the GIC initialisation fails, then currently we do not return an error
or clean-up afterwards. Although for root controllers, this failure may be
fatal anyway, for secondary controllers, it may not be fatal and so return
an error on failure and clean-up.

For non-banked GIC controllers, make sure that we free any memory
allocated if we fail to initialise the IRQ domain. Please note that
free_percpu() only frees memory if the pointer passed to it is not NULL
and so it is unnecessary to check if both pointers are valid or not.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/irqchip/irq-gic.c | 57 ++++++++++++++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 16 deletions(-)

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index b0a781f8c450..42a1412b5186 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -999,13 +999,13 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
 	.unmap = gic_irq_domain_unmap,
 };
 
-static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
+static int __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 			   void __iomem *dist_base, void __iomem *cpu_base,
 			   u32 percpu_offset, struct fwnode_handle *handle)
 {
 	irq_hw_number_t hwirq_base;
 	struct gic_chip_data *gic;
-	int gic_irqs, irq_base, i;
+	int gic_irqs, irq_base, i, ret;
 
 	BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
 
@@ -1030,17 +1030,16 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 		gic->chip.irq_set_affinity = gic_set_affinity;
 #endif
 
-#ifdef CONFIG_GIC_NON_BANKED
-	if (percpu_offset) { /* Frankein-GIC without banked registers... */
+	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) {
+		/* Frankein-GIC without banked registers... */
 		unsigned int cpu;
 
 		gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
 		gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
 		if (WARN_ON(!gic->dist_base.percpu_base ||
 			    !gic->cpu_base.percpu_base)) {
-			free_percpu(gic->dist_base.percpu_base);
-			free_percpu(gic->cpu_base.percpu_base);
-			return;
+			ret = -ENOMEM;
+			goto error;
 		}
 
 		for_each_possible_cpu(cpu) {
@@ -1052,9 +1051,8 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 		}
 
 		gic_set_base_accessor(gic, gic_get_percpu_base);
-	} else
-#endif
-	{			/* Normal, sane GIC... */
+	} else {
+		/* Normal, sane GIC... */
 		WARN(percpu_offset,
 		     "GIC_NON_BANKED not enabled, ignoring %08x offset!",
 		     percpu_offset);
@@ -1104,8 +1102,10 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 					hwirq_base, &gic_irq_domain_ops, gic);
 	}
 
-	if (WARN_ON(!gic->domain))
-		return;
+	if (WARN_ON(!gic->domain)) {
+		ret = -ENODEV;
+		goto error;
+	}
 
 	if (gic_nr == 0) {
 		/*
@@ -1127,6 +1127,18 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 	gic_dist_init(gic);
 	gic_cpu_init(gic);
 	gic_pm_init(gic);
+
+	return 0;
+
+error:
+	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) {
+		free_percpu(gic->dist_base.percpu_base);
+		free_percpu(gic->cpu_base.percpu_base);
+	}
+
+	kfree(gic->chip.name);
+
+	return ret;
 }
 
 void __init gic_init(unsigned int gic_nr, int irq_start,
@@ -1187,7 +1199,7 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 	void __iomem *cpu_base;
 	void __iomem *dist_base;
 	u32 percpu_offset;
-	int irq;
+	int irq, ret;
 
 	if (WARN_ON(!node))
 		return -ENODEV;
@@ -1212,8 +1224,14 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 	if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
 		percpu_offset = 0;
 
-	__gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset,
+	ret = __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset,
 			 &node->fwnode);
+	if (ret) {
+		iounmap(dist_base);
+		iounmap(cpu_base);
+		return ret;
+	}
+
 	if (!gic_cnt)
 		gic_init_physaddr(node);
 
@@ -1302,7 +1320,7 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
 	struct acpi_madt_generic_distributor *dist;
 	void __iomem *cpu_base, *dist_base;
 	struct fwnode_handle *domain_handle;
-	int count;
+	int count, ret;
 
 	/* Collect CPU base addresses */
 	count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
@@ -1345,7 +1363,14 @@ static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
 		return -ENOMEM;
 	}
 
-	__gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
+	ret = __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
+	if (ret) {
+		pr_err("Failed to initialise GIC\n");
+		irq_domain_free_fwnode(domain_handle);
+		iounmap(cpu_base);
+		iounmap(dist_base);
+		return ret;
+	}
 
 	acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
 
-- 
2.1.4

[toc] | [prev] | [next] | [standalone]

#1359910 — [PATCH 15/15] irqchip/gic: Add support for tegra AGIC interrupt controller

Add a driver for the Tegra-AGIC interrupt controller which is compatible
with the ARM GIC-400 interrupt controller.

The Tegra AGIC (Audio GIC) is part of the Audio Processing Engine (APE) on
Tegra210 and can route interrupts to either the GIC for the CPU subsystem
or the Audio DSP (ADSP) within the APE. The AGIC uses CPU interface 0 to
route interrupts to the CPU GIC and CPU interface 1 to route interrupts to
the ADSP.

The APE is located within its own power domain on the chip and so the
AGIC needs to manage both the power domain and its clocks. Commit
afbbd2338176 ("irqchip/gic: Document optional Clock and Power Domain
properties") adding clock and power-domain properties to the GIC binding
and so the aim would be to make use of these to handle power management
(however, this is very much dependent upon adding support for generic
PM domains for Tegra which is still a work-in-progress).

With the AGIC being located in a different power domain to the main CPU
cluster this means that:
1. The interrupt controller cannot be registered via IRQCHIP_DECLARE()
   because it needs to be registered as a platform device so that the
   generic PM domain core will ensure that the power domain is available
   before probing.
2. The interrupt controller cannot be suspended/restored based upon
   changes in the CPU power state and needs to use runtime-pm instead.

The GIC platform driver has been implemented by making the following
changes to the core GIC driver:
1. Remove the dependency on CONFIG_CPU_PM from PM specific variables and
   functions so that they can be used by the platform driver even when
   CONFIG_CPU_PM is not selected.
2. Move the code that maps the GIC registers and parses the device-tree
   blob into a new function called gic_of_setup() that can be used by
   both the platform driver as well as the existing driver.
3. Add and register platform driver for the GIC. The platform driver
   uses the PM_CLK framework for managing the clocks used by the GIC
   and so select CONFIG_PM_CLK.

Finally, a couple other notes on the implementation are:
1. Currently the GIC platform driver only supports non-root GICs and
   assumes that the GIC has a parent interrupt. It is assumed that
   root interrupt controllers need to be initialised early.
2. There is no specific suspend handling for platform devices because
   non-wakeup interrupts will be disabled by the kernel during late
   suspend.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 .../bindings/interrupt-controller/arm,gic.txt      |   1 +
 drivers/irqchip/Kconfig                            |   1 +
 drivers/irqchip/irq-gic.c                          | 210 ++++++++++++++++++---
 3 files changed, 189 insertions(+), 23 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
index c471d1a7a8ea..9d84a86d0934 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
@@ -21,6 +21,7 @@ Main node required properties:
 	"arm,pl390"
 	"arm,tc11mp-gic"
 	"brcm,brahma-b15-gic"
+	"nvidia,tegra210-agic"
 	"qcom,msm-8660-qgic"
 	"qcom,msm-qgic2"
 - interrupt-controller : Identifies the node as an interrupt controller
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 7e8c441ff2de..ececa3cb6c0a 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -7,6 +7,7 @@ config ARM_GIC
 	select IRQ_DOMAIN
 	select IRQ_DOMAIN_HIERARCHY
 	select MULTI_IRQ_HANDLER
+	select PM_CLK
 
 config ARM_GIC_MAX_NR
 	int
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 7cc5380db298..9e7cf7abf757 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -26,6 +26,7 @@
 #include <linux/module.h>
 #include <linux/list.h>
 #include <linux/smp.h>
+#include <linux/clk.h>
 #include <linux/cpu.h>
 #include <linux/cpu_pm.h>
 #include <linux/cpumask.h>
@@ -37,6 +38,9 @@
 #include <linux/irqdomain.h>
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
+#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_runtime.h>
 #include <linux/slab.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/chained_irq.h>
@@ -72,7 +76,6 @@ struct gic_chip_data {
 	struct irq_chip chip;
 	union gic_base dist_base;
 	union gic_base cpu_base;
-#ifdef CONFIG_CPU_PM
 	u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
 	u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
 	u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
@@ -80,7 +83,6 @@ struct gic_chip_data {
 	u32 __percpu *saved_ppi_enable;
 	u32 __percpu *saved_ppi_active;
 	u32 __percpu *saved_ppi_conf;
-#endif
 	struct irq_domain *domain;
 	unsigned int gic_irqs;
 #ifdef CONFIG_GIC_NON_BANKED
@@ -512,7 +514,6 @@ int gic_cpu_if_down(unsigned int gic_nr)
 	return 0;
 }
 
-#ifdef CONFIG_CPU_PM
 /*
  * Saves the GIC distributor registers during suspend or idle.  Must be called
  * with interrupts disabled but before powering down the GIC.  After calling
@@ -728,11 +729,6 @@ static void gic_pm_init(struct gic_chip_data *gic)
 	if (gic == &gic_data[0])
 		cpu_pm_register_notifier(&gic_notifier_block);
 }
-#else
-static void gic_pm_init(struct gic_chip_data *gic)
-{
-}
-#endif
 
 #ifdef CONFIG_SMP
 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
@@ -1227,27 +1223,42 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
 	return true;
 }
 
-int __init
-gic_of_init(struct device_node *node, struct device_node *parent)
+static int gic_of_setup(struct device_node *node, void __iomem **dist_base,
+			void __iomem **cpu_base, u32 *percpu_offset)
 {
-	void __iomem *cpu_base;
-	void __iomem *dist_base;
-	u32 percpu_offset;
-	int irq, ret;
-
 	if (WARN_ON(!node))
 		return -ENODEV;
 
-	dist_base = of_iomap(node, 0);
-	if (WARN(!dist_base, "unable to map gic dist registers\n"))
+	*dist_base = of_iomap(node, 0);
+	if (WARN(!*dist_base, "unable to map gic dist registers\n"))
 		return -ENOMEM;
 
-	cpu_base = of_iomap(node, 1);
-	if (WARN(!cpu_base, "unable to map gic cpu registers\n")) {
-		iounmap(dist_base);
+	*cpu_base = of_iomap(node, 1);
+	if (WARN(!*cpu_base, "unable to map gic cpu registers\n")) {
+		iounmap(*dist_base);
 		return -ENOMEM;
 	}
 
+	if (of_property_read_u32(node, "cpu-offset", percpu_offset))
+		*percpu_offset = 0;
+
+	return 0;
+}
+
+int __init gic_of_init(struct device_node *node, struct device_node *parent)
+{
+	void __iomem *cpu_base;
+	void __iomem *dist_base;
+	u32 percpu_offset;
+	int irq, ret;
+
+	if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
+		return -EINVAL;
+
+	ret = gic_of_setup(node, &dist_base, &cpu_base, &percpu_offset);
+	if (ret)
+		return ret;
+
 	/*
 	 * Disable split EOI/Deactivate if either HYP is not available
 	 * or the CPU interface is too small.
@@ -1255,9 +1266,6 @@ gic_of_init(struct device_node *node, struct device_node *parent)
 	if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base))
 		static_key_slow_dec(&supports_deactivate);
 
-	if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
-		percpu_offset = 0;
-
 	ret = __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset,
 			 &node->fwnode);
 	if (ret) {
@@ -1290,6 +1298,162 @@ IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
 
+static int gic_runtime_resume(struct device *dev)
+{
+	struct gic_chip_data *gic = dev_get_drvdata(dev);
+	int ret;
+
+	ret = pm_clk_resume(dev);
+	if (ret)
+		return ret;
+
+	gic_dist_restore(gic);
+	gic_cpu_restore(gic);
+
+	return 0;
+}
+
+static int gic_runtime_suspend(struct device *dev)
+{
+	struct gic_chip_data *gic = dev_get_drvdata(dev);
+
+	gic_dist_save(gic);
+	gic_cpu_save(gic);
+
+	return pm_clk_suspend(dev);
+}
+
+static int gic_get_clocks(struct device *dev)
+{
+	struct clk *clk;
+	unsigned int i, count;
+	int ret;
+
+	if (!dev || !dev->of_node)
+		return -EINVAL;
+
+	count = of_count_phandle_with_args(dev->of_node, "clocks",
+					   "#clock-cells");
+	if (count == 0)
+		return -ENODEV;
+
+	ret = pm_clk_create(dev);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < count; i++) {
+		clk = of_clk_get(dev->of_node, i);
+		if (IS_ERR(clk)) {
+			dev_err(dev, "failed to get clock at index %d\n", i);
+			ret = PTR_ERR(clk);
+			goto error;
+		}
+
+		ret = pm_clk_add_clk(dev, clk);
+		if (ret) {
+			dev_err(dev, "failed to add clock at index %d\n", i);
+			clk_put(clk);
+			goto error;
+		}
+	}
+
+	return 0;
+
+error:
+	pm_clk_destroy(dev);
+
+	return ret;
+}
+
+static int gic_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct gic_chip_data *gic;
+	void __iomem *dist_base;
+	void __iomem *cpu_base;
+	u32 percpu_offset;
+	int ret, irq;
+
+	if (dev->of_node == NULL)
+		return -EINVAL;
+
+	gic = devm_kzalloc(dev, sizeof(*gic), GFP_KERNEL);
+	if (!gic)
+		return -ENOMEM;
+
+	ret = gic_get_clocks(dev);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, gic);
+
+	pm_runtime_enable(dev);
+
+	ret = pm_runtime_get_sync(dev);
+	if (ret < 0)
+		goto rpm_disable;
+
+	irq = irq_of_parse_and_map(dev->of_node, 0);
+	if (!irq) {
+		ret = -EINVAL;
+		goto rpm_put;
+	}
+
+	ret = gic_of_setup(dev->of_node, &dist_base, &cpu_base, &percpu_offset);
+	if (ret)
+		goto irq_dispose;
+
+	ret = gic_init_bases(gic, -1, dist_base, cpu_base,
+			     percpu_offset, &dev->of_node->fwnode,
+			     dev->of_node->name);
+	if (ret)
+		goto gic_unmap;
+
+	gic->chip.parent = dev;
+
+	irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, gic);
+
+	pm_runtime_put(dev);
+
+	dev_info(dev, "GIC IRQ controller registered\n");
+
+	return 0;
+
+gic_unmap:
+	iounmap(dist_base);
+	iounmap(cpu_base);
+irq_dispose:
+	irq_dispose_mapping(irq);
+rpm_put:
+	pm_runtime_put_sync(dev);
+rpm_disable:
+	pm_runtime_disable(dev);
+	pm_clk_destroy(dev);
+
+	return ret;
+}
+
+static const struct dev_pm_ops gic_pm_ops = {
+	SET_RUNTIME_PM_OPS(gic_runtime_suspend,
+			   gic_runtime_resume, NULL)
+};
+
+static const struct of_device_id gic_match[] = {
+	{ .compatible = "nvidia,tegra210-agic", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, gic_match);
+
+static struct platform_driver gic_driver = {
+	.probe		= gic_probe,
+	.driver		= {
+		.name	= "gic",
+		.of_match_table	= gic_match,
+		.pm	= &gic_pm_ops,
+	}
+};
+
+builtin_platform_driver(gic_driver);
 #endif
 
 #ifdef CONFIG_ACPI
-- 
2.1.4

[toc] | [prev] | [standalone]

Page 3 of 3 — ← Prev page 1 2 [3]

Back to top | Article view | linux.kernel

csiph-web