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Re: [RFC PATCH 1/5] clk: sunxi: Add a driver for the PLL2 on A31/23/33

Started byMaxime Ripard <maxime.ripard@free-electrons.com>
First post2016-07-05 08:20 +0200
Last post2016-07-05 08:20 +0200
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  Re: [RFC PATCH 1/5] clk: sunxi: Add a driver for the PLL2 on  A31/23/33 Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-07-05 08:20 +0200

#1436785 — Re: [RFC PATCH 1/5] clk: sunxi: Add a driver for the PLL2 on A31/23/33

FromMaxime Ripard <maxime.ripard@free-electrons.com>
Date2016-07-05 08:20 +0200
SubjectRe: [RFC PATCH 1/5] clk: sunxi: Add a driver for the PLL2 on A31/23/33
Message-ID<rRrS9-7vt-11@gated-at.bofh.it>

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Hi,

On Tue, Jun 28, 2016 at 06:13:21PM +0800, Icenowy Zheng wrote:
> This is based on the PLL2 driver for A10/20.

Thanks for this patch.

However, as you might have seen, we're switching to a new clock code
base, so it would be great if you could use that instead.

http://lists.infradead.org/pipermail/linux-arm-kernel/2016-June/440077.html

While we declared all the clocks for the H3, nothing really mandates
that for the existing platforms we don't introduce a few clocks as
they are needed. That will probably even smoothen the transition.

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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