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Re: [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3

Started byLothar Waßmann <LW@KARO-electronics.de>
First post2016-06-09 09:50 +0200
Last post2016-06-12 14:10 +0200
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  Re: [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3 Lothar Waßmann <LW@KARO-electronics.de> - 2016-06-09 09:50 +0200
    Re: [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3 Dong Aisheng <dongas86@gmail.com> - 2016-06-12 14:10 +0200

#1418137 — Re: [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3

FromLothar Waßmann <LW@KARO-electronics.de>
Date2016-06-09 09:50 +0200
SubjectRe: [PATCH 05/11] clk: imx: refine the powerup_set bit of clk-pllv3
Message-ID<rI2SZ-3kN-7@gated-at.bofh.it>
Hi,

On Wed, 8 Jun 2016 22:33:34 +0800 Dong Aisheng wrote:
> There's a powerdown bit already, so let's change the name of
> powerup_set bit to power_invert to reflects the power polarity
> to make it less confusing.
> 
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
>  drivers/clk/imx/clk-pllv3.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index eea2b1b3791e..3fdfb6d2cc71 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -29,8 +29,8 @@
>   * struct clk_pllv3 - IMX PLL clock version 3
>   * @clk_hw:	 clock source
>   * @base:	 base address of PLL registers
> - * @powerup_set: set POWER bit to power up the PLL
> - * @powerdown:   pll powerdown offset bit
> + * @powerdown:	 pll powerdown bit offset
> + * @power_invert: set powerdown bit to power up the PLL
s/set/clear/ ?



Lothar Waßmann

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#1420255

FromDong Aisheng <dongas86@gmail.com>
Date2016-06-12 14:10 +0200
Message-ID<rJcng-8vZ-17@gated-at.bofh.it>
In reply to#1418137
On Thu, Jun 09, 2016 at 09:43:28AM +0200, Lothar Wa??mann wrote:
> Hi,
> 
> On Wed, 8 Jun 2016 22:33:34 +0800 Dong Aisheng wrote:
> > There's a powerdown bit already, so let's change the name of
> > powerup_set bit to power_invert to reflects the power polarity
> > to make it less confusing.
> > 
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> >  drivers/clk/imx/clk-pllv3.c | 14 +++++++-------
> >  1 file changed, 7 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> > index eea2b1b3791e..3fdfb6d2cc71 100644
> > --- a/drivers/clk/imx/clk-pllv3.c
> > +++ b/drivers/clk/imx/clk-pllv3.c
> > @@ -29,8 +29,8 @@
> >   * struct clk_pllv3 - IMX PLL clock version 3
> >   * @clk_hw:	 clock source
> >   * @base:	 base address of PLL registers
> > - * @powerup_set: set POWER bit to power up the PLL
> > - * @powerdown:   pll powerdown offset bit
> > + * @powerdown:	 pll powerdown bit offset
> > + * @power_invert: set powerdown bit to power up the PLL
> s/set/clear/ ?
> 

It is set.
By default set the powerdown bit will powerdown the PLL according
to spec.
However, for IMX_PLLV3_USB, it's actually power up the PLL,
so the power_invert reflect such using.

Regards
Dong Aisheng

> 
> 
> Lothar Wa??mann
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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