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Groups > linux.kernel > #1330915 > unrolled thread

[PATCH 0/6] More updates for NS2 DT

Started byAnup Patel <anup.patel@broadcom.com>
First post2016-02-10 07:20 +0100
Last post2016-02-13 01:00 +0100
Articles 5 — 2 participants

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  [PATCH 0/6] More updates for NS2 DT Anup Patel <anup.patel@broadcom.com> - 2016-02-10 07:20 +0100
    [PATCH 5/6] arm64: dts: Add ARM SP805 watchdog DT node for NS2 Anup Patel <anup.patel@broadcom.com> - 2016-02-10 07:20 +0100
    [PATCH 6/6] arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2 Anup Patel <anup.patel@broadcom.com> - 2016-02-10 07:20 +0100
    [PATCH 3/6] arm64: dts: Add ARM SP804 timer DT nodes for NS2 Anup Patel <anup.patel@broadcom.com> - 2016-02-10 07:20 +0100
    Re: [PATCH 0/6] More updates for NS2 DT Florian Fainelli <f.fainelli@gmail.com> - 2016-02-13 01:00 +0100

#1330915 — [PATCH 0/6] More updates for NS2 DT

FromAnup Patel <anup.patel@broadcom.com>
Date2016-02-10 07:20 +0100
Subject[PATCH 0/6] More updates for NS2 DT
Message-ID<r0wi5-6Uy-3@gated-at.bofh.it>
This patchset primarily adds more DT nodes for NS2 SVK. It also does
minor update to arch/arm64/Kconfig.platforms and adds missing DT
bindings document for sp805 driver.

The patchset is based on v4.5-rc3 tag and is available in ns2_dt2_v1
branch of https://github.com/Broadcom/arm64-linux.git

All patches have been tested on Broadcom NS2 SVK.

Anup Patel (5):
  arm64: Select COMMON_CLK_IPROC, PINCTRL and GPIOLIB for iProc SoCs
  arm64: dts: Add SDHCI DT node for NS2
  arm64: dts: Add ARM SP804 timer DT nodes for NS2
  dt-bindings: watchdog: Add ARM SP805 DT bindings
  arm64: dts: Add ARM SP805 watchdog DT node for NS2

Ray Jui (1):
  arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2

 .../devicetree/bindings/watchdog/arm,sp805.txt     |  17 +++
 arch/arm64/Kconfig.platforms                       |   3 +
 arch/arm64/boot/dts/broadcom/ns2-svk.dts           |  12 ++
 arch/arm64/boot/dts/broadcom/ns2.dtsi              | 140 +++++++++++++++++++++
 4 files changed, 172 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/watchdog/arm,sp805.txt

-- 
1.9.1

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#1330916 — [PATCH 5/6] arm64: dts: Add ARM SP805 watchdog DT node for NS2

FromAnup Patel <anup.patel@broadcom.com>
Date2016-02-10 07:20 +0100
Subject[PATCH 5/6] arm64: dts: Add ARM SP805 watchdog DT node for NS2
Message-ID<r0wi6-6Uy-21@gated-at.bofh.it>
In reply to#1330915
We have one ARM SP805 watchdog instance on NS2 for non-secure software
hence this patch adds appropriate watchdog DT node in NS2 DT.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Pramod KUMAR <pramodku@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 83e1c27..062616b4 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -306,6 +306,14 @@
 			status = "disabled";
 		};
 
+		wdt0: watchdog@66090000 {
+			compatible = "arm,sp805", "arm,primecell";
+			reg = <0x66090000 0x1000>;
+			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>, <&iprocslow>;
+			clock-names = "wdogclk", "apb_pclk";
+		};
+
 		i2c1: i2c@660b0000 {
 			compatible = "brcm,iproc-i2c";
 			reg = <0x660b0000 0x100>;
-- 
1.9.1

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#1330918 — [PATCH 6/6] arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2

FromAnup Patel <anup.patel@broadcom.com>
Date2016-02-10 07:20 +0100
Subject[PATCH 6/6] arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2
Message-ID<r0wi6-6Uy-23@gated-at.bofh.it>
In reply to#1330915
From: Ray Jui <rjui@broadcom.com>

This patch enables PCIe0 and PCIe4 for NS2 by adding
appropriate DT nodes in NS2 DT.

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm64/boot/dts/broadcom/ns2-svk.dts |  8 ++++
 arch/arm64/boot/dts/broadcom/ns2.dtsi    | 74 ++++++++++++++++++++++++++++++++
 2 files changed, 82 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index 3321bd1..ce0ab84 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -52,6 +52,14 @@
 	};
 };
 
+&pcie0 {
+	status = "ok";
+};
+
+&pcie4 {
+	status = "ok";
+};
+
 &i2c0 {
 	status = "ok";
 };
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index 062616b4..6f81c9d 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -137,6 +137,80 @@
 		};
 	};
 
+	pcie0: pcie@20020000 {
+		compatible = "brcm,iproc-pcie";
+		reg = <0 0x20020000 0 0x1000>;
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
+
+		linux,pci-domain = <0>;
+
+		bus-range = <0x00 0xff>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
+
+		brcm,pcie-ob;
+		brcm,pcie-ob-oarr-size;
+		brcm,pcie-ob-axi-offset = <0x00000000>;
+		brcm,pcie-ob-window-size = <256>;
+
+		status = "disabled";
+
+		msi-parent = <&msi0>;
+		msi0: msi@20020000 {
+			compatible = "brcm,iproc-msi";
+			msi-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
+				     <GIC_SPI 278 IRQ_TYPE_NONE>,
+				     <GIC_SPI 279 IRQ_TYPE_NONE>,
+				     <GIC_SPI 280 IRQ_TYPE_NONE>;
+			brcm,num-eq-region = <1>;
+			brcm,num-msi-msg-region = <1>;
+		};
+	};
+
+	pcie4: pcie@50020000 {
+		compatible = "brcm,iproc-pcie";
+		reg = <0 0x50020000 0 0x1000>;
+
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0>;
+		interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
+
+		linux,pci-domain = <4>;
+
+		bus-range = <0x00 0xff>;
+
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
+
+		brcm,pcie-ob;
+		brcm,pcie-ob-oarr-size;
+		brcm,pcie-ob-axi-offset = <0x30000000>;
+		brcm,pcie-ob-window-size = <256>;
+
+		status = "disabled";
+
+		msi-parent = <&msi4>;
+		msi4: msi@50020000 {
+			compatible = "brcm,iproc-msi";
+			msi-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
+				     <GIC_SPI 302 IRQ_TYPE_NONE>,
+				     <GIC_SPI 303 IRQ_TYPE_NONE>,
+				     <GIC_SPI 304 IRQ_TYPE_NONE>;
+		};
+	};
+
 	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
-- 
1.9.1

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#1330919 — [PATCH 3/6] arm64: dts: Add ARM SP804 timer DT nodes for NS2

FromAnup Patel <anup.patel@broadcom.com>
Date2016-02-10 07:20 +0100
Subject[PATCH 3/6] arm64: dts: Add ARM SP804 timer DT nodes for NS2
Message-ID<r0wi6-6Uy-25@gated-at.bofh.it>
In reply to#1330915
We have four ARM SP804 dual-mode timer instances in NS2 SoC
hence this patch adds appropriate DT nodes for NS2.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Pramod KUMAR <pramodku@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm64/boot/dts/broadcom/ns2.dtsi | 40 +++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index b1f352d..83e1c27 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -256,6 +256,46 @@
 			      <0x65260000 0x1000>;
 		};
 
+		timer0: timer@66030000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x66030000 0x1000>;
+			interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>,
+				 <&iprocslow>,
+				 <&iprocslow>;
+			clock-names = "timer1", "timer2", "apb_pclk";
+		};
+
+		timer1: timer@66040000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x66040000 0x1000>;
+			interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>,
+				 <&iprocslow>,
+				 <&iprocslow>;
+			clock-names = "timer1", "timer2", "apb_pclk";
+		};
+
+		timer2: timer@66050000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x66050000 0x1000>;
+			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>,
+				 <&iprocslow>,
+				 <&iprocslow>;
+			clock-names = "timer1", "timer2", "apb_pclk";
+		};
+
+		timer3: timer@66060000 {
+			compatible = "arm,sp804", "arm,primecell";
+			reg = <0x66060000 0x1000>;
+			interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&iprocslow>,
+				 <&iprocslow>,
+				 <&iprocslow>;
+			clock-names = "timer1", "timer2", "apb_pclk";
+		};
+
 		i2c0: i2c@66080000 {
 			compatible = "brcm,iproc-i2c";
 			reg = <0x66080000 0x100>;
-- 
1.9.1

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#1333216

FromFlorian Fainelli <f.fainelli@gmail.com>
Date2016-02-13 01:00 +0100
Message-ID<r1vN1-5rS-13@gated-at.bofh.it>
In reply to#1330915
On 09/02/16 22:10, Anup Patel wrote:
> This patchset primarily adds more DT nodes for NS2 SVK. It also does
> minor update to arch/arm64/Kconfig.platforms and adds missing DT
> bindings document for sp805 driver.
> 
> The patchset is based on v4.5-rc3 tag and is available in ns2_dt2_v1
> branch of https://github.com/Broadcom/arm64-linux.git
> 
> All patches have been tested on Broadcom NS2 SVK.
> 
> Anup Patel (5):
>   arm64: Select COMMON_CLK_IPROC, PINCTRL and GPIOLIB for iProc SoCs
>   arm64: dts: Add SDHCI DT node for NS2
>   arm64: dts: Add ARM SP804 timer DT nodes for NS2
>   dt-bindings: watchdog: Add ARM SP805 DT bindings
>   arm64: dts: Add ARM SP805 watchdog DT node for NS2
> 
> Ray Jui (1):
>   arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2

Patch 1 applied to soc-arm64/next

Patch 2-6 applied to devicetree-arm64/next, with Rob's Acked-by and the
suggested rename from wdt@ to watchdog@ that he recommended, thanks
everyone!
-- 
Florian

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