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Re: [PATCH v10 4/4] x86: Create a new synthetic cpu capability for machine check recovery

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  Re: [PATCH v10 4/4] x86: Create a new synthetic cpu capability for  machine check recovery "Luck, Tony" <tony.luck@intel.com> - 2016-02-10 00:40 +0100
    Re: [PATCH v10 4/4] x86: Create a new synthetic cpu capability for  machine check recovery Borislav Petkov <bp@alien8.de> - 2016-02-10 12:10 +0100
      Re: [PATCH v10 4/4] x86: Create a new synthetic cpu capability for  machine check recovery "Luck, Tony" <tony.luck@intel.com> - 2016-02-10 20:30 +0100
        Re: [PATCH v10 4/4] x86: Create a new synthetic cpu capability for  machine check recovery Borislav Petkov <bp@alien8.de> - 2016-02-11 13:00 +0100

#1330773 — Re: [PATCH v10 4/4] x86: Create a new synthetic cpu capability for machine check recovery

> > +	if (mca_cfg.recovery || (mca_cfg.ser &&
> > +		!strncmp(c->x86_model_id, "Intel(R) Xeon(R) CPU E7-", 24)))
> 
> Eeww, a model string check :-(
> 
> Lemme guess: those E7s can't be represented by a range of
> model/steppings, can they?

We use the same model number for E5 and E7 series. E.g. 63 for Haswell.
The model_id string seems to be the only way to tell ahead of time
whether you will get a recoverable machine check or die when you
touch uncorrected memory.

-Tony

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#1331071

On Tue, Feb 09, 2016 at 03:38:57PM -0800, Luck, Tony wrote:
> We use the same model number for E5 and E7 series. E.g. 63 for Haswell.
> The model_id string seems to be the only way to tell ahead of time
> whether you will get a recoverable machine check or die when you
> touch uncorrected memory.

What about MSR_IA32_PLATFORM_ID or some other MSR or register, for
example?

I.e., isn't there some other, more reliable distinction between E5 and
E7 besides the model ID?

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.

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#1331451

On Wed, Feb 10, 2016 at 12:06:03PM +0100, Borislav Petkov wrote:
> What about MSR_IA32_PLATFORM_ID or some other MSR or register, for
> example?

Bits 52:50 give us "information concerning the intended platform
for the processor" ... but we don't seem to decode that vague
statement into anything that I can make use of.

> I.e., isn't there some other, more reliable distinction between E5 and
> E7 besides the model ID?

Digging in the data sheet I found the CAPID0 register which does
indicate in bit 4 whether this is an "EX" (a.k.a. "E7" part). But
we invent a new PCI device ID for this every generation (0x0EC3 in
Ivy Bridge, 0x2fc0 in Haswell, 0x6fc0 in Broadwell). The offset
has stayed at 0x84 through all this.

I don't think that hunting the ever-changing PCI-id is a
good choice ... the "E5/E7" naming convention has stuck for
four generations[1] (Sandy Bridge, Ivy Bridge, Haswell, Broadwell).

-Tony

[1] Although this probably means that marketing are about to
think of something new ... they generally do when people start
understanding the model names :-(

-Tony

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#1331854

On Wed, Feb 10, 2016 at 11:27:50AM -0800, Luck, Tony wrote:
> Digging in the data sheet I found the CAPID0 register which does
> indicate in bit 4 whether this is an "EX" (a.k.a. "E7" part). But
> we invent a new PCI device ID for this every generation (0x0EC3 in
> Ivy Bridge, 0x2fc0 in Haswell, 0x6fc0 in Broadwell). The offset
> has stayed at 0x84 through all this.
> 
> I don't think that hunting the ever-changing PCI-id is a
> good choice ...

Right :-\

> the "E5/E7" naming convention has stuck for
> four generations[1] (Sandy Bridge, Ivy Bridge, Haswell, Broadwell).
> 
> -Tony
> 
> [1] Although this probably means that marketing are about to
> think of something new ... they generally do when people start
> understanding the model names :-(

Yeah, customers shouldn't slack and relax into even thinking they know
the model names. Fortunately there's wikipedia...

Thanks.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.

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