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Groups > linux.kernel > #1273836 > unrolled thread
| Started by | Andy Gross <agross@codeaurora.org> |
|---|---|
| First post | 2015-11-20 09:40 +0100 |
| Last post | 2015-11-20 09:40 +0100 |
| Articles | 9 — 3 participants |
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[PATCH 0/4] Add QCOM DWC3 Phy support Andy Gross <agross@codeaurora.org> - 2015-11-20 09:40 +0100
[PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register Andy Gross <agross@codeaurora.org> - 2015-11-20 09:40 +0100
Re: [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register Felipe Balbi <balbi@ti.com> - 2015-11-20 16:10 +0100
Re: [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register Andy Gross <agross@codeaurora.org> - 2015-11-20 17:00 +0100
[PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage Andy Gross <agross@codeaurora.org> - 2015-11-20 09:40 +0100
Re: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage Rob Herring <robh@kernel.org> - 2015-11-20 15:40 +0100
Re: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage Felipe Balbi <balbi@ti.com> - 2015-11-20 16:10 +0100
Re: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage Andy Gross <agross@codeaurora.org> - 2015-11-20 17:00 +0100
[PATCH 3/4] ARM: dts: qcom: Add DWC3 USB support on IPQ8064 Andy Gross <agross@codeaurora.org> - 2015-11-20 09:40 +0100
| From | Andy Gross <agross@codeaurora.org> |
|---|---|
| Date | 2015-11-20 09:40 +0100 |
| Subject | [PATCH 0/4] Add QCOM DWC3 Phy support |
| Message-ID | <qwPoC-4LV-19@gated-at.bofh.it> |
This set of patches adds support for the QCOM DWC3 phys found on various Qualcomm platforms. The PHY portion of this set was originally part of: https://lkml.org/lkml/2014/9/12/597 The applicable review comments were fixed and additional changes were made to accomodate the TCSR phy mux selection required to get working ports. Andy Gross (4): phy: Add Qualcomm DWC3 HS/SS PHY driver usb: dwc3: qcom: Configure TCSR phy mux register ARM: dts: qcom: Add DWC3 USB support on IPQ8064 Documentation: usb: dwc3: qcom: Add TCSR mux usage .../devicetree/bindings/usb/qcom,dwc3.txt | 11 + arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 24 + arch/arm/boot/dts/qcom-ipq8064.dtsi | 89 ++++ drivers/phy/Kconfig | 11 + drivers/phy/Makefile | 1 + drivers/phy/phy-qcom-dwc3.c | 483 +++++++++++++++++++++ drivers/usb/dwc3/dwc3-qcom.c | 25 ++ 7 files changed, 644 insertions(+) create mode 100644 drivers/phy/phy-qcom-dwc3.c -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Andy Gross <agross@codeaurora.org> |
|---|---|
| Date | 2015-11-20 09:40 +0100 |
| Subject | [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register |
| Message-ID | <qwPoD-4LV-43@gated-at.bofh.it> |
| In reply to | #1273836 |
This patch adds automatic configuration of the TCSR phy mux register based on
the syscon-tcsr devicetree entry. This configuration is optional, as some
platforms may not require the mux selection.
Signed-off-by: Andy Gross <agross@codeaurora.org>
---
drivers/usb/dwc3/dwc3-qcom.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 0880260..fcf264c 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -17,6 +17,8 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
struct dwc3_qcom {
struct device *dev;
@@ -30,6 +32,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct dwc3_qcom *qdwc;
+ struct regmap *regmap;
+ u32 mux_offset;
+ u32 mux_bit;
int ret;
qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
@@ -58,6 +63,26 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
qdwc->sleep_clk = NULL;
}
+ /* look for tcsr and if present, provision it */
+ regmap = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
+ if (!IS_ERR(regmap)) {
+ if (of_property_read_u32_index(node, "syscon-tcsr", 1,
+ &mux_offset)) {
+ dev_err(qdwc->dev, "missing USB TCSR mux offset\n");
+ return -EINVAL;
+ }
+ if (of_property_read_u32_index(node, "syscon-tcsr", 2,
+ &mux_bit)) {
+ dev_err(qdwc->dev, "missing USB TCSR mux bit\n");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(regmap, mux_offset, BIT(mux_bit),
+ BIT(mux_bit));
+ } else {
+ dev_info(qdwc->dev, "missing syscon tcsr entry\n");
+ }
+
ret = clk_prepare_enable(qdwc->core_clk);
if (ret) {
dev_err(qdwc->dev, "failed to enable core clock\n");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
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| From | Felipe Balbi <balbi@ti.com> |
|---|---|
| Date | 2015-11-20 16:10 +0100 |
| Subject | Re: [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register |
| Message-ID | <qwVu1-q6-11@gated-at.bofh.it> |
| In reply to | #1273838 |
[Multipart message — attachments visible in raw view] — view raw
Hi,
Andy Gross <agross@codeaurora.org> writes:
> This patch adds automatic configuration of the TCSR phy mux register based on
> the syscon-tcsr devicetree entry. This configuration is optional, as some
> platforms may not require the mux selection.
>
> Signed-off-by: Andy Gross <agross@codeaurora.org>
just when I find a way to make a generic dwc3-of-simple.c glue layer :-p
I can, certainly drop my patches but I need more details on the syscon
usage below.
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index 0880260..fcf264c 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -17,6 +17,8 @@
> #include <linux/of.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
>
> struct dwc3_qcom {
> struct device *dev;
> @@ -30,6 +32,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> {
> struct device_node *node = pdev->dev.of_node;
> struct dwc3_qcom *qdwc;
> + struct regmap *regmap;
> + u32 mux_offset;
> + u32 mux_bit;
> int ret;
>
> qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
> @@ -58,6 +63,26 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> qdwc->sleep_clk = NULL;
> }
>
> + /* look for tcsr and if present, provision it */
> + regmap = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
> + if (!IS_ERR(regmap)) {
> + if (of_property_read_u32_index(node, "syscon-tcsr", 1,
> + &mux_offset)) {
> + dev_err(qdwc->dev, "missing USB TCSR mux offset\n");
> + return -EINVAL;
> + }
> + if (of_property_read_u32_index(node, "syscon-tcsr", 2,
> + &mux_bit)) {
> + dev_err(qdwc->dev, "missing USB TCSR mux bit\n");
> + return -EINVAL;
> + }
> +
> + regmap_update_bits(regmap, mux_offset, BIT(mux_bit),
> + BIT(mux_bit));
what is tcsr and what does it ? It also seems to be optional, why's that ?
--
balbi
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| From | Andy Gross <agross@codeaurora.org> |
|---|---|
| Date | 2015-11-20 17:00 +0100 |
| Subject | Re: [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register |
| Message-ID | <qwWgq-IS-13@gated-at.bofh.it> |
| In reply to | #1274153 |
On Fri, Nov 20, 2015 at 09:06:33AM -0600, Felipe Balbi wrote:
>
> Hi,
>
> Andy Gross <agross@codeaurora.org> writes:
> > This patch adds automatic configuration of the TCSR phy mux register based on
> > the syscon-tcsr devicetree entry. This configuration is optional, as some
> > platforms may not require the mux selection.
> >
> > Signed-off-by: Andy Gross <agross@codeaurora.org>
>
> just when I find a way to make a generic dwc3-of-simple.c glue layer :-p
>
> I can, certainly drop my patches but I need more details on the syscon
> usage below.
>
> > ---
> > drivers/usb/dwc3/dwc3-qcom.c | 25 +++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> > index 0880260..fcf264c 100644
> > --- a/drivers/usb/dwc3/dwc3-qcom.c
> > +++ b/drivers/usb/dwc3/dwc3-qcom.c
> > @@ -17,6 +17,8 @@
> > #include <linux/of.h>
> > #include <linux/of_platform.h>
> > #include <linux/platform_device.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/regmap.h>
> >
> > struct dwc3_qcom {
> > struct device *dev;
> > @@ -30,6 +32,9 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> > {
> > struct device_node *node = pdev->dev.of_node;
> > struct dwc3_qcom *qdwc;
> > + struct regmap *regmap;
> > + u32 mux_offset;
> > + u32 mux_bit;
> > int ret;
> >
> > qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
> > @@ -58,6 +63,26 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> > qdwc->sleep_clk = NULL;
> > }
> >
> > + /* look for tcsr and if present, provision it */
> > + regmap = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
> > + if (!IS_ERR(regmap)) {
> > + if (of_property_read_u32_index(node, "syscon-tcsr", 1,
> > + &mux_offset)) {
> > + dev_err(qdwc->dev, "missing USB TCSR mux offset\n");
> > + return -EINVAL;
> > + }
> > + if (of_property_read_u32_index(node, "syscon-tcsr", 2,
> > + &mux_bit)) {
> > + dev_err(qdwc->dev, "missing USB TCSR mux bit\n");
> > + return -EINVAL;
> > + }
> > +
> > + regmap_update_bits(regmap, mux_offset, BIT(mux_bit),
> > + BIT(mux_bit));
>
> what is tcsr and what does it ? It also seems to be optional, why's that ?
>
> --
> balbi
The syscon is to set the mux selection for the phys. Our hardware has a
steering mux between hsic and dwc3 and setting this to 1 steers the phys to the
right controller.
It is optional because not all platforms appear to have this stupidity.
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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| From | Andy Gross <agross@codeaurora.org> |
|---|---|
| Date | 2015-11-20 09:40 +0100 |
| Subject | [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage |
| Message-ID | <qwPoD-4LV-49@gated-at.bofh.it> |
| In reply to | #1273836 |
This patch adds documentation for the optional syscon-tcsr property in the
Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to
configure the TCSR USB phy mux register.
Signed-off-by: Andy Gross <agross@codeaurora.org>
---
Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
index ca164e7..dfa222d 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
@@ -8,6 +8,10 @@ Required properties:
"core" Master/Core clock, have to be >= 125 MHz for SS
operation and >= 60MHz for HS operation
+Optional properties:
+- syscon-tcsr Specifies TCSR handle, register offset, and bit position for
+ configuring the phy mux setting.
+
Optional clocks:
"iface" System bus AXI clock. Not present on all platforms
"sleep" Sleep clock, used when USB3 core goes into low
@@ -22,6 +26,11 @@ Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
Example device nodes:
+ tcsr: syscon@1a400000 {
+ compatible = "qcom,tcsr-ipq8064", "syscon";
+ reg = <0x1a400000 0x100>;
+ };
+
hs_phy: phy@100f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x100f8800 0x30>;
@@ -51,6 +60,8 @@ Example device nodes:
ranges;
+ syscon-tcsr = <&tcsr 0xb0 0x1>;
+
status = "ok";
dwc3@10000000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2015-11-20 15:40 +0100 |
| Subject | Re: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage |
| Message-ID | <qwV10-8qz-15@gated-at.bofh.it> |
| In reply to | #1273841 |
On Fri, Nov 20, 2015 at 02:35:09AM -0600, Andy Gross wrote:
> This patch adds documentation for the optional syscon-tcsr property in the
> Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to
> configure the TCSR USB phy mux register.
>
> Signed-off-by: Andy Gross <agross@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> index ca164e7..dfa222d 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> @@ -8,6 +8,10 @@ Required properties:
> "core" Master/Core clock, have to be >= 125 MHz for SS
> operation and >= 60MHz for HS operation
>
> +Optional properties:
> +- syscon-tcsr Specifies TCSR handle, register offset, and bit position for
> + configuring the phy mux setting.
> +
> Optional clocks:
> "iface" System bus AXI clock. Not present on all platforms
> "sleep" Sleep clock, used when USB3 core goes into low
> @@ -22,6 +26,11 @@ Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
>
> Example device nodes:
>
> + tcsr: syscon@1a400000 {
> + compatible = "qcom,tcsr-ipq8064", "syscon";
> + reg = <0x1a400000 0x100>;
> + };
> +
> hs_phy: phy@100f8800 {
> compatible = "qcom,dwc3-hs-usb-phy";
> reg = <0x100f8800 0x30>;
> @@ -51,6 +60,8 @@ Example device nodes:
>
> ranges;
>
> + syscon-tcsr = <&tcsr 0xb0 0x1>;
> +
> status = "ok";
>
> dwc3@10000000 {
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
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| From | Felipe Balbi <balbi@ti.com> |
|---|---|
| Date | 2015-11-20 16:10 +0100 |
| Subject | Re: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage |
| Message-ID | <qwVu1-q6-1@gated-at.bofh.it> |
| In reply to | #1273841 |
[Multipart message — attachments visible in raw view] — view raw
Hi, Andy Gross <agross@codeaurora.org> writes: > This patch adds documentation for the optional syscon-tcsr property in the > Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to > configure the TCSR USB phy mux register. > > Signed-off-by: Andy Gross <agross@codeaurora.org> > --- > Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt > index ca164e7..dfa222d 100644 > --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt > @@ -8,6 +8,10 @@ Required properties: > "core" Master/Core clock, have to be >= 125 MHz for SS > operation and >= 60MHz for HS operation > > +Optional properties: > +- syscon-tcsr Specifies TCSR handle, register offset, and bit position for > + configuring the phy mux setting. oh, it's a PHY mux ? I don't think it should be part of any dwc3-* glue layer then. By the time we reach dwc3, the mux should be properly configured. Kishon, any ideas ? -- balbi
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| From | Andy Gross <agross@codeaurora.org> |
|---|---|
| Date | 2015-11-20 17:00 +0100 |
| Subject | Re: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage |
| Message-ID | <qwWgp-IS-5@gated-at.bofh.it> |
| In reply to | #1274149 |
On Fri, Nov 20, 2015 at 09:08:46AM -0600, Felipe Balbi wrote: > > Hi, > > Andy Gross <agross@codeaurora.org> writes: > > This patch adds documentation for the optional syscon-tcsr property in the > > Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to > > configure the TCSR USB phy mux register. > > > > Signed-off-by: Andy Gross <agross@codeaurora.org> > > --- > > Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt > > index ca164e7..dfa222d 100644 > > --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt > > +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt > > @@ -8,6 +8,10 @@ Required properties: > > "core" Master/Core clock, have to be >= 125 MHz for SS > > operation and >= 60MHz for HS operation > > > > +Optional properties: > > +- syscon-tcsr Specifies TCSR handle, register offset, and bit position for > > + configuring the phy mux setting. > > oh, it's a PHY mux ? I don't think it should be part of any dwc3-* glue > layer then. By the time we reach dwc3, the mux should be properly > configured. > > Kishon, any ideas ? > > -- > balbi The only issue with putting it at the phy layer is that i'd have redundant syscon entries for each pair of phys, unless i group them somehow in dt. The only other issue I can think of is that in the downstream kernels, they do this before messing with the configuration of the dwc3. So long as the phys do their thing before the dwc3 (phys latched before config), we're ok. -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Andy Gross <agross@codeaurora.org> |
|---|---|
| Date | 2015-11-20 09:40 +0100 |
| Subject | [PATCH 3/4] ARM: dts: qcom: Add DWC3 USB support on IPQ8064 |
| Message-ID | <qwPoD-4LV-51@gated-at.bofh.it> |
| In reply to | #1273836 |
This patch adds Qualcomm DWC3 USB nodes to device tree to enable support for the
DWC3 controller found on IPQ8064/AP148 platforms.
Signed-off-by: Andy Gross <agross@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 24 +++++++++
arch/arm/boot/dts/qcom-ipq8064.dtsi | 89 ++++++++++++++++++++++++++++++++
2 files changed, 113 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index d501382..bf1638c 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -97,5 +97,29 @@
sata@29000000 {
status = "ok";
};
+
+ phy@100f8800 {
+ status = "ok";
+ };
+
+ phy@100f8830 {
+ status = "ok";
+ };
+
+ usb30@0 {
+ status = "ok";
+ };
+
+ phy@110f8800 {
+ status = "ok";
+ };
+
+ phy@110f8830 {
+ status = "ok";
+ };
+
+ usb30@1 {
+ status = "ok";
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index fa69863..b2dcd9d 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -329,5 +329,94 @@
#reset-cells = <1>;
};
+ hs_phy_0: phy@100f8800 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ ss_phy_0: phy@100f8830 {
+ compatible = "qcom,dwc3-ss-usb-phy";
+ reg = <0x100f8830 0x30>;
+
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb30@0 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
+ syscon-tcsr = <&tcsr 0xb0 1>;
+
+ ranges;
+
+ status = "disabled";
+
+ dwc3@10000000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000000 0xcd00>;
+ interrupts = <0 205 0x4>;
+ phys = <&hs_phy_0>, <&ss_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ dr_mode = "host";
+ };
+ };
+
+ hs_phy_1: phy@110f8800 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ reg = <0x110f8800 0x30>;
+ clocks = <&gcc USB30_1_UTMI_CLK>;
+ clock-names = "ref";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ ss_phy_1: phy@110f8830 {
+ compatible = "qcom,dwc3-ss-usb-phy";
+ reg = <0x110f8830 0x30>;
+
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "ref";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb30@1 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "core";
+
+ syscon-tcsr = <&tcsr 0xb0 0>;
+
+ ranges;
+
+ status = "disabled";
+
+ dwc3@11000000 {
+ compatible = "snps,dwc3";
+ reg = <0x11000000 0xcd00>;
+ interrupts = <0 110 0x4>;
+ phys = <&hs_phy_1>, <&ss_phy_1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ dr_mode = "host";
+ };
+ };
};
};
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