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Groups > linux.kernel > #1259525 > unrolled thread
| Started by | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| First post | 2015-10-30 15:30 +0100 |
| Last post | 2015-11-11 23:20 +0100 |
| Articles | 20 on this page of 51 — 8 participants |
Back to article view | Back to linux.kernel
[PATCH 00/19] drm: Add Allwinner A10 display engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
[PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Chen-Yu Tsai <wens@csie.org> - 2015-10-30 16:30 +0100
Re: [PATCH 19/19] ARM: sun5i: chip: Enable the TV Encoder Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-06 20:40 +0100
[PATCH 03/19] clk: sunxi: Add TCON channel0 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 03/19] clk: sunxi: Add TCON channel0 clock Chen-Yu Tsai <wens@csie.org> - 2015-10-31 11:30 +0100
Re: [PATCH 03/19] clk: sunxi: Add TCON channel0 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-06 23:20 +0100
[PATCH 02/19] clk: sunxi: Add PLL3 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 02/19] clk: sunxi: Add PLL3 clock Stephen Boyd <sboyd@codeaurora.org> - 2015-10-30 22:40 +0100
[PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Chen-Yu Tsai <wens@csie.org> - 2015-10-30 17:10 +0100
Re: [PATCH 06/19] clk: sunxi: Add Allwinner R8 AHB gates support Hans de Goede <hdegoede@redhat.com> - 2015-10-30 17:40 +0100
[PATCH 09/19] drm: sun4i: Add DT bindings documentation Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation Rob Herring <robh@kernel.org> - 2015-10-30 17:50 +0100
Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation Thierry Reding <thierry.reding@gmail.com> - 2015-10-30 18:40 +0100
Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation Rob Herring <robh@kernel.org> - 2015-11-01 15:40 +0100
Re: [PATCH 09/19] drm: sun4i: Add DT bindings documentation Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-06 23:40 +0100
[PATCH 18/19] ARM: sun5i: r8: Add AHB gates to the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
[PATCH 12/19] drm: sun4i: tv: Add PAL output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
[PATCH 10/19] drm: sun4i: Add RGB output Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
[PATCH 15/19] ARM: sun5i: dt: Add display and TCON clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
[PATCH 16/19] ARM: sun5i: dt: Add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
[PATCH 11/19] drm: sun4i: Add composite output Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [linux-sunxi] [PATCH 11/19] drm: sun4i: Add composite output Jonathan Liu <net147@gmail.com> - 2015-11-02 04:00 +0100
Re: [linux-sunxi] [PATCH 11/19] drm: sun4i: Add composite output Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 01:40 +0100
[PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Thierry Reding <thierry.reding@gmail.com> - 2015-10-30 18:40 +0100
Re: [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 01:50 +0100
[PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 01/19] clk: sunxi: Add display clock Stephen Boyd <sboyd@codeaurora.org> - 2015-10-30 22:30 +0100
Re: [PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 00:40 +0100
Re: [PATCH 01/19] clk: sunxi: Add display clock Stephen Boyd <sboyd@codeaurora.org> - 2015-11-12 21:40 +0100
Re: [PATCH 01/19] clk: sunxi: Add display clock Chen-Yu Tsai <wens@csie.org> - 2015-10-31 11:30 +0100
Re: [PATCH 01/19] clk: sunxi: Add display clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-06 20:50 +0100
[PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks Chen-Yu Tsai <wens@csie.org> - 2015-11-09 05:30 +0100
[PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Stephen Boyd <sboyd@codeaurora.org> - 2015-10-30 22:40 +0100
Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 01:20 +0100
Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Chen-Yu Tsai <wens@csie.org> - 2015-10-31 11:00 +0100
Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-07 01:10 +0100
Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock Chen-Yu Tsai <wens@csie.org> - 2015-11-09 04:40 +0100
[PATCH 05/19] clk: sunxi: add DRAM gates Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 05/19] clk: sunxi: add DRAM gates Chen-Yu Tsai <wens@csie.org> - 2015-11-09 05:20 +0100
Re: [PATCH 05/19] clk: sunxi: add DRAM gates Chen-Yu Tsai <wens@csie.org> - 2015-11-13 09:10 +0100
[PATCH 13/19] drm: sun4i: tv: Add NTSC output standard Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
[PATCH 17/19] ARM: sun5i: dt: Add display blocks to the DTSI Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-10-30 15:30 +0100
Re: [PATCH 00/19] drm: Add Allwinner A10 display engine support Daniel Vetter <daniel@ffwll.ch> - 2015-10-30 16:10 +0100
Re: [PATCH 00/19] drm: Add Allwinner A10 display engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-12 06:20 +0100
Re: [PATCH 00/19] drm: Add Allwinner A10 display engine support Chen-Yu Tsai <wens@csie.org> - 2015-11-09 04:50 +0100
Re: [PATCH 08/19] drm: Add Allwinner A10 Display Engine support Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-11-11 23:20 +0100
Page 2 of 3 — ← Prev page 1 [2] 3 Next page →
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-10-30 15:30 +0100 |
| Subject | [PATCH 15/19] ARM: sun5i: dt: Add display and TCON clocks |
| Message-ID | <qpiQP-6Tg-43@gated-at.bofh.it> |
| In reply to | #1259525 |
Enable the display and TCON (channel 0 and channel 1) clocks that are going
to be needed to drive the display engine, tcon and TV encoders.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 8 +++---
arch/arm/boot/dts/sun5i-a13.dtsi | 3 ++-
arch/arm/boot/dts/sun5i-r8.dtsi | 5 ++--
arch/arm/boot/dts/sun5i.dtsi | 53 +++++++++++++++++++++++++++++++++++++++
4 files changed, 63 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index bddd0de88af6..0981a9e2db3b 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -65,8 +65,9 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
- clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
- <&ahb_gates 44>;
+ clocks = <&ahb_gates 36>, <&ahb_gates 43>,
+ <&ahb_gates 44>, <&de_be_clk>,
+ <&tcon_ch1_clk>;
status = "disabled";
};
@@ -74,7 +75,8 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
- clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+ clocks = <&ahb_gates 36>, <&ahb_gates 44>,
+ <&de_be_clk>, <&tcon_ch0_clk>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index d910d3a6c41c..130644d7e054 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -61,7 +61,8 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
- clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
+ clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
+ <&tcon_ch0_clk>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index 0ef865601ac9..b1e4e0170d51 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -51,8 +51,9 @@
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
- clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
- <&ahb_gates 44>;
+ clocks = <&ahb_gates 34>, <&ahb_gates 36>,
+ <&ahb_gates 44>, <&de_be_clk>,
+ <&tcon_ch1_clk>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index bde9a545b79f..861c5a621e70 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -129,6 +129,15 @@
clock-output-names = "pll3";
};
+ pll3x2: pll3x2_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <2>;
+ clocks = <&pll3>;
+ clock-output-names = "pll3x2";
+ };
+
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -161,6 +170,15 @@
clock-output-names = "pll7";
};
+ pll7x2: pll7x2_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <2>;
+ clocks = <&pll7>;
+ clock-output-names = "pll7x2";
+ };
+
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
@@ -320,6 +338,41 @@
clock-output-names = "usb_ohci0", "usb_phy";
};
+ de_be_clk: clk@01c20104 {
+ #clock-cells = <0>;
+ #reset-cells = <0>;
+ compatible = "allwinner,sun4i-a10-display-clk";
+ reg = <0x01c20104 0x4>;
+ clocks = <&pll3>, <&pll7>, <&pll5 1>;
+ clock-output-names = "de-be";
+ };
+
+ de_fe_clk: clk@01c2010c {
+ #clock-cells = <0>;
+ #reset-cells = <0>;
+ compatible = "allwinner,sun4i-a10-display-clk";
+ reg = <0x01c2010c 0x4>;
+ clocks = <&pll3>, <&pll7>, <&pll5 1>;
+ clock-output-names = "de-fe";
+ };
+
+ tcon_ch0_clk: clk@01c20118 {
+ #clock-cells = <0>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+ reg = <0x01c20118 0x4>;
+ clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+ clock-output-names = "tcon-ch0-sclk";
+ };
+
+ tcon_ch1_clk: clk@01c2012c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+ reg = <0x01c2012c 0x4>;
+ clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+ clock-output-names = "tcon-ch1-sclk";
+ };
+
codec_clk: clk@01c20140 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-codec-clk";
--
2.6.2
--
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-10-30 15:30 +0100 |
| Subject | [PATCH 16/19] ARM: sun5i: dt: Add DRAM gates |
| Message-ID | <qpiQP-6Tg-39@gated-at.bofh.it> |
| In reply to | #1259525 |
The DRAM gates control whether the image / display devices on the SoC have
access to the DRAM clock or not.
Enable it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 5 +++--
arch/arm/boot/dts/sun5i-a13.dtsi | 2 +-
arch/arm/boot/dts/sun5i-r8.dtsi | 2 +-
arch/arm/boot/dts/sun5i.dtsi | 19 +++++++++++++++++++
4 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 0981a9e2db3b..c996b5d1851a 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -67,7 +67,7 @@
allwinner,pipeline = "de_be0-lcd0-hdmi";
clocks = <&ahb_gates 36>, <&ahb_gates 43>,
<&ahb_gates 44>, <&de_be_clk>,
- <&tcon_ch1_clk>;
+ <&tcon_ch1_clk>, <&dram_gates 26>;
status = "disabled";
};
@@ -76,7 +76,8 @@
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clocks = <&ahb_gates 36>, <&ahb_gates 44>,
- <&de_be_clk>, <&tcon_ch0_clk>;
+ <&de_be_clk>, <&tcon_ch0_clk>,
+ <&dram_gates 26>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 130644d7e054..17b36b942d38 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -62,7 +62,7 @@
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
- <&tcon_ch0_clk>;
+ <&tcon_ch0_clk>, <&dram_gates 26>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index b1e4e0170d51..691d3de75b35 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -53,7 +53,7 @@
allwinner,pipeline = "de_be0-lcd0-tve0";
clocks = <&ahb_gates 34>, <&ahb_gates 36>,
<&ahb_gates 44>, <&de_be_clk>,
- <&tcon_ch1_clk>;
+ <&tcon_ch1_clk>, <&dram_gates 26>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 861c5a621e70..426db76c0fe6 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -338,6 +338,25 @@
clock-output-names = "usb_ohci0", "usb_phy";
};
+ dram_gates: clk@01c20100 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun5i-a13-dram-gates-clk";
+ reg = <0x01c20100 0x4>;
+ clocks = <&pll5 0>;
+ clock-indices = <0>,
+ <1>,
+ <25>,
+ <26>,
+ <29>,
+ <31>;
+ clock-output-names = "dram_ve",
+ "dram_csi",
+ "dram_de_fe",
+ "dram_de_be",
+ "dram_ace",
+ "dram_iep";
+ };
+
de_be_clk: clk@01c20104 {
#clock-cells = <0>;
#reset-cells = <0>;
--
2.6.2
--
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[toc] | [prev] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-10-30 15:30 +0100 |
| Subject | [PATCH 11/19] drm: sun4i: Add composite output |
| Message-ID | <qpiQQ-6Tg-49@gated-at.bofh.it> |
| In reply to | #1259525 |
Some Allwinner SoCs have an IP called the TV encoder that is used to output
composite and VGA signals. In such a case, we need to use the second TCON
channel.
Add support for that TV encoder.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/gpu/drm/sun4i/Makefile | 1 +
drivers/gpu/drm/sun4i/sun4i_drv.c | 10 +-
drivers/gpu/drm/sun4i/sun4i_tv.c | 532 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/sun4i/sun4i_tv.h | 18 ++
4 files changed, 560 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/sun4i/sun4i_tv.c
create mode 100644 drivers/gpu/drm/sun4i/sun4i_tv.h
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 4d230b658a05..fc0dc8be82d9 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -6,5 +6,6 @@ sun4i-drm-y += sun4i_layer.o
sun4i-drm-y += sun4i_tcon.o
sun4i-drm-y += sun4i_rgb.o
+sun4i-drm-y += sun4i_tv.o
obj-$(CONFIG_DRM_SUN4I) += sun4i-drm.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index f2c9c8a2eb75..3cf7a9e89afa 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -22,6 +22,7 @@
#include "sun4i_layer.h"
#include "sun4i_rgb.h"
#include "sun4i_tcon.h"
+#include "sun4i_tv.h"
static void sun4i_drv_preclose(struct drm_device *drm,
struct drm_file *file_priv)
@@ -134,12 +135,18 @@ static int sun4i_drv_load(struct drm_device *drm, unsigned long flags)
goto err_free_crtc;
}
+ ret = sun4i_tv_init(drm);
+ if (ret) {
+ dev_err(drm->dev, "Couldn't create our RGB output\n");
+ goto err_free_rgb;
+ }
+
/* Create our framebuffer */
drv->fbdev = sun4i_framebuffer_init(drm);
if (IS_ERR(drv->fbdev)) {
dev_err(drm->dev, "Couldn't create our framebuffer\n");
ret = PTR_ERR(drv->fbdev);
- goto err_free_rgb;
+ goto err_free_tv;
}
/* Enable connectors polling */
@@ -147,6 +154,7 @@ static int sun4i_drv_load(struct drm_device *drm, unsigned long flags)
return 0;
+err_free_tv:
err_free_rgb:
err_free_crtc:
err_free_layers:
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
new file mode 100644
index 000000000000..dc55e340410c
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -0,0 +1,532 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/regmap.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+
+#include "sun4i_backend.h"
+#include "sun4i_drv.h"
+#include "sun4i_tcon.h"
+
+#define SUN4I_TVE_EN_REG 0x000
+#define SUN4I_TVE_EN_DAC_MAP_MASK GENMASK(19, 4)
+#define SUN4I_TVE_EN_DAC_MAP(dac, out) (((out) & 0xf) << (dac + 1) * 4)
+#define SUN4I_TVE_EN_ENABLE BIT(0)
+
+#define SUN4I_TVE_CFG0_REG 0x004
+#define SUN4I_TVE_CFG0_DAC_CONTROL_54M BIT(26)
+#define SUN4I_TVE_CFG0_CORE_DATAPATH_54M BIT(25)
+#define SUN4I_TVE_CFG0_CORE_CONTROL_54M BIT(24)
+#define SUN4I_TVE_CFG0_YC_EN BIT(17)
+#define SUN4I_TVE_CFG0_COMP_EN BIT(16)
+#define SUN4I_TVE_CFG0_RES(x) ((x) & 0xf)
+#define SUN4I_TVE_CFG0_RES_480i SUN4I_TVE_CFG0_RES(0)
+#define SUN4I_TVE_CFG0_RES_576i SUN4I_TVE_CFG0_RES(1)
+
+#define SUN4I_TVE_DAC0_REG 0x008
+#define SUN4I_TVE_DAC0_CLOCK_INVERT BIT(24)
+#define SUN4I_TVE_DAC0_LUMA(x) (((x) & 3) << 20)
+#define SUN4I_TVE_DAC0_LUMA_0_4 SUN4I_TVE_DAC0_LUMA(3)
+#define SUN4I_TVE_DAC0_CHROMA(x) (((x) & 3) << 18)
+#define SUN4I_TVE_DAC0_CHROMA_0_75 SUN4I_TVE_DAC0_CHROMA(3)
+#define SUN4I_TVE_DAC0_INTERNAL_DAC(x) (((x) & 3) << 16)
+#define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS SUN4I_TVE_DAC0_INTERNAL_DAC(3)
+#define SUN4I_TVE_DAC0_DAC_EN(dac) BIT(dac)
+
+#define SUN4I_TVE_NOTCH_REG 0x00c
+#define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x) ((4 - (x)) << (dac * 3))
+
+#define SUN4I_TVE_CHROMA_FREQ_REG 0x010
+
+#define SUN4I_TVE_PORCH_REG 0x014
+#define SUN4I_TVE_PORCH_BACK(x) ((x) << 16)
+#define SUN4I_TVE_PORCH_FRONT(x) (x)
+
+#define SUN4I_TVE_LINE_REG 0x01c
+#define SUN4I_TVE_LINE_FIRST(x) ((x) << 16)
+#define SUN4I_TVE_LINE_NUMBER(x) (x)
+
+#define SUN4I_TVE_LEVEL_REG 0x020
+#define SUN4I_TVE_LEVEL_BLANK(x) ((x) << 16)
+#define SUN4I_TVE_LEVEL_BLACK(x) (x)
+
+#define SUN4I_TVE_DAC1_REG 0x024
+#define SUN4I_TVE_DAC1_AMPLITUDE(dac, x) ((x) << (dac * 8))
+
+#define SUN4I_TVE_DETECT_STA_REG 0x038
+#define SUN4I_TVE_DETECT_STA_DAC(dac) BIT((dac * 8))
+#define SUN4I_TVE_DETECT_STA_UNCONNECTED 0
+#define SUN4I_TVE_DETECT_STA_CONNECTED 1
+#define SUN4I_TVE_DETECT_STA_GROUND 2
+
+#define SUN4I_TVE_CB_CR_LVL_REG 0x10c
+#define SUN4I_TVE_CB_CR_LVL_CR_BURST(x) ((x) << 8)
+#define SUN4I_TVE_CB_CR_LVL_CB_BURST(x) (x)
+
+#define SUN4I_TVE_TINT_BURST_PHASE_REG 0x110
+#define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x) (x)
+
+#define SUN4I_TVE_BURST_WIDTH_REG 0x114
+#define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x) ((x) << 16)
+#define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x) ((x) << 8)
+#define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x) (x)
+
+#define SUN4I_TVE_CB_CR_GAIN_REG 0x118
+#define SUN4I_TVE_CB_CR_GAIN_CR(x) ((x) << 8)
+#define SUN4I_TVE_CB_CR_GAIN_CB(x) (x)
+
+#define SUN4I_TVE_SYNC_VBI_REG 0x11c
+#define SUN4I_TVE_SYNC_VBI_SYNC(x) ((x) << 16)
+#define SUN4I_TVE_SYNC_VBI_VBLANK(x) (x)
+
+#define SUN4I_TVE_ACTIVE_LINE_REG 0x124
+#define SUN4I_TVE_ACTIVE_LINE(x) (x)
+
+#define SUN4I_TVE_CHROMA_REG 0x128
+#define SUN4I_TVE_CHROMA_COMP_GAIN(x) ((x) & 3)
+#define SUN4I_TVE_CHROMA_COMP_GAIN_50 SUN4I_TVE_CHROMA_COMP_GAIN(2)
+
+#define SUN4I_TVE_12C_REG 0x12c
+#define SUN4I_TVE_12C_NOTCH_WIDTH_WIDE BIT(8)
+#define SUN4I_TVE_12C_COMP_YUV_EN BIT(0)
+
+#define SUN4I_TVE_RESYNC_REG 0x130
+#define SUN4I_TVE_RESYNC_FIELD BIT(31)
+#define SUN4I_TVE_RESYNC_LINE(x) ((x) << 16)
+#define SUN4I_TVE_RESYNC_PIXEL(x) (x)
+
+#define SUN4I_TVE_SLAVE_REG 0x134
+
+#define SUN4I_TVE_WSS_DATA2_REG 0x244
+
+struct color_gains {
+ u16 cb;
+ u16 cr;
+};
+
+struct burst_levels {
+ u16 cb;
+ u16 cr;
+};
+
+struct video_levels {
+ u16 black;
+ u16 blank;
+};
+
+struct resync_parameters {
+ bool field;
+ u16 line;
+ u16 pixel;
+};
+
+struct tv_mode {
+ char *name;
+
+ u32 mode;
+ u32 chroma_freq;
+ u16 back_porch;
+ u16 front_porch;
+ u16 line_number;
+ u16 vblank_level;
+
+ u32 hdisplay;
+ u16 hfront_porch;
+ u16 hsync_len;
+ u16 hback_porch;
+
+ u32 vdisplay;
+ u16 vfront_porch;
+ u16 vsync_len;
+ u16 vback_porch;
+
+ bool yc_en;
+ bool dac3_en;
+ bool dac_bit25_en;
+
+ struct color_gains *color_gains;
+ struct burst_levels *burst_levels;
+ struct video_levels *video_levels;
+ struct resync_parameters *resync_params;
+};
+
+struct sun4i_tv {
+ struct drm_connector connector;
+ struct drm_encoder encoder;
+
+ struct clk *clk;
+ struct regmap *regs;
+
+ struct sun4i_drv *drv;
+};
+
+struct tv_mode tv_modes[] = {
+};
+
+static inline struct sun4i_tv *
+drm_encoder_to_sun4i_tv(struct drm_encoder *encoder)
+{
+ return container_of(encoder, struct sun4i_tv,
+ encoder);
+}
+
+static inline struct sun4i_tv *
+drm_connector_to_sun4i_tv(struct drm_connector *connector)
+{
+ return container_of(connector, struct sun4i_tv,
+ connector);
+}
+
+/*
+ * FIXME: If only the drm_display_mode private field was usable, this
+ * could go away...
+ *
+ * So far, it doesn't seem to be preserved when the mode is passed by
+ * to mode_set for some reason.
+ */
+static struct tv_mode *sun4i_tv_find_tv_by_mode(struct drm_display_mode *mode)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
+ struct tv_mode *tv_mode = &tv_modes[i];
+
+ if (!strcmp(mode->name, tv_mode->name))
+ return tv_mode;
+ }
+
+ return NULL;
+}
+
+static int sun4i_tv_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ return 0;
+}
+
+static void sun4i_tv_disable(struct drm_encoder *encoder)
+{
+ struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
+ struct sun4i_drv *drv = tv->drv;
+ struct sun4i_tcon *tcon = drv->tcon;
+
+ DRM_DEBUG_DRIVER("Disabling the TV Output\n");
+
+ sun4i_tcon_disable_channel(tcon, 1);
+
+ regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
+ SUN4I_TVE_EN_ENABLE,
+ 0);
+}
+
+static void sun4i_tv_enable(struct drm_encoder *encoder)
+{
+ struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
+ struct sun4i_drv *drv = tv->drv;
+ struct sun4i_tcon *tcon = drv->tcon;
+
+ DRM_DEBUG_DRIVER("Enabling the TV Output\n");
+
+ regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
+ SUN4I_TVE_EN_ENABLE,
+ SUN4I_TVE_EN_ENABLE);
+
+ sun4i_tcon_enable_channel(tcon, 1);
+}
+
+static void sun4i_tv_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
+ struct sun4i_drv *drv = tv->drv;
+ struct sun4i_tcon *tcon = drv->tcon;
+ struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
+
+ sun4i_backend_apply_color_correction(drv->backend);
+ sun4i_tcon1_mode_set(tcon, mode);
+
+ /* Enable and map the DAC to the output */
+ regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
+ SUN4I_TVE_EN_DAC_MAP_MASK,
+ SUN4I_TVE_EN_DAC_MAP(0, 1) |
+ SUN4I_TVE_EN_DAC_MAP(1, 2) |
+ SUN4I_TVE_EN_DAC_MAP(2, 3) |
+ SUN4I_TVE_EN_DAC_MAP(3, 4));
+
+ /* Set PAL settings */
+ regmap_write(tv->regs, SUN4I_TVE_CFG0_REG,
+ tv_mode->mode |
+ (tv_mode->yc_en ? SUN4I_TVE_CFG0_YC_EN : 0) |
+ SUN4I_TVE_CFG0_COMP_EN |
+ SUN4I_TVE_CFG0_DAC_CONTROL_54M |
+ SUN4I_TVE_CFG0_CORE_DATAPATH_54M |
+ SUN4I_TVE_CFG0_CORE_CONTROL_54M);
+
+ /* Configure the DAC for a composite output */
+ regmap_write(tv->regs, SUN4I_TVE_DAC0_REG,
+ SUN4I_TVE_DAC0_DAC_EN(0) |
+ (tv_mode->dac3_en ? SUN4I_TVE_DAC0_DAC_EN(3) : 0) |
+ SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS |
+ SUN4I_TVE_DAC0_CHROMA_0_75 |
+ SUN4I_TVE_DAC0_LUMA_0_4 |
+ SUN4I_TVE_DAC0_CLOCK_INVERT |
+ (tv_mode->dac_bit25_en ? BIT(25) : 0) |
+ BIT(30));
+
+ /* Configure the sample delay between DAC0 and the other DAC */
+ regmap_write(tv->regs, SUN4I_TVE_NOTCH_REG,
+ SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(1, 0) |
+ SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(2, 0));
+
+ regmap_write(tv->regs, SUN4I_TVE_CHROMA_FREQ_REG,
+ tv_mode->chroma_freq);
+
+ /* Set the front and back porch */
+ regmap_write(tv->regs, SUN4I_TVE_PORCH_REG,
+ SUN4I_TVE_PORCH_BACK(tv_mode->back_porch) |
+ SUN4I_TVE_PORCH_FRONT(tv_mode->front_porch));
+
+ /* Set the lines setup */
+ regmap_write(tv->regs, SUN4I_TVE_LINE_REG,
+ SUN4I_TVE_LINE_FIRST(22) |
+ SUN4I_TVE_LINE_NUMBER(tv_mode->line_number));
+
+ regmap_write(tv->regs, SUN4I_TVE_LEVEL_REG,
+ SUN4I_TVE_LEVEL_BLANK(tv_mode->video_levels->blank) |
+ SUN4I_TVE_LEVEL_BLACK(tv_mode->video_levels->black));
+
+ regmap_write(tv->regs, SUN4I_TVE_DAC1_REG,
+ SUN4I_TVE_DAC1_AMPLITUDE(0, 0x18) |
+ SUN4I_TVE_DAC1_AMPLITUDE(1, 0x18) |
+ SUN4I_TVE_DAC1_AMPLITUDE(2, 0x18) |
+ SUN4I_TVE_DAC1_AMPLITUDE(3, 0x18));
+
+ regmap_write(tv->regs, SUN4I_TVE_CB_CR_LVL_REG,
+ SUN4I_TVE_CB_CR_LVL_CB_BURST(tv_mode->burst_levels->cb) |
+ SUN4I_TVE_CB_CR_LVL_CR_BURST(tv_mode->burst_levels->cr));
+
+ /* Set burst width for a composite output */
+ regmap_write(tv->regs, SUN4I_TVE_BURST_WIDTH_REG,
+ SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(126) |
+ SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(68) |
+ SUN4I_TVE_BURST_WIDTH_BREEZEWAY(22));
+
+ regmap_write(tv->regs, SUN4I_TVE_CB_CR_GAIN_REG,
+ SUN4I_TVE_CB_CR_GAIN_CB(tv_mode->color_gains->cb) |
+ SUN4I_TVE_CB_CR_GAIN_CR(tv_mode->color_gains->cr));
+
+ regmap_write(tv->regs, SUN4I_TVE_SYNC_VBI_REG,
+ SUN4I_TVE_SYNC_VBI_SYNC(0x10) |
+ SUN4I_TVE_SYNC_VBI_VBLANK(tv_mode->vblank_level));
+
+ regmap_write(tv->regs, SUN4I_TVE_ACTIVE_LINE_REG,
+ SUN4I_TVE_ACTIVE_LINE(1440));
+
+ /* Set composite chroma gain to 50 % */
+ regmap_write(tv->regs, SUN4I_TVE_CHROMA_REG,
+ SUN4I_TVE_CHROMA_COMP_GAIN_50);
+
+ regmap_write(tv->regs, SUN4I_TVE_12C_REG,
+ SUN4I_TVE_12C_COMP_YUV_EN |
+ SUN4I_TVE_12C_NOTCH_WIDTH_WIDE);
+
+ regmap_write(tv->regs, SUN4I_TVE_RESYNC_REG,
+ SUN4I_TVE_RESYNC_PIXEL(tv_mode->resync_params->pixel) |
+ SUN4I_TVE_RESYNC_LINE(tv_mode->resync_params->line) |
+ (tv_mode->resync_params->field ?
+ SUN4I_TVE_RESYNC_FIELD : 0));
+
+ regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
+
+ clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
+}
+
+static struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
+ .atomic_check = sun4i_tv_atomic_check,
+ .disable = sun4i_tv_disable,
+ .enable = sun4i_tv_enable,
+ .mode_set = sun4i_tv_mode_set,
+};
+
+static void sun4i_tv_destroy(struct drm_encoder *encoder)
+{
+ drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs sun4i_tv_funcs = {
+ .destroy = sun4i_tv_destroy,
+};
+
+static struct regmap_config sun4i_tv_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SUN4I_TVE_WSS_DATA2_REG,
+ .name = "tv-encoder",
+};
+
+static int sun4i_tv_comp_get_modes(struct drm_connector *connector)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
+ struct drm_display_mode *mode = drm_mode_create(connector->dev);
+ struct tv_mode *tv_mode = &tv_modes[i];
+
+ DRM_DEBUG_DRIVER("Creating mode %s\n", tv_mode->name);
+
+ strcpy(mode->name, tv_mode->name);
+ mode->type = DRM_MODE_TYPE_DRIVER;
+ mode->clock = 13500;
+ mode->flags = DRM_MODE_FLAG_INTERLACE;
+
+ mode->hdisplay = tv_mode->hdisplay;
+ mode->hsync_start = mode->hdisplay + tv_mode->hfront_porch;
+ mode->hsync_end = mode->hsync_start + tv_mode->hsync_len;
+ mode->htotal = mode->hsync_end + tv_mode->hback_porch;
+
+ mode->vdisplay = tv_mode->vdisplay;
+ mode->vsync_start = mode->vdisplay + tv_mode->vfront_porch;
+ mode->vsync_end = mode->vsync_start + tv_mode->vsync_len;
+ mode->vtotal = mode->vsync_end + tv_mode->vback_porch;
+
+ drm_mode_probed_add(connector, mode);
+ }
+
+ return i;
+}
+
+static int sun4i_tv_comp_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ /* TODO */
+ return MODE_OK;
+}
+
+static struct drm_encoder *
+sun4i_tv_comp_best_encoder(struct drm_connector *connector)
+{
+ struct sun4i_tv *tv = drm_connector_to_sun4i_tv(connector);
+
+ return &tv->encoder;
+}
+
+static struct drm_connector_helper_funcs sun4i_tv_comp_connector_helper_funcs = {
+ .get_modes = sun4i_tv_comp_get_modes,
+ .mode_valid = sun4i_tv_comp_mode_valid,
+ .best_encoder = sun4i_tv_comp_best_encoder,
+};
+
+static enum drm_connector_status
+sun4i_tv_comp_connector_detect(struct drm_connector *connector, bool force)
+{
+ return connector_status_connected;
+}
+
+static void
+sun4i_tv_comp_connector_destroy(struct drm_connector *connector)
+{
+ drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs sun4i_tv_comp_connector_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .detect = sun4i_tv_comp_connector_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = sun4i_tv_comp_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+int sun4i_tv_init(struct drm_device *drm)
+{
+ struct sun4i_drv *drv = drm->dev_private;
+ struct device_node *np;
+ struct sun4i_tv *tv;
+ struct resource res;
+ void __iomem *regs;
+ int ret;
+
+ tv = devm_kzalloc(drm->dev, sizeof(*tv), GFP_KERNEL);
+ if (!tv)
+ return -ENOMEM;
+ tv->drv = drv;
+
+ np = of_parse_phandle(drm->dev->of_node, "allwinner,tv-encoder", 0);
+ if (!np) {
+ dev_err(drm->dev, "Couldn't find the TV encoder node\n");
+ return -ENODEV;
+ }
+
+ ret = of_address_to_resource(np, 0, &res);
+ regs = devm_ioremap_resource(drm->dev, &res);
+ if (IS_ERR(regs)) {
+ dev_err(drm->dev, "Couldn't map the TV encoder registers\n");
+ return PTR_ERR(regs);
+ }
+
+ tv->regs = devm_regmap_init_mmio(drm->dev, regs,
+ &sun4i_tv_regmap_config);
+ if (IS_ERR(tv->regs)) {
+ dev_err(drm->dev, "Couldn't create the TV encoder regmap\n");
+ return PTR_ERR(tv->regs);
+ }
+
+ tv->clk = of_clk_get(np, 0);
+ if (IS_ERR(tv->clk)) {
+ dev_err(drm->dev, "Couldn't get the TV encoder clock\n");
+ return PTR_ERR(tv->clk);
+ }
+ clk_prepare_enable(tv->clk);
+
+ drm_encoder_helper_add(&tv->encoder,
+ &sun4i_tv_helper_funcs);
+ ret = drm_encoder_init(drm,
+ &tv->encoder,
+ &sun4i_tv_funcs,
+ DRM_MODE_ENCODER_TVDAC);
+ if (ret) {
+ dev_err(drm->dev, "Couldn't initialise the TV encoder\n");
+ return ret;
+ }
+
+ tv->encoder.possible_crtcs = BIT(0);
+
+ drm_connector_helper_add(&tv->connector,
+ &sun4i_tv_comp_connector_helper_funcs);
+ ret = drm_connector_init(drm, &tv->connector,
+ &sun4i_tv_comp_connector_funcs,
+ DRM_MODE_CONNECTOR_Composite);
+ if (ret) {
+ dev_err(drm->dev,
+ "Couldn't initialise the Composite connector\n");
+ goto err_cleanup_connector;
+ }
+ tv->connector.interlace_allowed = true;
+
+ drm_mode_connector_attach_encoder(&tv->connector, &tv->encoder);
+
+ return 0;
+
+err_cleanup_connector:
+ drm_encoder_cleanup(&tv->encoder);
+ return ret;
+}
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.h b/drivers/gpu/drm/sun4i/sun4i_tv.h
new file mode 100644
index 000000000000..7e39f3581bf9
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2015 Free Electrons
+ * Copyright (C) 2015 NextThing Co
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _SUN4I_TV_H_
+#define _SUN4I_TV_H_
+
+int sun4i_tv_init(struct drm_device *drm);
+
+#endif /* _SUN4I_TV_H_ */
--
2.6.2
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[toc] | [prev] | [next] | [standalone]
| From | Jonathan Liu <net147@gmail.com> |
|---|---|
| Date | 2015-11-02 04:00 +0100 |
| Subject | Re: [linux-sunxi] [PATCH 11/19] drm: sun4i: Add composite output |
| Message-ID | <qqdvI-882-1@gated-at.bofh.it> |
| In reply to | #1259539 |
On 31 October 2015 at 01:20, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some Allwinner SoCs have an IP called the TV encoder that is used to output
> composite and VGA signals. In such a case, we need to use the second TCON
> channel.
>
> Add support for that TV encoder.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/gpu/drm/sun4i/Makefile | 1 +
> drivers/gpu/drm/sun4i/sun4i_drv.c | 10 +-
> drivers/gpu/drm/sun4i/sun4i_tv.c | 532 ++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/sun4i/sun4i_tv.h | 18 ++
> 4 files changed, 560 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/sun4i/sun4i_tv.c
> create mode 100644 drivers/gpu/drm/sun4i/sun4i_tv.h
>
> diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
> index 4d230b658a05..fc0dc8be82d9 100644
> --- a/drivers/gpu/drm/sun4i/Makefile
> +++ b/drivers/gpu/drm/sun4i/Makefile
> @@ -6,5 +6,6 @@ sun4i-drm-y += sun4i_layer.o
> sun4i-drm-y += sun4i_tcon.o
>
> sun4i-drm-y += sun4i_rgb.o
> +sun4i-drm-y += sun4i_tv.o
>
> obj-$(CONFIG_DRM_SUN4I) += sun4i-drm.o
> diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
> index f2c9c8a2eb75..3cf7a9e89afa 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_drv.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
> @@ -22,6 +22,7 @@
> #include "sun4i_layer.h"
> #include "sun4i_rgb.h"
> #include "sun4i_tcon.h"
> +#include "sun4i_tv.h"
>
> static void sun4i_drv_preclose(struct drm_device *drm,
> struct drm_file *file_priv)
> @@ -134,12 +135,18 @@ static int sun4i_drv_load(struct drm_device *drm, unsigned long flags)
> goto err_free_crtc;
> }
>
> + ret = sun4i_tv_init(drm);
> + if (ret) {
> + dev_err(drm->dev, "Couldn't create our RGB output\n");
RGB should be composite. Seems like a copy-paste error.
> + goto err_free_rgb;
> + }
> +
> /* Create our framebuffer */
> drv->fbdev = sun4i_framebuffer_init(drm);
> if (IS_ERR(drv->fbdev)) {
> dev_err(drm->dev, "Couldn't create our framebuffer\n");
> ret = PTR_ERR(drv->fbdev);
> - goto err_free_rgb;
> + goto err_free_tv;
> }
>
> /* Enable connectors polling */
Regards,
Jonathan
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-11-07 01:40 +0100 |
| Subject | Re: [linux-sunxi] [PATCH 11/19] drm: sun4i: Add composite output |
| Message-ID | <qrZHX-3on-7@gated-at.bofh.it> |
| In reply to | #1260311 |
[Multipart message — attachments visible in raw view] — view raw
On Mon, Nov 02, 2015 at 01:53:20PM +1100, Jonathan Liu wrote:
> > + ret = sun4i_tv_init(drm);
> > + if (ret) {
> > + dev_err(drm->dev, "Couldn't create our RGB output\n");
>
> RGB should be composite. Seems like a copy-paste error.
Good catch. Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-10-30 15:30 +0100 |
| Subject | [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS |
| Message-ID | <qpiQP-6Tg-41@gated-at.bofh.it> |
| In reply to | #1259525 |
Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
panel driver.
It is a 480x272 panel connected through a 24-bits RGB interface.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/gpu/drm/panel/panel-simple.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index f97b73ec4713..3a9ecb64d1e6 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -1096,6 +1096,29 @@ static const struct panel_desc shelly_sca07010_bfn_lnn = {
.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
};
+static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
+ .clock = 9000,
+ .hdisplay = 480,
+ .hsync_start = 480 + 5,
+ .hsync_end = 480 + 5 + 30,
+ .htotal = 480 + 5 + 30 + 10,
+ .vdisplay = 272,
+ .vsync_start = 272 + 8,
+ .vsync_end = 272 + 8 + 5,
+ .vtotal = 272 + 8 + 5 + 3,
+ .vrefresh = 60,
+};
+
+static const struct panel_desc olimex_lcd_olinuxino_43ts = {
+ .modes = &olimex_lcd_olinuxino_43ts_mode,
+ .num_modes = 1,
+ .size = {
+ .width = 105,
+ .height = 67,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
static const struct of_device_id platform_of_match[] = {
{
.compatible = "ampire,am800480r3tmqwa1h",
@@ -1191,6 +1214,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "shelly,sca07010-bfn-lnn",
.data = &shelly_sca07010_bfn_lnn,
}, {
+ .compatible = "olimex,lcd-olinuxino-43-ts",
+ .data = &olimex_lcd_olinuxino_43ts,
+ }, {
/* sentinel */
}
};
--
2.6.2
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| From | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| Date | 2015-10-30 18:40 +0100 |
| Subject | Re: [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS |
| Message-ID | <qplOG-eO-7@gated-at.bofh.it> |
| In reply to | #1259540 |
[Multipart message — attachments visible in raw view] — view raw
On Fri, Oct 30, 2015 at 03:20:53PM +0100, Maxime Ripard wrote:
> Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
> panel driver.
>
> It is a 480x272 panel connected through a 24-bits RGB interface.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/gpu/drm/panel/panel-simple.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
I don't see a patch adding the DT binding documentation for this panel.
Also, the olimex vendor prefix isn't defined.
> diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> index f97b73ec4713..3a9ecb64d1e6 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -1096,6 +1096,29 @@ static const struct panel_desc shelly_sca07010_bfn_lnn = {
> .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
> };
>
> +static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
> + .clock = 9000,
> + .hdisplay = 480,
> + .hsync_start = 480 + 5,
> + .hsync_end = 480 + 5 + 30,
> + .htotal = 480 + 5 + 30 + 10,
> + .vdisplay = 272,
> + .vsync_start = 272 + 8,
> + .vsync_end = 272 + 8 + 5,
> + .vtotal = 272 + 8 + 5 + 3,
> + .vrefresh = 60,
> +};
> +
> +static const struct panel_desc olimex_lcd_olinuxino_43ts = {
> + .modes = &olimex_lcd_olinuxino_43ts_mode,
> + .num_modes = 1,
> + .size = {
> + .width = 105,
> + .height = 67,
> + },
> + .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
> +};
> +
These mode and panel descriptors are all sorted alphabetically (by
vendor, by model), please keep it so.
> static const struct of_device_id platform_of_match[] = {
> {
> .compatible = "ampire,am800480r3tmqwa1h",
> @@ -1191,6 +1214,9 @@ static const struct of_device_id platform_of_match[] = {
> .compatible = "shelly,sca07010-bfn-lnn",
> .data = &shelly_sca07010_bfn_lnn,
> }, {
> + .compatible = "olimex,lcd-olinuxino-43-ts",
> + .data = &olimex_lcd_olinuxino_43ts,
> + }, {
> /* sentinel */
> }
Here as well.
Thierry
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-11-07 01:50 +0100 |
| Subject | Re: [PATCH 07/19] drm/panel: simple: Add timings for the Olimex LCD-OLinuXino-4.3TS |
| Message-ID | <qrZRD-3rI-11@gated-at.bofh.it> |
| In reply to | #1259658 |
[Multipart message — attachments visible in raw view] — view raw
Hi Thierry,
On Fri, Oct 30, 2015 at 06:32:30PM +0100, Thierry Reding wrote:
> On Fri, Oct 30, 2015 at 03:20:53PM +0100, Maxime Ripard wrote:
> > Add support for the Olimex LCD-OLinuXino-4.3TS panel to the DRM simple
> > panel driver.
> >
> > It is a 480x272 panel connected through a 24-bits RGB interface.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > drivers/gpu/drm/panel/panel-simple.c | 26 ++++++++++++++++++++++++++
> > 1 file changed, 26 insertions(+)
>
> I don't see a patch adding the DT binding documentation for this panel.
>
> Also, the olimex vendor prefix isn't defined.
>
> > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
> > index f97b73ec4713..3a9ecb64d1e6 100644
> > --- a/drivers/gpu/drm/panel/panel-simple.c
> > +++ b/drivers/gpu/drm/panel/panel-simple.c
> > @@ -1096,6 +1096,29 @@ static const struct panel_desc shelly_sca07010_bfn_lnn = {
> > .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
> > };
> >
> > +static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
> > + .clock = 9000,
> > + .hdisplay = 480,
> > + .hsync_start = 480 + 5,
> > + .hsync_end = 480 + 5 + 30,
> > + .htotal = 480 + 5 + 30 + 10,
> > + .vdisplay = 272,
> > + .vsync_start = 272 + 8,
> > + .vsync_end = 272 + 8 + 5,
> > + .vtotal = 272 + 8 + 5 + 3,
> > + .vrefresh = 60,
> > +};
> > +
> > +static const struct panel_desc olimex_lcd_olinuxino_43ts = {
> > + .modes = &olimex_lcd_olinuxino_43ts_mode,
> > + .num_modes = 1,
> > + .size = {
> > + .width = 105,
> > + .height = 67,
> > + },
> > + .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
> > +};
> > +
>
> These mode and panel descriptors are all sorted alphabetically (by
> vendor, by model), please keep it so.
>
> > static const struct of_device_id platform_of_match[] = {
> > {
> > .compatible = "ampire,am800480r3tmqwa1h",
> > @@ -1191,6 +1214,9 @@ static const struct of_device_id platform_of_match[] = {
> > .compatible = "shelly,sca07010-bfn-lnn",
> > .data = &shelly_sca07010_bfn_lnn,
> > }, {
> > + .compatible = "olimex,lcd-olinuxino-43-ts",
> > + .data = &olimex_lcd_olinuxino_43ts,
> > + }, {
> > /* sentinel */
> > }
>
> Here as well.
Thanks for your feedback, consider it fixed.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-10-30 15:30 +0100 |
| Subject | [PATCH 01/19] clk: sunxi: Add display clock |
| Message-ID | <qpiQP-6Tg-47@gated-at.bofh.it> |
| In reply to | #1259525 |
The A10 SoCs and its relatives has a special clock controller to drive the
display engines (both frontend and backend).
Add a driver for it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-sun4i-display.c | 199 ++++++++++++++++++++++++++++++++++
2 files changed, 200 insertions(+)
create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index cb4c299214ce..a9e1a5885846 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -9,6 +9,7 @@ obj-y += clk-a10-mod1.o
obj-y += clk-a10-pll2.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
+obj-y += clk-sun4i-display.o
obj-y += clk-simple-gates.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
diff --git a/drivers/clk/sunxi/clk-sun4i-display.c b/drivers/clk/sunxi/clk-sun4i-display.c
new file mode 100644
index 000000000000..f13b095c6d7a
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-display.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define SUN4I_A10_DISPLAY_PARENTS 3
+
+#define SUN4I_A10_DISPLAY_GATE_BIT 31
+#define SUN4I_A10_DISPLAY_RESET_BIT 30
+#define SUN4I_A10_DISPLAY_MUX_MASK 3
+#define SUN4I_A10_DISPLAY_MUX_SHIFT 24
+#define SUN4I_A10_DISPLAY_DIV_WIDTH 4
+#define SUN4I_A10_DISPLAY_DIV_SHIFT 0
+
+struct reset_data {
+ void __iomem *reg;
+ spinlock_t *lock;
+ struct reset_controller_dev rcdev;
+};
+
+static DEFINE_SPINLOCK(sun4i_a10_display_lock);
+
+static int sun4i_a10_display_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct reset_data *data = container_of(rcdev,
+ struct reset_data,
+ rcdev);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(data->lock, flags);
+
+ reg = readl(data->reg);
+ writel(reg & ~BIT(SUN4I_A10_DISPLAY_RESET_BIT), data->reg);
+
+ spin_unlock_irqrestore(data->lock, flags);
+
+ return 0;
+}
+
+static int sun4i_a10_display_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct reset_data *data = container_of(rcdev,
+ struct reset_data,
+ rcdev);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(data->lock, flags);
+
+ reg = readl(data->reg);
+ writel(reg | BIT(SUN4I_A10_DISPLAY_RESET_BIT), data->reg);
+
+ spin_unlock_irqrestore(data->lock, flags);
+
+ return 0;
+}
+
+static int sun4i_a10_display_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct reset_data *data = container_of(rcdev,
+ struct reset_data,
+ rcdev);
+
+ return !(readl(data->reg) & BIT(SUN4I_A10_DISPLAY_RESET_BIT));
+}
+
+static struct reset_control_ops sun4i_a10_display_reset_ops = {
+ .assert = sun4i_a10_display_assert,
+ .deassert = sun4i_a10_display_deassert,
+ .status = sun4i_a10_display_status,
+};
+
+static int sun4i_a10_display_reset_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *spec)
+{
+ if (WARN_ON(spec->args_count != rcdev->of_reset_n_cells))
+ return -EINVAL;
+
+ /* We only have a single reset signal */
+ return 0;
+}
+
+static void __init sun4i_a10_display_setup(struct device_node *node)
+{
+ const char *parents[SUN4I_A10_DISPLAY_PARENTS];
+ const char *clk_name = node->name;
+ struct reset_data *reset_data;
+ struct clk_divider *div;
+ struct clk_gate *gate;
+ struct clk_mux *mux;
+ void __iomem *reg;
+ struct clk *clk;
+ int i;
+
+ of_property_read_string(node, "clock-output-names", &clk_name);
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg)) {
+ pr_err("%s: Could not map the clock registers\n", clk_name);
+ return;
+ }
+
+ for (i = 0; i < SUN4I_A10_DISPLAY_PARENTS; i++)
+ parents[i] = of_clk_get_parent_name(node, i);
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return;
+
+ mux->reg = reg;
+ mux->shift = SUN4I_A10_DISPLAY_MUX_SHIFT;
+ mux->mask = SUN4I_A10_DISPLAY_MUX_MASK;
+ mux->lock = &sun4i_a10_display_lock;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ goto free_mux;
+
+ gate->reg = reg;
+ gate->bit_idx = SUN4I_A10_DISPLAY_GATE_BIT;
+ gate->lock = &sun4i_a10_display_lock;
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ goto free_gate;
+
+ div->reg = reg;
+ div->shift = SUN4I_A10_DISPLAY_DIV_SHIFT;
+ div->width = SUN4I_A10_DISPLAY_DIV_WIDTH;
+ div->lock = &sun4i_a10_display_lock;
+
+ clk = clk_register_composite(NULL, clk_name,
+ parents, SUN4I_A10_DISPLAY_PARENTS,
+ &mux->hw, &clk_mux_ops,
+ &div->hw, &clk_divider_ops,
+ &gate->hw, &clk_gate_ops,
+ 0);
+ if (IS_ERR(clk)) {
+ pr_err("%s: Couldn't register the clock\n", clk_name);
+ goto free_div;
+ }
+
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+
+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
+ if (!reset_data)
+ goto free_clk;
+
+ reset_data->reg = reg;
+ reset_data->lock = &sun4i_a10_display_lock;
+ reset_data->rcdev.nr_resets = 1;
+ reset_data->rcdev.ops = &sun4i_a10_display_reset_ops;
+ reset_data->rcdev.of_node = node;
+ reset_data->rcdev.of_reset_n_cells = 0;
+ reset_data->rcdev.of_xlate = &sun4i_a10_display_reset_xlate;
+
+ if (reset_controller_register(&reset_data->rcdev)) {
+ pr_err("%s: Couldn't register the reset controller\n",
+ clk_name);
+ goto free_reset;
+ }
+
+ return;
+
+free_reset:
+ kfree(reset_data);
+free_clk:
+ clk_unregister(clk);
+free_div:
+ kfree(div);
+free_gate:
+ kfree(gate);
+free_mux:
+ kfree(mux);
+}
+
+CLK_OF_DECLARE(sun4i_a10_display, "allwinner,sun4i-a10-display-clk",
+ sun4i_a10_display_setup);
--
2.6.2
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| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Date | 2015-10-30 22:30 +0100 |
| Subject | Re: [PATCH 01/19] clk: sunxi: Add display clock |
| Message-ID | <qpppf-2vw-5@gated-at.bofh.it> |
| In reply to | #1259541 |
On 10/30, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi/clk-sun4i-display.c b/drivers/clk/sunxi/clk-sun4i-display.c
> new file mode 100644
> index 000000000000..f13b095c6d7a
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-display.c
> @@ -0,0 +1,199 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
#include <linux/kernel.h> for container_of?
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/reset-controller.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#define SUN4I_A10_DISPLAY_PARENTS 3
> +
> +#define SUN4I_A10_DISPLAY_GATE_BIT 31
> +#define SUN4I_A10_DISPLAY_RESET_BIT 30
> +#define SUN4I_A10_DISPLAY_MUX_MASK 3
> +#define SUN4I_A10_DISPLAY_MUX_SHIFT 24
> +#define SUN4I_A10_DISPLAY_DIV_WIDTH 4
> +#define SUN4I_A10_DISPLAY_DIV_SHIFT 0
> +
> +struct reset_data {
> + void __iomem *reg;
> + spinlock_t *lock;
> + struct reset_controller_dev rcdev;
> +};
> +
> +static DEFINE_SPINLOCK(sun4i_a10_display_lock);
> +
> +static int sun4i_a10_display_assert(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct reset_data *data = container_of(rcdev,
> + struct reset_data,
> + rcdev);
Can this be a macro rcdev_to_reset_data() or something?
> + unsigned long flags;
[..]
> +
> +static int sun4i_a10_display_status(struct reset_controller_dev *rcdev,
> + unsigned long id)
> +{
> + struct reset_data *data = container_of(rcdev,
> + struct reset_data,
> + rcdev);
> +
> + return !(readl(data->reg) & BIT(SUN4I_A10_DISPLAY_RESET_BIT));
> +}
> +
> +static struct reset_control_ops sun4i_a10_display_reset_ops = {
Someone should make it so this can be const...
> + .assert = sun4i_a10_display_assert,
> + .deassert = sun4i_a10_display_deassert,
> + .status = sun4i_a10_display_status,
> +};
> +
> +static int sun4i_a10_display_reset_xlate(struct reset_controller_dev *rcdev,
> + const struct of_phandle_args *spec)
> +{
> + if (WARN_ON(spec->args_count != rcdev->of_reset_n_cells))
> + return -EINVAL;
Do we really need this check? Seems like something the reset core
should handle.
> +
> + /* We only have a single reset signal */
> + return 0;
> +}
> +
> +static void __init sun4i_a10_display_setup(struct device_node *node)
> +{
> + const char *parents[SUN4I_A10_DISPLAY_PARENTS];
> + const char *clk_name = node->name;
> + struct reset_data *reset_data;
> + struct clk_divider *div;
> + struct clk_gate *gate;
> + struct clk_mux *mux;
> + void __iomem *reg;
> + struct clk *clk;
> + int i;
> +
> + of_property_read_string(node, "clock-output-names", &clk_name);
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg)) {
> + pr_err("%s: Could not map the clock registers\n", clk_name);
> + return;
> + }
> +
> + for (i = 0; i < SUN4I_A10_DISPLAY_PARENTS; i++)
> + parents[i] = of_clk_get_parent_name(node, i);
of_clk_parent_fill()?
> +
> + mux = kzalloc(sizeof(*mux), GFP_KERNEL);
> + if (!mux)
[..]
> + goto free_reset;
> + }
> +
> + return;
> +
> +free_reset:
> + kfree(reset_data);
> +free_clk:
> + clk_unregister(clk);
We really ought to have a clk_composite_unregister() API.
--
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a Linux Foundation Collaborative Project
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-11-07 00:40 +0100 |
| Subject | Re: [PATCH 01/19] clk: sunxi: Add display clock |
| Message-ID | <qrYLT-2ND-7@gated-at.bofh.it> |
| In reply to | #1259802 |
[Multipart message — attachments visible in raw view] — view raw
Hi Stephen, Thanks for your feedback! On Fri, Oct 30, 2015 at 02:29:02PM -0700, Stephen Boyd wrote: > > + > > + mux = kzalloc(sizeof(*mux), GFP_KERNEL); > > + if (!mux) > [..] > > + goto free_reset; > > + } > > + > > + return; > > + > > +free_reset: > > + kfree(reset_data); > > +free_clk: > > + clk_unregister(clk); > > We really ought to have a clk_composite_unregister() API. Can we? We can always unregister the clock itself, but do we have a way to retrieve the structure that has been allocated in there? (note that it also applies to the generic clocks registration: muxes, dividers, and so on). Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Date | 2015-11-12 21:40 +0100 |
| Subject | Re: [PATCH 01/19] clk: sunxi: Add display clock |
| Message-ID | <qu6OZ-5ho-9@gated-at.bofh.it> |
| In reply to | #1264654 |
On 11/06, Maxime Ripard wrote: > Hi Stephen, > > Thanks for your feedback! > > On Fri, Oct 30, 2015 at 02:29:02PM -0700, Stephen Boyd wrote: > > > + > > > + mux = kzalloc(sizeof(*mux), GFP_KERNEL); > > > + if (!mux) > > [..] > > > + goto free_reset; > > > + } > > > + > > > + return; > > > + > > > +free_reset: > > > + kfree(reset_data); > > > +free_clk: > > > + clk_unregister(clk); > > > > We really ought to have a clk_composite_unregister() API. > > Can we? > > We can always unregister the clock itself, but do we have a way to > retrieve the structure that has been allocated in there? > > (note that it also applies to the generic clocks registration: muxes, > dividers, and so on). Yes we have a way. We've done the same sort of design for other generic clocks. Do the __clk_get_hw() thing like in clk-divider.c -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2015-10-31 11:30 +0100 |
| Subject | Re: [PATCH 01/19] clk: sunxi: Add display clock |
| Message-ID | <qpBA6-1C8-19@gated-at.bofh.it> |
| In reply to | #1259541 |
Hi, On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > The A10 SoCs and its relatives has a special clock controller to drive the > display engines (both frontend and backend). > > Add a driver for it. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > --- > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk-sun4i-display.c | 199 ++++++++++++++++++++++++++++++++++ > 2 files changed, 200 insertions(+) > create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c > > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index cb4c299214ce..a9e1a5885846 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -9,6 +9,7 @@ obj-y += clk-a10-mod1.o > obj-y += clk-a10-pll2.o > obj-y += clk-a20-gmac.o > obj-y += clk-mod0.o > +obj-y += clk-sun4i-display.o > obj-y += clk-simple-gates.o > obj-y += clk-sun8i-mbus.o > obj-y += clk-sun9i-core.o > diff --git a/drivers/clk/sunxi/clk-sun4i-display.c b/drivers/clk/sunxi/clk-sun4i-display.c > new file mode 100644 > index 000000000000..f13b095c6d7a > --- /dev/null > +++ b/drivers/clk/sunxi/clk-sun4i-display.c > @@ -0,0 +1,199 @@ > +/* > + * Copyright 2015 Maxime Ripard > + * > + * Maxime Ripard <maxime.ripard@free-electrons.com> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/of_address.h> > +#include <linux/reset-controller.h> > +#include <linux/slab.h> > +#include <linux/spinlock.h> > + > +#define SUN4I_A10_DISPLAY_PARENTS 3 Can we change this to 4, so we can reuse this for TCON clocks on sun4i/sun7i? Thanks ChenYu > +#define SUN4I_A10_DISPLAY_GATE_BIT 31 > +#define SUN4I_A10_DISPLAY_RESET_BIT 30 > +#define SUN4I_A10_DISPLAY_MUX_MASK 3 > +#define SUN4I_A10_DISPLAY_MUX_SHIFT 24 > +#define SUN4I_A10_DISPLAY_DIV_WIDTH 4 > +#define SUN4I_A10_DISPLAY_DIV_SHIFT 0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-11-06 20:50 +0100 |
| Subject | Re: [PATCH 01/19] clk: sunxi: Add display clock |
| Message-ID | <qrVbk-k7-17@gated-at.bofh.it> |
| In reply to | #1259969 |
[Multipart message — attachments visible in raw view] — view raw
Hi, On Sat, Oct 31, 2015 at 06:28:16PM +0800, Chen-Yu Tsai wrote: > Hi, > > On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > > The A10 SoCs and its relatives has a special clock controller to drive the > > display engines (both frontend and backend). > > > > Add a driver for it. > > > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > --- > > drivers/clk/sunxi/Makefile | 1 + > > drivers/clk/sunxi/clk-sun4i-display.c | 199 ++++++++++++++++++++++++++++++++++ > > 2 files changed, 200 insertions(+) > > create mode 100644 drivers/clk/sunxi/clk-sun4i-display.c > > > > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > > index cb4c299214ce..a9e1a5885846 100644 > > --- a/drivers/clk/sunxi/Makefile > > +++ b/drivers/clk/sunxi/Makefile > > @@ -9,6 +9,7 @@ obj-y += clk-a10-mod1.o > > obj-y += clk-a10-pll2.o > > obj-y += clk-a20-gmac.o > > obj-y += clk-mod0.o > > +obj-y += clk-sun4i-display.o > > obj-y += clk-simple-gates.o > > obj-y += clk-sun8i-mbus.o > > obj-y += clk-sun9i-core.o > > diff --git a/drivers/clk/sunxi/clk-sun4i-display.c b/drivers/clk/sunxi/clk-sun4i-display.c > > new file mode 100644 > > index 000000000000..f13b095c6d7a > > --- /dev/null > > +++ b/drivers/clk/sunxi/clk-sun4i-display.c > > @@ -0,0 +1,199 @@ > > +/* > > + * Copyright 2015 Maxime Ripard > > + * > > + * Maxime Ripard <maxime.ripard@free-electrons.com> > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License as published by > > + * the Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + */ > > + > > +#include <linux/clk-provider.h> > > +#include <linux/of_address.h> > > +#include <linux/reset-controller.h> > > +#include <linux/slab.h> > > +#include <linux/spinlock.h> > > + > > +#define SUN4I_A10_DISPLAY_PARENTS 3 > > Can we change this to 4, so we can reuse this for TCON clocks on > sun4i/sun7i? Good point, I'll change this. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-10-30 15:30 +0100 |
| Subject | [PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks |
| Message-ID | <qpiQQ-6Tg-53@gated-at.bofh.it> |
| In reply to | #1259525 |
Enable the pll3 and pll7 clocks in the DT that are used to drive the
display-related clocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 59a9426e3bd4..bde9a545b79f 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -88,6 +88,15 @@
clock-output-names = "osc24M";
};
+ osc3M: osc3M_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <8>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "osc3M";
+ };
+
osc32k: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -112,6 +121,14 @@
"pll2-4x", "pll2-8x";
};
+ pll3: clk@01c20010 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll3-clk";
+ reg = <0x01c20010 0x4>;
+ clocks = <&osc3M>;
+ clock-output-names = "pll3";
+ };
+
pll4: clk@01c20018 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -136,6 +153,14 @@
clock-output-names = "pll6_sata", "pll6_other", "pll6";
};
+ pll7: clk@01c20030 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll3-clk";
+ reg = <0x01c20030 0x4>;
+ clocks = <&osc3M>;
+ clock-output-names = "pll7";
+ };
+
/* dummy is 200M */
cpu: cpu@01c20054 {
#clock-cells = <0>;
--
2.6.2
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2015-11-09 05:30 +0100 |
| Subject | Re: [PATCH 14/19] ARM: sun5i: dt: Add pll3 and pll7 clocks |
| Message-ID | <qsMfE-1po-7@gated-at.bofh.it> |
| In reply to | #1259544 |
On Fri, Oct 30, 2015 at 10:21 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Enable the pll3 and pll7 clocks in the DT that are used to drive the > display-related clocks. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-10-30 15:30 +0100 |
| Subject | [PATCH 04/19] clk: sunxi: Add TCON channel1 clock |
| Message-ID | <qpiQQ-6Tg-57@gated-at.bofh.it> |
| In reply to | #1259525 |
The TCON is a controller generating the timings to output videos signals,
acting like both a CRTC and an encoder.
It has two channels depending on the output, each channel being driven by
its own clock (and own clock controller).
Add a driver for the channel 1 clock.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-sun4i-tcon-ch1.c | 167 +++++++++++++++++++++++++++++++++
2 files changed, 168 insertions(+)
create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 7821b2b63d58..ed59ee4b3a85 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y += clk-simple-gates.o
obj-y += clk-sun4i-display.o
obj-y += clk-sun4i-pll3.o
obj-y += clk-sun4i-tcon-ch0.o
+obj-y += clk-sun4i-tcon-ch1.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
new file mode 100644
index 000000000000..9f2ab52b0bf9
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define SUN4I_TCON_CH1_SCLK_NAME_LEN 32
+
+#define SUN4I_A10_TCON_CH1_SCLK1_PARENTS 2
+#define SUN4I_A10_TCON_CH1_SCLK2_PARENTS 4
+
+#define SUN4I_A10_TCON_CH1_SCLK2_GATE_BIT 31
+#define SUN4I_A10_TCON_CH1_SCLK2_MUX_MASK 3
+#define SUN4I_A10_TCON_CH1_SCLK2_MUX_SHIFT 24
+#define SUN4I_A10_TCON_CH1_SCLK2_DIV_WIDTH 4
+#define SUN4I_A10_TCON_CH1_SCLK2_DIV_SHIFT 0
+
+#define SUN4I_A10_TCON_CH1_SCLK1_GATE_BIT 15
+#define SUN4I_A10_TCON_CH1_SCLK1_MUX_MASK 1
+#define SUN4I_A10_TCON_CH1_SCLK1_MUX_SHIFT 11
+
+static DEFINE_SPINLOCK(sun4i_a10_tcon_ch1_lock);
+
+static void __init sun4i_a10_tcon_ch1_setup(struct device_node *node)
+{
+ const char *sclk1_parents[SUN4I_A10_TCON_CH1_SCLK1_PARENTS];
+ const char *sclk2_parents[SUN4I_A10_TCON_CH1_SCLK2_PARENTS];
+ const char *sclk1_name = node->name;
+ char sclk2_name[SUN4I_TCON_CH1_SCLK_NAME_LEN];
+ char sclk2d2_name[SUN4I_TCON_CH1_SCLK_NAME_LEN];
+ struct clk_gate *sclk1_gate, *sclk2_gate;
+ struct clk_mux *sclk1_mux, *sclk2_mux;
+ struct clk *sclk1, *sclk2, *sclk2d2;
+ struct clk_divider *sclk2_div;
+ void __iomem *reg;
+ int i;
+
+ of_property_read_string(node, "clock-output-names",
+ &sclk1_name);
+
+ snprintf(sclk2_name, SUN4I_TCON_CH1_SCLK_NAME_LEN,
+ "%s2", sclk1_name);
+
+ snprintf(sclk2d2_name, SUN4I_TCON_CH1_SCLK_NAME_LEN,
+ "%s2d2", sclk1_name);
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg)) {
+ pr_err("%s: Could not map the clock registers\n", sclk2_name);
+ return;
+ }
+
+ for (i = 0; i < SUN4I_A10_TCON_CH1_SCLK2_PARENTS; i++)
+ sclk2_parents[i] = of_clk_get_parent_name(node, i);
+
+ sclk2_mux = kzalloc(sizeof(*sclk2_mux), GFP_KERNEL);
+ if (!sclk2_mux)
+ return;
+
+ sclk2_mux->reg = reg;
+ sclk2_mux->shift = SUN4I_A10_TCON_CH1_SCLK2_MUX_SHIFT;
+ sclk2_mux->mask = SUN4I_A10_TCON_CH1_SCLK2_MUX_MASK;
+ sclk2_mux->lock = &sun4i_a10_tcon_ch1_lock;
+
+ sclk2_gate = kzalloc(sizeof(*sclk2_gate), GFP_KERNEL);
+ if (!sclk2_gate)
+ goto free_sclk2_mux;
+
+ sclk2_gate->reg = reg;
+ sclk2_gate->bit_idx = SUN4I_A10_TCON_CH1_SCLK2_GATE_BIT;
+ sclk2_gate->lock = &sun4i_a10_tcon_ch1_lock;
+
+ sclk2_div = kzalloc(sizeof(*sclk2_div), GFP_KERNEL);
+ if (!sclk2_div)
+ goto free_sclk2_gate;
+
+ sclk2_div->reg = reg;
+ sclk2_div->shift = SUN4I_A10_TCON_CH1_SCLK2_DIV_SHIFT;
+ sclk2_div->width = SUN4I_A10_TCON_CH1_SCLK2_DIV_WIDTH;
+ sclk2_div->lock = &sun4i_a10_tcon_ch1_lock;
+
+ sclk2 = clk_register_composite(NULL, sclk2_name, sclk2_parents,
+ SUN4I_A10_TCON_CH1_SCLK2_PARENTS,
+ &sclk2_mux->hw, &clk_mux_ops,
+ &sclk2_div->hw, &clk_divider_ops,
+ &sclk2_gate->hw, &clk_gate_ops,
+ 0);
+ if (IS_ERR(sclk2)) {
+ pr_err("%s: Couldn't register the clock\n", sclk2_name);
+ goto free_sclk2_div;
+ }
+
+ sclk2d2 = clk_register_fixed_factor(NULL, sclk2d2_name, sclk2_name, 0,
+ 1, 2);
+ if (IS_ERR(sclk2d2)) {
+ pr_err("%s: Couldn't register the clock\n", sclk2d2_name);
+ goto free_sclk2;
+ }
+
+ sclk1_parents[0] = sclk2_name;
+ sclk1_parents[1] = sclk2d2_name;
+
+ sclk1_mux = kzalloc(sizeof(*sclk1_mux), GFP_KERNEL);
+ if (!sclk1_mux)
+ goto free_sclk2d2;
+
+ sclk1_mux->reg = reg;
+ sclk1_mux->shift = SUN4I_A10_TCON_CH1_SCLK1_MUX_SHIFT;
+ sclk1_mux->mask = SUN4I_A10_TCON_CH1_SCLK1_MUX_MASK;
+ sclk1_mux->lock = &sun4i_a10_tcon_ch1_lock;
+
+ sclk1_gate = kzalloc(sizeof(*sclk1_gate), GFP_KERNEL);
+ if (!sclk1_gate)
+ goto free_sclk1_mux;
+
+ sclk1_gate->reg = reg;
+ sclk1_gate->bit_idx = SUN4I_A10_TCON_CH1_SCLK1_GATE_BIT;
+ sclk1_gate->lock = &sun4i_a10_tcon_ch1_lock;
+
+ sclk1 = clk_register_composite(NULL, sclk1_name, sclk1_parents,
+ SUN4I_A10_TCON_CH1_SCLK1_PARENTS,
+ &sclk1_mux->hw, &clk_mux_ops,
+ NULL, NULL,
+ &sclk1_gate->hw, &clk_gate_ops,
+ 0);
+ if (IS_ERR(sclk1)) {
+ pr_err("%s: Couldn't register the clock\n", sclk1_name);
+ goto free_sclk1_gate;
+ }
+
+ of_clk_add_provider(node, of_clk_src_simple_get, sclk1);
+
+ return;
+
+free_sclk1_gate:
+ kfree(sclk1_gate);
+free_sclk1_mux:
+ kfree(sclk1_mux);
+free_sclk2d2:
+ clk_unregister(sclk2d2);
+free_sclk2:
+ clk_unregister(sclk2);
+free_sclk2_div:
+ kfree(sclk2_div);
+free_sclk2_gate:
+ kfree(sclk2_gate);
+free_sclk2_mux:
+ kfree(sclk2_mux);
+}
+
+CLK_OF_DECLARE(sun4i_a10_tcon_ch1, "allwinner,sun4i-a10-tcon-ch1-clk",
+ sun4i_a10_tcon_ch1_setup);
--
2.6.2
--
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| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Date | 2015-10-30 22:40 +0100 |
| Subject | Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock |
| Message-ID | <qppyW-2yK-15@gated-at.bofh.it> |
| In reply to | #1259545 |
On 10/30, Maxime Ripard wrote: > The TCON is a controller generating the timings to output videos signals, > acting like both a CRTC and an encoder. > > It has two channels depending on the output, each channel being driven by > its own clock (and own clock controller). > > Add a driver for the channel 1 clock. > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Similar comments apply to patches 3 and 4. Was the same code copy/pasted two more times and then changed to have different values? Looks like we should consolidate all that stuff into something more generic so that we don't have the same problems 3 times. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2015-11-07 01:20 +0100 |
| Subject | Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock |
| Message-ID | <qrZoB-3h8-5@gated-at.bofh.it> |
| In reply to | #1259806 |
[Multipart message — attachments visible in raw view] — view raw
Hi, On Fri, Oct 30, 2015 at 02:37:34PM -0700, Stephen Boyd wrote: > On 10/30, Maxime Ripard wrote: > > The TCON is a controller generating the timings to output videos signals, > > acting like both a CRTC and an encoder. > > > > It has two channels depending on the output, each channel being driven by > > its own clock (and own clock controller). > > > > Add a driver for the channel 1 clock. > > > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > Similar comments apply to patches 3 and 4. Was the same code > copy/pasted two more times and then changed to have different > values? I don't really recall, but I probably used the same skeleton yeah. > Looks like we should consolidate all that stuff into something more > generic so that we don't have the same problems 3 times. Does it? They're both pretty different actually. One is a gate + mux + reset (patch 3), the other one is actually a combination of two clocks, one that is the parent of the other, the former being a gate + mux, the latter a gate + div. At least at the hardware level, they're very different, and adding more code to deal with both case would complicate quite a lot the probe code, for no real reasons. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2015-10-31 11:00 +0100 |
| Subject | Re: [PATCH 04/19] clk: sunxi: Add TCON channel1 clock |
| Message-ID | <qpB75-1cS-13@gated-at.bofh.it> |
| In reply to | #1259545 |
On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The TCON is a controller generating the timings to output videos signals,
> acting like both a CRTC and an encoder.
>
> It has two channels depending on the output, each channel being driven by
> its own clock (and own clock controller).
>
> Add a driver for the channel 1 clock.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/clk/sunxi/Makefile | 1 +
> drivers/clk/sunxi/clk-sun4i-tcon-ch1.c | 167 +++++++++++++++++++++++++++++++++
> 2 files changed, 168 insertions(+)
> create mode 100644 drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
According to the documents I have, this variant of the TCON clock
is specific to sun5i. On sun4i/sun7i, TCON CH1 clock has the same
layout as TCON CH0 and the other display clocks.
>
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index 7821b2b63d58..ed59ee4b3a85 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -13,6 +13,7 @@ obj-y += clk-simple-gates.o
> obj-y += clk-sun4i-display.o
> obj-y += clk-sun4i-pll3.o
> obj-y += clk-sun4i-tcon-ch0.o
> +obj-y += clk-sun4i-tcon-ch1.o
> obj-y += clk-sun8i-mbus.o
> obj-y += clk-sun9i-core.o
> obj-y += clk-sun9i-mmc.o
> diff --git a/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
> new file mode 100644
> index 000000000000..9f2ab52b0bf9
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
> @@ -0,0 +1,167 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#define SUN4I_TCON_CH1_SCLK_NAME_LEN 32
> +
> +#define SUN4I_A10_TCON_CH1_SCLK1_PARENTS 2
> +#define SUN4I_A10_TCON_CH1_SCLK2_PARENTS 4
> +
> +#define SUN4I_A10_TCON_CH1_SCLK2_GATE_BIT 31
> +#define SUN4I_A10_TCON_CH1_SCLK2_MUX_MASK 3
> +#define SUN4I_A10_TCON_CH1_SCLK2_MUX_SHIFT 24
> +#define SUN4I_A10_TCON_CH1_SCLK2_DIV_WIDTH 4
> +#define SUN4I_A10_TCON_CH1_SCLK2_DIV_SHIFT 0
> +
> +#define SUN4I_A10_TCON_CH1_SCLK1_GATE_BIT 15
> +#define SUN4I_A10_TCON_CH1_SCLK1_MUX_MASK 1
> +#define SUN4I_A10_TCON_CH1_SCLK1_MUX_SHIFT 11
> +
> +static DEFINE_SPINLOCK(sun4i_a10_tcon_ch1_lock);
> +
> +static void __init sun4i_a10_tcon_ch1_setup(struct device_node *node)
> +{
> + const char *sclk1_parents[SUN4I_A10_TCON_CH1_SCLK1_PARENTS];
> + const char *sclk2_parents[SUN4I_A10_TCON_CH1_SCLK2_PARENTS];
> + const char *sclk1_name = node->name;
> + char sclk2_name[SUN4I_TCON_CH1_SCLK_NAME_LEN];
> + char sclk2d2_name[SUN4I_TCON_CH1_SCLK_NAME_LEN];
> + struct clk_gate *sclk1_gate, *sclk2_gate;
> + struct clk_mux *sclk1_mux, *sclk2_mux;
> + struct clk *sclk1, *sclk2, *sclk2d2;
> + struct clk_divider *sclk2_div;
> + void __iomem *reg;
> + int i;
> +
> + of_property_read_string(node, "clock-output-names",
> + &sclk1_name);
> +
> + snprintf(sclk2_name, SUN4I_TCON_CH1_SCLK_NAME_LEN,
> + "%s2", sclk1_name);
> +
> + snprintf(sclk2d2_name, SUN4I_TCON_CH1_SCLK_NAME_LEN,
> + "%s2d2", sclk1_name);
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> + if (IS_ERR(reg)) {
> + pr_err("%s: Could not map the clock registers\n", sclk2_name);
> + return;
> + }
> +
> + for (i = 0; i < SUN4I_A10_TCON_CH1_SCLK2_PARENTS; i++)
> + sclk2_parents[i] = of_clk_get_parent_name(node, i);
> +
> + sclk2_mux = kzalloc(sizeof(*sclk2_mux), GFP_KERNEL);
> + if (!sclk2_mux)
> + return;
> +
> + sclk2_mux->reg = reg;
> + sclk2_mux->shift = SUN4I_A10_TCON_CH1_SCLK2_MUX_SHIFT;
> + sclk2_mux->mask = SUN4I_A10_TCON_CH1_SCLK2_MUX_MASK;
> + sclk2_mux->lock = &sun4i_a10_tcon_ch1_lock;
> +
> + sclk2_gate = kzalloc(sizeof(*sclk2_gate), GFP_KERNEL);
> + if (!sclk2_gate)
> + goto free_sclk2_mux;
> +
> + sclk2_gate->reg = reg;
> + sclk2_gate->bit_idx = SUN4I_A10_TCON_CH1_SCLK2_GATE_BIT;
> + sclk2_gate->lock = &sun4i_a10_tcon_ch1_lock;
> +
> + sclk2_div = kzalloc(sizeof(*sclk2_div), GFP_KERNEL);
> + if (!sclk2_div)
> + goto free_sclk2_gate;
> +
> + sclk2_div->reg = reg;
> + sclk2_div->shift = SUN4I_A10_TCON_CH1_SCLK2_DIV_SHIFT;
> + sclk2_div->width = SUN4I_A10_TCON_CH1_SCLK2_DIV_WIDTH;
> + sclk2_div->lock = &sun4i_a10_tcon_ch1_lock;
> +
> + sclk2 = clk_register_composite(NULL, sclk2_name, sclk2_parents,
> + SUN4I_A10_TCON_CH1_SCLK2_PARENTS,
> + &sclk2_mux->hw, &clk_mux_ops,
> + &sclk2_div->hw, &clk_divider_ops,
> + &sclk2_gate->hw, &clk_gate_ops,
> + 0);
> + if (IS_ERR(sclk2)) {
> + pr_err("%s: Couldn't register the clock\n", sclk2_name);
> + goto free_sclk2_div;
> + }
> +
> + sclk2d2 = clk_register_fixed_factor(NULL, sclk2d2_name, sclk2_name, 0,
> + 1, 2);
> + if (IS_ERR(sclk2d2)) {
> + pr_err("%s: Couldn't register the clock\n", sclk2d2_name);
> + goto free_sclk2;
> + }
> +
> + sclk1_parents[0] = sclk2_name;
> + sclk1_parents[1] = sclk2d2_name;
Is there any need to expose these 2 clocks via DT using of_clk_add_provider?
Note that these complex clock trees within a clock node breaks the
assigned-clock-parents mechanism, as you can no longer specify the output
clock's direct parents.
Regards
ChenYu
> +
> + sclk1_mux = kzalloc(sizeof(*sclk1_mux), GFP_KERNEL);
> + if (!sclk1_mux)
> + goto free_sclk2d2;
> +
> + sclk1_mux->reg = reg;
> + sclk1_mux->shift = SUN4I_A10_TCON_CH1_SCLK1_MUX_SHIFT;
> + sclk1_mux->mask = SUN4I_A10_TCON_CH1_SCLK1_MUX_MASK;
> + sclk1_mux->lock = &sun4i_a10_tcon_ch1_lock;
> +
> + sclk1_gate = kzalloc(sizeof(*sclk1_gate), GFP_KERNEL);
> + if (!sclk1_gate)
> + goto free_sclk1_mux;
> +
> + sclk1_gate->reg = reg;
> + sclk1_gate->bit_idx = SUN4I_A10_TCON_CH1_SCLK1_GATE_BIT;
> + sclk1_gate->lock = &sun4i_a10_tcon_ch1_lock;
> +
> + sclk1 = clk_register_composite(NULL, sclk1_name, sclk1_parents,
> + SUN4I_A10_TCON_CH1_SCLK1_PARENTS,
> + &sclk1_mux->hw, &clk_mux_ops,
> + NULL, NULL,
> + &sclk1_gate->hw, &clk_gate_ops,
> + 0);
> + if (IS_ERR(sclk1)) {
> + pr_err("%s: Couldn't register the clock\n", sclk1_name);
> + goto free_sclk1_gate;
> + }
> +
> + of_clk_add_provider(node, of_clk_src_simple_get, sclk1);
> +
> + return;
> +
> +free_sclk1_gate:
> + kfree(sclk1_gate);
> +free_sclk1_mux:
> + kfree(sclk1_mux);
> +free_sclk2d2:
> + clk_unregister(sclk2d2);
> +free_sclk2:
> + clk_unregister(sclk2);
> +free_sclk2_div:
> + kfree(sclk2_div);
> +free_sclk2_gate:
> + kfree(sclk2_gate);
> +free_sclk2_mux:
> + kfree(sclk2_mux);
> +}
> +
> +CLK_OF_DECLARE(sun4i_a10_tcon_ch1, "allwinner,sun4i-a10-tcon-ch1-clk",
> + sun4i_a10_tcon_ch1_setup);
> --
> 2.6.2
>
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