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| Started by | Caesar Wang <wxt@rock-chips.com> |
|---|---|
| First post | 2015-10-21 04:50 +0200 |
| Last post | 2015-10-21 15:40 +0200 |
| Articles | 3 — 2 participants |
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[PATCH v1 2/2] ARM: dts: rockchip: Add the OTP gpio pinctrl Caesar Wang <wxt@rock-chips.com> - 2015-10-21 04:50 +0200
Re: [PATCH v1 2/2] ARM: dts: rockchip: Add the OTP gpio pinctrl Doug Anderson <dianders@chromium.org> - 2015-10-21 06:30 +0200
Re: [PATCH v1 2/2] ARM: dts: rockchip: Add the OTP gpio pinctrl Doug Anderson <dianders@chromium.org> - 2015-10-21 15:40 +0200
| From | Caesar Wang <wxt@rock-chips.com> |
|---|---|
| Date | 2015-10-21 04:50 +0200 |
| Subject | [PATCH v1 2/2] ARM: dts: rockchip: Add the OTP gpio pinctrl |
| Message-ID | <qlRDr-6mE-1@gated-at.bofh.it> |
We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---
Changes in v1:
- As the Doug comments, drop the thermal driver patchs since
we can with pinctrl changing to work.
- As the Doug's patch to add the 'init' property.
arch/arm/boot/dts/rk3288.dtsi | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..6ea89aa 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,9 @@
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- pinctrl-names = "default";
- pinctrl-0 = <&otp_out>;
+ pinctrl-names = "init", "default";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
@@ -1273,6 +1274,10 @@
};
tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
otp_out: otp-out {
rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
};
--
1.9.1
--
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| From | Doug Anderson <dianders@chromium.org> |
|---|---|
| Date | 2015-10-21 06:30 +0200 |
| Message-ID | <qlTce-ll-5@gated-at.bofh.it> |
| In reply to | #1252434 |
Caesar, On Tue, Oct 20, 2015 at 7:43 PM, Caesar Wang <wxt@rock-chips.com> wrote: > We need the OTP pin is gpio state before resetting the TSADC controller, > since the tshut polarity will generate a high signal. It might or might not be "high" depending on polarity, right? It's just possible that it could glitch during probe. Other than that nit, this seems fine to me. If it's not too much trouble it'd be nice if you could spin with the description change. Otherwise: Reviewed-by: Douglas Anderson <dianders@chromium.org> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Doug Anderson <dianders@chromium.org> |
|---|---|
| Date | 2015-10-21 15:40 +0200 |
| Message-ID | <qm1Mt-4re-5@gated-at.bofh.it> |
| In reply to | #1252459 |
Caesar, On Tue, Oct 20, 2015 at 9:42 PM, Caesar Wang <wxt@rock-chips.com> wrote: > I think the description is right, maybe need other decriptions. > The tshut polarity is low in a short period of time when the TSADC > controller is reset. > > In other words, > > If T < (setting temperature), the OTP output the High Signal. ------> if the > otp out polarity is high, the TSHUT will work. > If T > (setting temperature), the OTP output the Low Signal. Ah! I re-read the cover letter more carefully and now I see. OK, I think your current description is fine, then. ;) -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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