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[PATCH v2 0/2] Fix display on second resume on 5250-snow

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  [PATCH v2 0/2] Fix display on second resume on 5250-snow Tomeu Vizoso <tomeu.vizoso@collabora.com> - 2015-10-15 12:40 +0200
    [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Tomeu Vizoso <tomeu.vizoso@collabora.com> - 2015-10-15 12:40 +0200
      Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-10-16 01:50 +0200
        Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Michael Turquette <mturquette@baylibre.com> - 2015-10-16 14:50 +0200
          Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Stephen Boyd <sboyd@codeaurora.org> - 2015-10-16 19:30 +0200
            Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Tomeu Vizoso <tomeu.vizoso@collabora.com> - 2015-10-16 21:00 +0200
              Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Kukjin Kim <kgene@kernel.org> - 2015-10-17 01:50 +0200
                Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-10-17 11:00 +0200
                  Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Javier Martinez Canillas <javier@osg.samsung.com> - 2015-10-17 12:00 +0200
                    Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-10-17 12:10 +0200
    [PATCH v2 2/2] ARM: dts: exynos5250: Add clocks to DISP1 domain Tomeu Vizoso <tomeu.vizoso@collabora.com> - 2015-10-15 12:40 +0200
      Re: [PATCH v2 2/2] ARM: dts: exynos5250: Add clocks to DISP1 domain Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-10-16 01:50 +0200
        Re: [PATCH v2 2/2] ARM: dts: exynos5250: Add clocks to DISP1 domain Tomeu Vizoso <tomeu.vizoso@collabora.com> - 2015-10-16 10:20 +0200

#1247650 — [PATCH v2 0/2] Fix display on second resume on 5250-snow

Hi,

as discussed in [0], currently on the second resume from memory the
display is broken on Snow boards (ARM Samsung Series 3 Chromebook).

The reason is that on resume the contents of register SRC_TOP3 aren't
what the kernel thinks they are because the HW (or FW) is doing some
clock reparenting beneath our feet.

This series tasks the kernel to do the reparenting itself so that the HW
state always matches the kernel's internal state.

Thanks,

Tomeu

[0] http://lkml.kernel.org/g/561CDC33.7050103@collabora.com

Changes in v2:
- Reuse mout_aclk200_p
- Rename div_aclk300 as div_aclk300_disp

Tomeu Vizoso (2):
  clk: samsung: exynos5250: Add DISP1 clocks
  ARM: dts: exynos5250: Add clocks to DISP1 domain

 arch/arm/boot/dts/exynos5250.dtsi      |  4 ++++
 drivers/clk/samsung/clk-exynos5250.c   | 14 +++++++++++++-
 include/dt-bindings/clock/exynos5250.h |  4 +++-
 3 files changed, 20 insertions(+), 2 deletions(-)

-- 
2.5.0

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#1247654 — [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

When the DISP1 power domain is powered off, there's two clocks that need
to be temporarily reparented to OSC, and back to their original parents
when the domain is powered on again.

We expose these two clocks in the DT bindings so that the DT node of the
power domain can reference them.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
---

Changes in v2:
- Reuse mout_aclk200_p
- Rename div_aclk300 as div_aclk300_disp

 drivers/clk/samsung/clk-exynos5250.c   | 14 +++++++++++++-
 include/dt-bindings/clock/exynos5250.h |  4 +++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 55b83c7ef878..5bebf8cb0d70 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -222,9 +222,13 @@ PNAME(mout_mpll_user_p)	= { "fin_pll", "mout_mpll" };
 PNAME(mout_bpll_user_p)	= { "fin_pll", "mout_bpll" };
 PNAME(mout_aclk166_p)	= { "mout_cpll", "mout_mpll_user" };
 PNAME(mout_aclk200_p)	= { "mout_mpll_user", "mout_bpll_user" };
+PNAME(mout_aclk300_p)	= { "mout_aclk300_disp1_mid",
+			    "mout_aclk300_disp1_mid1" };
 PNAME(mout_aclk400_p)	= { "mout_aclk400_g3d_mid", "mout_gpll" };
 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" };
 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" };
+PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" };
+PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" };
 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" };
 PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" };
 PNAME(mout_hdmi_p)	= { "div_hdmi_pixel", "sclk_hdmiphy" };
@@ -303,9 +307,13 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	 */
 	MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1),
 	MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1),
+	MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1),
+	MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1),
 	MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1),
 	MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1),
 
+	MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1,
+		8, 1),
 	MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1),
 	MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1),
 
@@ -316,7 +324,10 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = {
 	MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1),
 	MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1),
 
-	MUX(0, "mout_aclk200_disp1_sub", mout_aclk200_sub_p, SRC_TOP3, 4, 1),
+	MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub",
+		mout_aclk200_sub_p, SRC_TOP3, 4, 1),
+	MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub",
+		mout_aclk300_sub_p, SRC_TOP3, 6, 1),
 	MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1),
 	MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1),
 	MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p,
@@ -392,6 +403,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = {
 	DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
 	DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0,
 							24, 3),
+	DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3),
 
 	DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3),
 	DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 8183d1c237d9..15508adcdfde 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -173,8 +173,10 @@
 /* mux clocks */
 #define CLK_MOUT_HDMI		1024
 #define CLK_MOUT_GPLL		1025
+#define CLK_MOUT_ACLK200_DISP1_SUB	1026
+#define CLK_MOUT_ACLK300_DISP1_SUB	1027
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS		1026
+#define CLK_NR_CLKS		1028
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
-- 
2.5.0

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#1248257 — Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

On 15.10.2015 19:31, Tomeu Vizoso wrote:
> When the DISP1 power domain is powered off, there's two clocks that need
> to be temporarily reparented to OSC, and back to their original parents
> when the domain is powered on again.
> 
> We expose these two clocks in the DT bindings so that the DT node of the
> power domain can reference them.
> 
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
> 
> Changes in v2:
> - Reuse mout_aclk200_p
> - Rename div_aclk300 as div_aclk300_disp
> 
>  drivers/clk/samsung/clk-exynos5250.c   | 14 +++++++++++++-
>  include/dt-bindings/clock/exynos5250.h |  4 +++-
>  2 files changed, 16 insertions(+), 2 deletions(-)
> 

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof


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#1248713 — Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

Quoting Krzysztof Kozlowski (2015-10-15 16:46:27)
> On 15.10.2015 19:31, Tomeu Vizoso wrote:
> > When the DISP1 power domain is powered off, there's two clocks that need
> > to be temporarily reparented to OSC, and back to their original parents
> > when the domain is powered on again.
> > 
> > We expose these two clocks in the DT bindings so that the DT node of the
> > power domain can reference them.
> > 
> > Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> > Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> > ---
> > 
> > Changes in v2:
> > - Reuse mout_aclk200_p
> > - Rename div_aclk300 as div_aclk300_disp
> > 
> >  drivers/clk/samsung/clk-exynos5250.c   | 14 +++++++++++++-
> >  include/dt-bindings/clock/exynos5250.h |  4 +++-
> >  2 files changed, 16 insertions(+), 2 deletions(-)
> > 
> 
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Applied to clk-next.

Regards,
Mike

> 
> Best regards,
> Krzysztof
> 
> 
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#1249017 — Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

On 10/16, Michael Turquette wrote:
> Quoting Krzysztof Kozlowski (2015-10-15 16:46:27)
> > On 15.10.2015 19:31, Tomeu Vizoso wrote:
> > > When the DISP1 power domain is powered off, there's two clocks that need
> > > to be temporarily reparented to OSC, and back to their original parents
> > > when the domain is powered on again.
> > > 
> > > We expose these two clocks in the DT bindings so that the DT node of the
> > > power domain can reference them.
> > > 
> > > Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> > > Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> > > ---
> > > 
> > > Changes in v2:
> > > - Reuse mout_aclk200_p
> > > - Rename div_aclk300 as div_aclk300_disp
> > > 
> > >  drivers/clk/samsung/clk-exynos5250.c   | 14 +++++++++++++-
> > >  include/dt-bindings/clock/exynos5250.h |  4 +++-
> > >  2 files changed, 16 insertions(+), 2 deletions(-)
> > > 
> > 
> > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> 
> Applied to clk-next.
> 

I think Tomeu wanted to take this through arm-soc? Otherwise
we'll need to provide a stable branch for the dt header.

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#1249073 — Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

On 16 October 2015 at 19:26, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 10/16, Michael Turquette wrote:
>> Quoting Krzysztof Kozlowski (2015-10-15 16:46:27)
>> > On 15.10.2015 19:31, Tomeu Vizoso wrote:
>> > > When the DISP1 power domain is powered off, there's two clocks that need
>> > > to be temporarily reparented to OSC, and back to their original parents
>> > > when the domain is powered on again.
>> > >
>> > > We expose these two clocks in the DT bindings so that the DT node of the
>> > > power domain can reference them.
>> > >
>> > > Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>> > > Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>> > > ---
>> > >
>> > > Changes in v2:
>> > > - Reuse mout_aclk200_p
>> > > - Rename div_aclk300 as div_aclk300_disp
>> > >
>> > >  drivers/clk/samsung/clk-exynos5250.c   | 14 +++++++++++++-
>> > >  include/dt-bindings/clock/exynos5250.h |  4 +++-
>> > >  2 files changed, 16 insertions(+), 2 deletions(-)
>> > >
>> >
>> > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>
>> Applied to clk-next.
>>
>
> I think Tomeu wanted to take this through arm-soc? Otherwise
> we'll need to provide a stable branch for the dt header.

Hi, Stephen is right, the second patch depends on this one.

Thanks,

Tomeu

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#1249219 — Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

On 10/17/15 03:56, Tomeu Vizoso wrote:
> On 16 October 2015 at 19:26, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> On 10/16, Michael Turquette wrote:
>>> Quoting Krzysztof Kozlowski (2015-10-15 16:46:27)
>>>> On 15.10.2015 19:31, Tomeu Vizoso wrote:
>>>>> When the DISP1 power domain is powered off, there's two clocks that need
>>>>> to be temporarily reparented to OSC, and back to their original parents
>>>>> when the domain is powered on again.
>>>>>
>>>>> We expose these two clocks in the DT bindings so that the DT node of the
>>>>> power domain can reference them.
>>>>>
>>>>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>>>>> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>>>>> ---
>>>>>
>>>>> Changes in v2:
>>>>> - Reuse mout_aclk200_p
>>>>> - Rename div_aclk300 as div_aclk300_disp
>>>>>
>>>>>  drivers/clk/samsung/clk-exynos5250.c   | 14 +++++++++++++-
>>>>>  include/dt-bindings/clock/exynos5250.h |  4 +++-
>>>>>  2 files changed, 16 insertions(+), 2 deletions(-)
>>>>>
>>>>
>>>> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>>
>>> Applied to clk-next.
>>>
>>
>> I think Tomeu wanted to take this through arm-soc? Otherwise
>> we'll need to provide a stable branch for the dt header.
> 
> Hi, Stephen is right, the second patch depends on this one.
> 
So...how can I take 2nd patch of this series in samsung(arm-soc) tree?
And this series shouldn't be for fixes for 4.3?...Mike how do you think?

Thanks,
Kukjin
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#1249287 — Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

2015-10-17 8:41 GMT+09:00 Kukjin Kim <kgene@kernel.org>:
> On 10/17/15 03:56, Tomeu Vizoso wrote:
>> On 16 October 2015 at 19:26, Stephen Boyd <sboyd@codeaurora.org> wrote:
>>> On 10/16, Michael Turquette wrote:
>>>> Quoting Krzysztof Kozlowski (2015-10-15 16:46:27)
>>>>> On 15.10.2015 19:31, Tomeu Vizoso wrote:
>>>>>> When the DISP1 power domain is powered off, there's two clocks that need
>>>>>> to be temporarily reparented to OSC, and back to their original parents
>>>>>> when the domain is powered on again.
>>>>>>
>>>>>> We expose these two clocks in the DT bindings so that the DT node of the
>>>>>> power domain can reference them.
>>>>>>
>>>>>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>>>>>> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
>>>>>> ---
>>>>>>
>>>>>> Changes in v2:
>>>>>> - Reuse mout_aclk200_p
>>>>>> - Rename div_aclk300 as div_aclk300_disp
>>>>>>
>>>>>>  drivers/clk/samsung/clk-exynos5250.c   | 14 +++++++++++++-
>>>>>>  include/dt-bindings/clock/exynos5250.h |  4 +++-
>>>>>>  2 files changed, 16 insertions(+), 2 deletions(-)
>>>>>>
>>>>>
>>>>> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
>>>>
>>>> Applied to clk-next.
>>>>
>>>
>>> I think Tomeu wanted to take this through arm-soc? Otherwise
>>> we'll need to provide a stable branch for the dt header.
>>
>> Hi, Stephen is right, the second patch depends on this one.
>>
> So...how can I take 2nd patch of this series in samsung(arm-soc) tree?
> And this series shouldn't be for fixes for 4.3?...Mike how do you think?

Stephen acked it so I thought everything will go through samsung-soc.

Dear Kukjin,
Indeed this can go as fix for current cycle... but in the same time
this does not fix any specific regression. Tomeu did not describe when
issue happened for the first time so I assumed it was like that
always. It's up to you.

Both patches (with Stephen's ack) are in my recent pull request but as
usual feel free to cherry pick. I'll drop them from next branch then.

Best regards,
Krzysztof
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#1249297 — Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

Hello Krzysztof,

On 10/17/2015 10:53 AM, Krzysztof Kozlowski wrote:
> 2015-10-17 8:41 GMT+09:00 Kukjin Kim <kgene@kernel.org>:

[snip]

>>>
>> So...how can I take 2nd patch of this series in samsung(arm-soc) tree?
>> And this series shouldn't be for fixes for 4.3?...Mike how do you think?
> 
> Stephen acked it so I thought everything will go through samsung-soc.
> 
> Dear Kukjin,
> Indeed this can go as fix for current cycle... but in the same time
> this does not fix any specific regression. Tomeu did not describe when
> issue happened for the first time so I assumed it was like that
> always. It's up to you.
>

Sorry for not answering about this series before but I've been in contact
with Tomeu over IRC before he posted it and since you already added your
Reviewed-by tag, I didn't feel the need do to it.

This is a regression for 4.3 since S2R was working correctly for 4.2 in
Snow, I tested after fixing resume with commit 6fd4899a54a5 ("irqchip:
exynos-combiner: Save IRQ enable set on suspend") and the display was
always enabled on resume.

I don't have access to a Snow anymore to bisect but I think the regression
was introduced by some of the changes in 4.3 to migrate the Exynos DRM to
Atomic Mode Settings. But probably that just exposed a latent bug and it
was working out of luck since I had the same issue than Tomeu in Exynos5420
and was fixed in the same way with commits:

885601002998 ("clk: exynos5420: Add IDs for clocks used in DISP1 power domain")
ea08de16eb1b ("ARM: dts: Add DISP1 power domain for exynos5420")

> Both patches (with Stephen's ack) are in my recent pull request but as
> usual feel free to cherry pick. I'll drop them from next branch then.
> 
> Best regards,
> Krzysztof
> --

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
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#1249299 — Re: [PATCH v2 1/2] clk: samsung: exynos5250: Add DISP1 clocks

2015-10-17 18:55 GMT+09:00 Javier Martinez Canillas <javier@osg.samsung.com>:
> Hello Krzysztof,
>
> On 10/17/2015 10:53 AM, Krzysztof Kozlowski wrote:
>> 2015-10-17 8:41 GMT+09:00 Kukjin Kim <kgene@kernel.org>:
>
> [snip]
>
>>>>
>>> So...how can I take 2nd patch of this series in samsung(arm-soc) tree?
>>> And this series shouldn't be for fixes for 4.3?...Mike how do you think?
>>
>> Stephen acked it so I thought everything will go through samsung-soc.
>>
>> Dear Kukjin,
>> Indeed this can go as fix for current cycle... but in the same time
>> this does not fix any specific regression. Tomeu did not describe when
>> issue happened for the first time so I assumed it was like that
>> always. It's up to you.
>>
>
> Sorry for not answering about this series before but I've been in contact
> with Tomeu over IRC before he posted it and since you already added your
> Reviewed-by tag, I didn't feel the need do to it.
>
> This is a regression for 4.3 since S2R was working correctly for 4.2 in
> Snow, I tested after fixing resume with commit 6fd4899a54a5 ("irqchip:
> exynos-combiner: Save IRQ enable set on suspend") and the display was
> always enabled on resume.

Hmmm, that means the patchset indeed should go as fixes.

Thanks for details,
Krzysztof
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#1247655 — [PATCH v2 2/2] ARM: dts: exynos5250: Add clocks to DISP1 domain

Adds to the node of the DISP1 power domain the two clocks that need to
be reparented while the domain is powered off:
CLK_MOUT_ACLK200_DISP1_SUB and CLK_MOUT_ACLK300_DISP1_SUB.

Otherwise the state is unknown at power up and the mixer's clocks are
all messed up.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Link: http://lkml.kernel.org/g/561CDC33.7050103@collabora.com
---


 arch/arm/boot/dts/exynos5250.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b24610ea8c2a..88b9cf5f226f 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -130,6 +130,10 @@
 		compatible = "samsung,exynos4210-pd";
 		reg = <0x100440A0 0x20>;
 		#power-domain-cells = <0>;
+		clocks = <&clock CLK_FIN_PLL>,
+			 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
+			 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
+		clock-names = "oscclk", "clk0", "clk1";
 	};
 
 	clock: clock-controller@10010000 {
-- 
2.5.0

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#1248260 — Re: [PATCH v2 2/2] ARM: dts: exynos5250: Add clocks to DISP1 domain

On 15.10.2015 19:31, Tomeu Vizoso wrote:
> Adds to the node of the DISP1 power domain the two clocks that need to
> be reparented while the domain is powered off:
> CLK_MOUT_ACLK200_DISP1_SUB and CLK_MOUT_ACLK300_DISP1_SUB.
> 
> Otherwise the state is unknown at power up and the mixer's clocks are
> all messed up.
> 
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> Link: http://lkml.kernel.org/g/561CDC33.7050103@collabora.com
> ---
> 
> 
>  arch/arm/boot/dts/exynos5250.dtsi | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index b24610ea8c2a..88b9cf5f226f 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -130,6 +130,10 @@
>  		compatible = "samsung,exynos4210-pd";
>  		reg = <0x100440A0 0x20>;
>  		#power-domain-cells = <0>;
> +		clocks = <&clock CLK_FIN_PLL>,
> +			 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
> +			 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
> +		clock-names = "oscclk", "clk0", "clk1";
>  	};
>  
>  	clock: clock-controller@10010000 {
> 

I reviewed it already. Any changes here since v1?

Best regards,
Krzysztof

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#1248453 — Re: [PATCH v2 2/2] ARM: dts: exynos5250: Add clocks to DISP1 domain

On 10/16/2015 01:44 AM, Krzysztof Kozlowski wrote:
> On 15.10.2015 19:31, Tomeu Vizoso wrote:
>> Adds to the node of the DISP1 power domain the two clocks that need to
>> be reparented while the domain is powered off:
>> CLK_MOUT_ACLK200_DISP1_SUB and CLK_MOUT_ACLK300_DISP1_SUB.
>>
>> Otherwise the state is unknown at power up and the mixer's clocks are
>> all messed up.
>>
>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>> Link: http://lkml.kernel.org/g/561CDC33.7050103@collabora.com
>> ---
>>
>>
>>  arch/arm/boot/dts/exynos5250.dtsi | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
>> index b24610ea8c2a..88b9cf5f226f 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -130,6 +130,10 @@
>>  		compatible = "samsung,exynos4210-pd";
>>  		reg = <0x100440A0 0x20>;
>>  		#power-domain-cells = <0>;
>> +		clocks = <&clock CLK_FIN_PLL>,
>> +			 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
>> +			 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
>> +		clock-names = "oscclk", "clk0", "clk1";
>>  	};
>>  
>>  	clock: clock-controller@10010000 {
>>
> 
> I reviewed it already. Any changes here since v1?

No, I just forgot to add your r-b tag, sorry about that.

Thanks,

Tomeu

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