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Groups > linux.kernel > #1246586 > unrolled thread
| Started by | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| First post | 2015-10-14 13:50 +0200 |
| Last post | 2015-10-15 09:20 +0200 |
| Articles | 15 — 2 participants |
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[PATCH v5 00/24] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
[PATCH v5 22/24] dmaengine: edma: Read channel mapping support only once from HW Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
[PATCH v5 19/24] dmaengine: edma: Simplify the interrupt handling Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
[PATCH v5 05/24] ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine driver Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
[PATCH v5 15/24] dmaengine: edma: Use dev_dbg instead pr_debug Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
[PATCH v5 21/24] dmaengine: edma: Simplify and optimize ccerr interrupt handler Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
[PATCH v5 13/24] dmaengine: edma: Use devm_kcalloc when possible Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
[PATCH v5 24/24] dmaengine: edma: Dynamic paRAM slot handling if HW supports it Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
[PATCH v5 10/24] ARM: davinci: Add dma_mask to eDMA devices Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
[PATCH v5 08/24] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
[PATCH v5 07/24] ARM/dmaengine: edma: Public API to use private struct pointer Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
[PATCH v5 02/24] ARM: common: edma: Remove unused functions Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
[PATCH v5 12/24] dmaengine: edma: Allocate memory dynamically for bitmaps and structures Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
Re: [PATCH v5 00/24] dmaengine/ARM: Merge the edma drivers into one Vinod Koul <vinod.koul@intel.com> - 2015-10-14 16:30 +0200
Re: [PATCH v5 00/24] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-15 09:20 +0200
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 13:50 +0200 |
| Subject | [PATCH v5 00/24] dmaengine/ARM: Merge the edma drivers into one |
| Message-ID | <qjsJb-5OD-3@gated-at.bofh.it> |
Hi,
Changes since v4:
- checkpatch errors/warnings/checks has been fixed in spot and not in a followup
patch.
- Sekhar's Acked-by added to patches touching arch/arm/mach-davinci/
- Other comments for v4 has been addressed
Changes since v3:
- Separated the two (patch 10/11 in v2 patch 10 in v3) patch which got squashed
by accident for v3
- Added Tony's Acked-by to patch 11 (for mach-oamp2 part)
Changes since v2:
- devm_kasprintf format string fixed
- Additional patch to enable dynamic paRAM slot usage when the channel mapping
is supported by the eDMA module.
On am335x we have 256 paRAM slots and 64 DMA channels, this means that we had
64 slots 'locked away' all the time. The dynamic paRAM slot logic will allow
us to use all 256 slots freely for any purpose.
Changes since v1:
- Convert edma platform device registration to use platform_device_register_full
- Moved the PM callback also to the dmaengine driver - missed in v1
- Commit message added to:
ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers
- New patch which reads the flag for the channel mapping support in one place
Cover letter:
with this series the edma two driver setup will be changed to have only one
driver to support eDMA3. The legacy edma interface will be removed and eDMA can
only be used via dmaengine API from this point on.
In order to do the merge the following improvements has been done:
- One driver instance per eDMA:
- Any number of eDMA instances are supported (both legacy and DT boot)
- Not relying on global variables, arrays, etc
- Code simplification and optimizations in several places
This change will also help us to do bigger changes in the eDMA driver since,
since now we have only one driver to work with.
The series has been tested on:
da850-evm (OMAP-L138)
- with legacy and DT boot (both eDMA0 and eDMA1 is enabled)
- In code swapping the eDMA instances in legacy mode to make sure the second
instance is handled correctly.
am335x-evmsk
- DT boot
I think this series could go via the dmaengine tree. Changes are trivial under
arch/arm/
Regards,
Peter
---
Peter Ujfalusi (24):
ARM: common: edma: Fix channel parameter for irq callbacks
ARM: common: edma: Remove unused functions
dmaengine: edma: Simplify and optimize the edma_execute path
ARM: davinci/common: Convert edma driver to handle one eDMA instance
per driver
ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine
driver
ARM: common: edma: Internal API to use pointer to 'struct edma'
ARM/dmaengine: edma: Public API to use private struct pointer
ARM/dmaengine: edma: Remove limitation on the number of eDMA
controllers
ARM: davinci: Use platform_device_register_full() to create pdev for
eDMA
ARM: davinci: Add dma_mask to eDMA devices
ARM/dmaengine: edma: Merge the two drivers under drivers/dma/
dmaengine: edma: Allocate memory dynamically for bitmaps and
structures
dmaengine: edma: Use devm_kcalloc when possible
dmaengine: edma: Cleanup regarding the use of dev around the code
dmaengine: edma: Use dev_dbg instead pr_debug
dmaengine: edma: Use the edma_write_slot instead open coded
memcpy_toio
dmaengine: edma: Print warning when linking slots from different eDMA
dmaengine: edma: Consolidate the comments for functions
dmaengine: edma: Simplify the interrupt handling
dmaengine: edma: Move the pending error check into helper function
dmaengine: edma: Simplify and optimize ccerr interrupt handler
dmaengine: edma: Read channel mapping support only once from HW
dmaengine: edma: Rename bitfields for slot and channel usage tracking
dmaengine: edma: Dynamic paRAM slot handling if HW supports it
arch/arm/Kconfig | 1 -
arch/arm/common/Kconfig | 3 -
arch/arm/common/Makefile | 1 -
arch/arm/common/edma.c | 1876 ---------------------------------
arch/arm/mach-davinci/devices-da8xx.c | 122 +--
arch/arm/mach-davinci/dm355.c | 40 +-
arch/arm/mach-davinci/dm365.c | 25 +-
arch/arm/mach-davinci/dm644x.c | 40 +-
arch/arm/mach-davinci/dm646x.c | 44 +-
arch/arm/mach-omap2/Kconfig | 1 -
drivers/dma/Kconfig | 1 -
drivers/dma/edma.c | 1631 ++++++++++++++++++++++++----
include/linux/platform_data/edma.h | 101 --
13 files changed, 1566 insertions(+), 2320 deletions(-)
delete mode 100644 arch/arm/common/edma.c
--
2.6.1
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 13:50 +0200 |
| Subject | [PATCH v5 22/24] dmaengine: edma: Read channel mapping support only once from HW |
| Message-ID | <qjsJd-5OD-49@gated-at.bofh.it> |
| In reply to | #1246586 |
Instead of directly reading it from CCCFG register take the information out
once when we set up the configuration from the HW.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index d105d1ae0f13..4b2ccc9de0ad 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -223,6 +223,7 @@ struct edma_cc {
unsigned num_region;
unsigned num_slots;
unsigned num_tc;
+ bool chmap_exist;
enum dma_event_q default_queue;
bool unused_chan_list_done;
@@ -1930,11 +1931,14 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
value = GET_NUM_EVQUE(cccfg);
ecc->num_tc = value + 1;
+ ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
+
dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
dev_dbg(dev, "num_region: %u\n", ecc->num_region);
dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
+ dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
/* Nothing need to be done if queue priority is provided */
if (pdata->queue_priority_mapping)
@@ -2223,7 +2227,7 @@ static int edma_probe(struct platform_device *pdev)
queue_priority_mapping[i][1]);
/* Map the channel to param entry if channel mapping logic exist */
- if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST)
+ if (ecc->chmap_exist)
edma_direct_dmach_to_param_mapping(ecc);
for (i = 0; i < ecc->num_region; i++) {
@@ -2293,7 +2297,7 @@ static int edma_pm_resume(struct device *dev)
queue_priority_mapping[i][1]);
/* Map the channel to param entry if channel mapping logic */
- if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST)
+ if (ecc->chmap_exist)
edma_direct_dmach_to_param_mapping(ecc);
for (i = 0; i < ecc->num_channels; i++) {
--
2.6.1
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 13:50 +0200 |
| Subject | [PATCH v5 19/24] dmaengine: edma: Simplify the interrupt handling |
| Message-ID | <qjsJd-5OD-53@gated-at.bofh.it> |
| In reply to | #1246586 |
With the merger of the arch/arm/common/edma.c code into the dmaengine
driver, there is no longer need to have per channel callback/data storage
for interrupt events.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 450 ++++++++++++++++++++++++-----------------------------
1 file changed, 205 insertions(+), 245 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 6bcbdceb3dc2..daa94a4bbe11 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -154,12 +154,6 @@ struct edmacc_param {
#define TCCHEN BIT(22)
#define ITCCHEN BIT(23)
-/*ch_status parameter of callback function possible values*/
-#define EDMA_DMA_COMPLETE 1
-#define EDMA_DMA_CC_ERROR 2
-#define EDMA_DMA_TC1_ERROR 3
-#define EDMA_DMA_TC2_ERROR 4
-
struct edma_pset {
u32 len;
dma_addr_t addr;
@@ -243,12 +237,6 @@ struct edma_cc {
*/
unsigned long *edma_unused;
- struct dma_interrupt_data {
- void (*callback)(unsigned channel, unsigned short ch_status,
- void *data);
- void *data;
- } *intr_data;
-
struct dma_device dma_slave;
struct edma_chan *slave_chans;
int dummy_slot;
@@ -486,24 +474,18 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
return 0;
}
-static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data)
+static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, bool enable)
{
lch = EDMA_CHAN_SLOT(lch);
- if (!callback)
- edma_shadow0_write_array(ecc, SH_IECR, lch >> 5,
- BIT(lch & 0x1f));
-
- ecc->intr_data[lch].callback = callback;
- ecc->intr_data[lch].data = data;
-
- if (callback) {
+ if (enable) {
edma_shadow0_write_array(ecc, SH_ICR, lch >> 5,
BIT(lch & 0x1f));
edma_shadow0_write_array(ecc, SH_IESR, lch >> 5,
BIT(lch & 0x1f));
+ } else {
+ edma_shadow0_write_array(ecc, SH_IECR, lch >> 5,
+ BIT(lch & 0x1f));
}
}
@@ -795,8 +777,6 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
* edma_alloc_channel - allocate DMA channel and paired parameter RAM
* @ecc: pointer to edma_cc struct
* @channel: specific channel to allocate; negative for "any unmapped channel"
- * @callback: optional; to be issued on DMA completion or errors
- * @data: passed to callback
* @eventq_no: an EVENTQ_* constant, used to choose which Transfer
* Controller (TC) executes requests using this channel. Use
* EVENTQ_DEFAULT unless you really need a high priority queue.
@@ -823,9 +803,7 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
* Returns the number of the channel, else negative errno.
*/
static int edma_alloc_channel(struct edma_cc *ecc, int channel,
- void (*callback)(unsigned channel, u16 ch_status, void *data),
- void *data,
- enum dma_event_q eventq_no)
+ enum dma_event_q eventq_no)
{
unsigned done = 0;
int ret = 0;
@@ -881,9 +859,7 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel,
edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel));
edma_write_slot(ecc, channel, &dummy_paramset);
- if (callback)
- edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel),
- callback, data);
+ edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true);
edma_map_dmach_to_queue(ecc, channel, eventq_no);
@@ -914,7 +890,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
if (channel >= ecc->num_channels)
return;
- edma_setup_interrupt(ecc, channel, NULL, NULL);
+ edma_setup_interrupt(ecc, channel, false);
/* REVISIT should probably take out of shadow region 0 */
edma_write_slot(ecc, channel, &dummy_paramset);
@@ -944,148 +920,6 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
edma_map_dmach_to_queue(ecc, channel, eventq_no);
}
-/* eDMA interrupt handler */
-static irqreturn_t dma_irq_handler(int irq, void *data)
-{
- struct edma_cc *ecc = data;
- int ctlr;
- u32 sh_ier;
- u32 sh_ipr;
- u32 bank;
-
- ctlr = ecc->id;
- if (ctlr < 0)
- return IRQ_NONE;
-
- dev_dbg(ecc->dev, "dma_irq_handler\n");
-
- sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
- if (!sh_ipr) {
- sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
- if (!sh_ipr)
- return IRQ_NONE;
- sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
- bank = 1;
- } else {
- sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
- bank = 0;
- }
-
- do {
- u32 slot;
- u32 channel;
-
- dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr);
-
- slot = __ffs(sh_ipr);
- sh_ipr &= ~(BIT(slot));
-
- if (sh_ier & BIT(slot)) {
- channel = (bank << 5) | slot;
- /* Clear the corresponding IPR bits */
- edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
- if (ecc->intr_data[channel].callback)
- ecc->intr_data[channel].callback(
- EDMA_CTLR_CHAN(ctlr, channel),
- EDMA_DMA_COMPLETE,
- ecc->intr_data[channel].data);
- }
- } while (sh_ipr);
-
- edma_shadow0_write(ecc, SH_IEVAL, 1);
- return IRQ_HANDLED;
-}
-
-/* eDMA error interrupt handler */
-static irqreturn_t dma_ccerr_handler(int irq, void *data)
-{
- struct edma_cc *ecc = data;
- int i;
- int ctlr;
- unsigned int cnt = 0;
-
- ctlr = ecc->id;
- if (ctlr < 0)
- return IRQ_NONE;
-
- dev_dbg(ecc->dev, "dma_ccerr_handler\n");
-
- if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
- (edma_read(ecc, EDMA_QEMR) == 0) &&
- (edma_read(ecc, EDMA_CCERR) == 0))
- return IRQ_NONE;
-
- while (1) {
- int j = -1;
-
- if (edma_read_array(ecc, EDMA_EMR, 0))
- j = 0;
- else if (edma_read_array(ecc, EDMA_EMR, 1))
- j = 1;
- if (j >= 0) {
- dev_dbg(ecc->dev, "EMR%d %08x\n", j,
- edma_read_array(ecc, EDMA_EMR, j));
- for (i = 0; i < 32; i++) {
- int k = (j << 5) + i;
-
- if (edma_read_array(ecc, EDMA_EMR, j) &
- BIT(i)) {
- /* Clear the corresponding EMR bits */
- edma_write_array(ecc, EDMA_EMCR, j,
- BIT(i));
- /* Clear any SER */
- edma_shadow0_write_array(ecc, SH_SECR,
- j, BIT(i));
- if (ecc->intr_data[k].callback) {
- ecc->intr_data[k].callback(
- EDMA_CTLR_CHAN(ctlr, k),
- EDMA_DMA_CC_ERROR,
- ecc->intr_data[k].data);
- }
- }
- }
- } else if (edma_read(ecc, EDMA_QEMR)) {
- dev_dbg(ecc->dev, "QEMR %02x\n",
- edma_read(ecc, EDMA_QEMR));
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_QEMCR, BIT(i));
- edma_shadow0_write(ecc, SH_QSECR,
- BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- } else if (edma_read(ecc, EDMA_CCERR)) {
- dev_dbg(ecc->dev, "CCERR %08x\n",
- edma_read(ecc, EDMA_CCERR));
- /* FIXME: CCERR.BIT(16) ignored! much better
- * to just write CCERRCLR with CCERR value...
- */
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_CCERRCLR, BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- }
- if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
- (edma_read(ecc, EDMA_QEMR) == 0) &&
- (edma_read(ecc, EDMA_CCERR) == 0))
- break;
- cnt++;
- if (cnt > 10)
- break;
- }
- edma_write(ecc, EDMA_EEVAL, 1);
- return IRQ_HANDLED;
-}
-
static inline struct edma_cc *to_edma_cc(struct dma_device *d)
{
return container_of(d, struct edma_cc, dma_slave);
@@ -1667,81 +1501,214 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}
-static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
+static void edma_completion_handler(struct edma_chan *echan)
{
- struct edma_chan *echan = data;
struct edma_cc *ecc = echan->ecc;
struct device *dev = echan->vchan.chan.device->dev;
- struct edma_desc *edesc;
- struct edmacc_param p;
+ struct edma_desc *edesc = echan->edesc;
- edesc = echan->edesc;
+ if (!edesc)
+ return;
spin_lock(&echan->vchan.lock);
- switch (ch_status) {
- case EDMA_DMA_COMPLETE:
- if (edesc) {
- if (edesc->cyclic) {
- vchan_cyclic_callback(&edesc->vdesc);
- goto out;
- } else if (edesc->processed == edesc->pset_nr) {
- dev_dbg(dev,
- "Transfer completed on channel %d\n",
- ch_num);
- edesc->residue = 0;
- edma_stop(ecc, echan->ch_num);
- vchan_cookie_complete(&edesc->vdesc);
- echan->edesc = NULL;
- } else {
- dev_dbg(dev,
- "Sub transfer completed on channel %d\n",
- ch_num);
-
- edma_pause(ecc, echan->ch_num);
-
- /* Update statistics for tx_status */
- edesc->residue -= edesc->sg_len;
- edesc->residue_stat = edesc->residue;
- edesc->processed_stat = edesc->processed;
- }
- edma_execute(echan);
+ if (edesc->cyclic) {
+ vchan_cyclic_callback(&edesc->vdesc);
+ spin_unlock(&echan->vchan.lock);
+ return;
+ } else if (edesc->processed == edesc->pset_nr) {
+ edesc->residue = 0;
+ edma_stop(ecc, echan->ch_num);
+ vchan_cookie_complete(&edesc->vdesc);
+ echan->edesc = NULL;
+
+ dev_dbg(dev, "Transfer completed on channel %d\n",
+ echan->ch_num);
+ } else {
+ dev_dbg(dev, "Sub transfer completed on channel %d\n",
+ echan->ch_num);
+
+ edma_pause(ecc, echan->ch_num);
+
+ /* Update statistics for tx_status */
+ edesc->residue -= edesc->sg_len;
+ edesc->residue_stat = edesc->residue;
+ edesc->processed_stat = edesc->processed;
+ }
+ edma_execute(echan);
+
+ spin_unlock(&echan->vchan.lock);
+}
+
+/* eDMA interrupt handler */
+static irqreturn_t dma_irq_handler(int irq, void *data)
+{
+ struct edma_cc *ecc = data;
+ int ctlr;
+ u32 sh_ier;
+ u32 sh_ipr;
+ u32 bank;
+
+ ctlr = ecc->id;
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_vdbg(ecc->dev, "dma_irq_handler\n");
+
+ sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
+ if (!sh_ipr) {
+ sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
+ if (!sh_ipr)
+ return IRQ_NONE;
+ sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
+ bank = 1;
+ } else {
+ sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
+ bank = 0;
+ }
+
+ do {
+ u32 slot;
+ u32 channel;
+
+ slot = __ffs(sh_ipr);
+ sh_ipr &= ~(BIT(slot));
+
+ if (sh_ier & BIT(slot)) {
+ channel = (bank << 5) | slot;
+ /* Clear the corresponding IPR bits */
+ edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
+ edma_completion_handler(&ecc->slave_chans[channel]);
}
- break;
- case EDMA_DMA_CC_ERROR:
- edma_read_slot(ecc, echan->slot[0], &p);
+ } while (sh_ipr);
+
+ edma_shadow0_write(ecc, SH_IEVAL, 1);
+ return IRQ_HANDLED;
+}
+
+static void edma_error_handler(struct edma_chan *echan)
+{
+ struct edma_cc *ecc = echan->ecc;
+ struct device *dev = echan->vchan.chan.device->dev;
+ struct edmacc_param p;
+
+ if (!echan->edesc)
+ return;
+
+ spin_lock(&echan->vchan.lock);
+ edma_read_slot(ecc, echan->slot[0], &p);
+ /*
+ * Issue later based on missed flag which will be sure
+ * to happen as:
+ * (1) we finished transmitting an intermediate slot and
+ * edma_execute is coming up.
+ * (2) or we finished current transfer and issue will
+ * call edma_execute.
+ *
+ * Important note: issuing can be dangerous here and
+ * lead to some nasty recursion when we are in a NULL
+ * slot. So we avoid doing so and set the missed flag.
+ */
+ if (p.a_b_cnt == 0 && p.ccnt == 0) {
+ dev_dbg(dev, "Error on null slot, setting miss\n");
+ echan->missed = 1;
+ } else {
/*
- * Issue later based on missed flag which will be sure
- * to happen as:
- * (1) we finished transmitting an intermediate slot and
- * edma_execute is coming up.
- * (2) or we finished current transfer and issue will
- * call edma_execute.
- *
- * Important note: issuing can be dangerous here and
- * lead to some nasty recursion when we are in a NULL
- * slot. So we avoid doing so and set the missed flag.
+ * The slot is already programmed but the event got
+ * missed, so its safe to issue it here.
*/
- if (p.a_b_cnt == 0 && p.ccnt == 0) {
- dev_dbg(dev, "Error on null slot, setting miss\n");
- echan->missed = 1;
- } else {
- /*
- * The slot is already programmed but the event got
- * missed, so its safe to issue it here.
+ dev_dbg(dev, "Missed event, TRIGGERING\n");
+ edma_clean_channel(ecc, echan->ch_num);
+ edma_stop(ecc, echan->ch_num);
+ edma_start(ecc, echan->ch_num);
+ edma_trigger_channel(ecc, echan->ch_num);
+ }
+ spin_unlock(&echan->vchan.lock);
+}
+
+/* eDMA error interrupt handler */
+static irqreturn_t dma_ccerr_handler(int irq, void *data)
+{
+ struct edma_cc *ecc = data;
+ int i;
+ int ctlr;
+ unsigned int cnt = 0;
+
+ ctlr = ecc->id;
+ if (ctlr < 0)
+ return IRQ_NONE;
+
+ dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
+
+ if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
+ (edma_read(ecc, EDMA_QEMR) == 0) &&
+ (edma_read(ecc, EDMA_CCERR) == 0))
+ return IRQ_NONE;
+
+ while (1) {
+ int j = -1;
+
+ if (edma_read_array(ecc, EDMA_EMR, 0))
+ j = 0;
+ else if (edma_read_array(ecc, EDMA_EMR, 1))
+ j = 1;
+ if (j >= 0) {
+ dev_dbg(ecc->dev, "EMR%d %08x\n", j,
+ edma_read_array(ecc, EDMA_EMR, j));
+ for (i = 0; i < 32; i++) {
+ int k = (j << 5) + i;
+
+ if (edma_read_array(ecc, EDMA_EMR, j) &
+ BIT(i)) {
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ecc, EDMA_EMCR, j,
+ BIT(i));
+ /* Clear any SER */
+ edma_shadow0_write_array(ecc, SH_SECR,
+ j, BIT(i));
+ edma_error_handler(&ecc->slave_chans[k]);
+ }
+ }
+ } else if (edma_read(ecc, EDMA_QEMR)) {
+ dev_dbg(ecc->dev, "QEMR %02x\n",
+ edma_read(ecc, EDMA_QEMR));
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ecc, EDMA_QEMCR, BIT(i));
+ edma_shadow0_write(ecc, SH_QSECR,
+ BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
+ } else if (edma_read(ecc, EDMA_CCERR)) {
+ dev_dbg(ecc->dev, "CCERR %08x\n",
+ edma_read(ecc, EDMA_CCERR));
+ /* FIXME: CCERR.BIT(16) ignored! much better
+ * to just write CCERRCLR with CCERR value...
*/
- dev_dbg(dev, "Missed event, TRIGGERING\n");
- edma_clean_channel(ecc, echan->ch_num);
- edma_stop(ecc, echan->ch_num);
- edma_start(ecc, echan->ch_num);
- edma_trigger_channel(ecc, echan->ch_num);
+ for (i = 0; i < 8; i++) {
+ if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
+ /* Clear the corresponding IPR bits */
+ edma_write(ecc, EDMA_CCERRCLR, BIT(i));
+
+ /* NOTE: not reported!! */
+ }
+ }
}
- break;
- default:
- break;
+ if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
+ (edma_read(ecc, EDMA_QEMR) == 0) &&
+ (edma_read(ecc, EDMA_CCERR) == 0))
+ break;
+ cnt++;
+ if (cnt > 10)
+ break;
}
-out:
- spin_unlock(&echan->vchan.lock);
+ edma_write(ecc, EDMA_EEVAL, 1);
+ return IRQ_HANDLED;
}
/* Alloc channel resources */
@@ -1753,8 +1720,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
int a_ch_num;
LIST_HEAD(descs);
- a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num,
- edma_callback, echan, EVENTQ_DEFAULT);
+ a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, EVENTQ_DEFAULT);
if (a_ch_num < 0) {
ret = -ENODEV;
@@ -2175,11 +2141,6 @@ static int edma_probe(struct platform_device *pdev)
if (!ecc->slave_chans)
return -ENOMEM;
- ecc->intr_data = devm_kcalloc(dev, ecc->num_channels,
- sizeof(*ecc->intr_data), GFP_KERNEL);
- if (!ecc->intr_data)
- return -ENOMEM;
-
ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels),
sizeof(unsigned long), GFP_KERNEL);
if (!ecc->edma_unused)
@@ -2350,8 +2311,7 @@ static int edma_pm_resume(struct device *dev)
BIT(i & 0x1f));
edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i),
- ecc->intr_data[i].callback,
- ecc->intr_data[i].data);
+ true);
}
}
--
2.6.1
--
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 13:50 +0200 |
| Subject | [PATCH v5 05/24] ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine driver |
| Message-ID | <qjsJd-5OD-51@gated-at.bofh.it> |
| In reply to | #1246586 |
If the of_dma_controller is registered in the non dmaengine driver we could
have race condition:
the of_dma_controller has been registered, but the dmaengine driver is not
yet probed. Drivers requesting DMA channels during this window will fail
since we do not yet have dmaengine drivers registered.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 10 ----------
drivers/dma/edma.c | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 7c2fe527e53b..d82fceda13a3 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -29,7 +29,6 @@
#include <linux/dma-mapping.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
-#include <linux/of_dma.h>
#include <linux/of_irq.h>
#include <linux/pm_runtime.h>
@@ -1191,10 +1190,6 @@ static int edma_of_parse_dt(struct device *dev,
return ret;
}
-static struct of_dma_filter_info edma_filter_info = {
- .filter_fn = edma_filter_fn,
-};
-
static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
struct device_node *node)
{
@@ -1209,11 +1204,6 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
if (ret)
return ERR_PTR(ret);
- dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
- dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
- of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
- &edma_filter_info);
-
return info;
}
#else
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 19fa49d6f555..fcb4680efed7 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -25,6 +25,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/of.h>
+#include <linux/of_dma.h>
#include <linux/platform_data/edma.h>
@@ -987,9 +988,14 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
INIT_LIST_HEAD(&dma->channels);
}
+static struct of_dma_filter_info edma_filter_info = {
+ .filter_fn = edma_filter_fn,
+};
+
static int edma_probe(struct platform_device *pdev)
{
struct edma_cc *ecc;
+ struct device_node *parent_node = pdev->dev.parent->of_node;
int ret;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
@@ -1024,6 +1030,13 @@ static int edma_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ecc);
+ if (parent_node) {
+ dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
+ dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
+ of_dma_controller_register(parent_node, of_dma_simple_xlate,
+ &edma_filter_info);
+ }
+
dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
return 0;
@@ -1037,7 +1050,10 @@ static int edma_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct edma_cc *ecc = dev_get_drvdata(dev);
+ struct device_node *parent_node = pdev->dev.parent->of_node;
+ if (parent_node)
+ of_dma_controller_free(parent_node);
dma_async_device_unregister(&ecc->dma_slave);
edma_free_slot(ecc->dummy_slot);
--
2.6.1
--
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 13:50 +0200 |
| Subject | [PATCH v5 15/24] dmaengine: edma: Use dev_dbg instead pr_debug |
| Message-ID | <qjsJd-5OD-55@gated-at.bofh.it> |
| In reply to | #1246586 |
We have access to dev, so it is better to use the dev_dbg for debug prints.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index a9fe5c92451d..08f9bd0aa0b3 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -676,23 +676,23 @@ static int edma_start(struct edma_cc *ecc, unsigned channel)
/* EDMA channels without event association */
if (test_bit(channel, ecc->edma_unused)) {
- pr_debug("EDMA: ESR%d %08x\n", j,
- edma_shadow0_read_array(ecc, SH_ESR, j));
+ dev_dbg(ecc->dev, "ESR%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_ESR, j));
edma_shadow0_write_array(ecc, SH_ESR, j, mask);
return 0;
}
/* EDMA channel with event association */
- pr_debug("EDMA: ER%d %08x\n", j,
- edma_shadow0_read_array(ecc, SH_ER, j));
+ dev_dbg(ecc->dev, "ER%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_ER, j));
/* Clear any pending event or error */
edma_write_array(ecc, EDMA_ECR, j, mask);
edma_write_array(ecc, EDMA_EMCR, j, mask);
/* Clear any SER */
edma_shadow0_write_array(ecc, SH_SECR, j, mask);
edma_shadow0_write_array(ecc, SH_EESR, j, mask);
- pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ecc, SH_EER, j));
+ dev_dbg(ecc->dev, "EER%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_EER, j));
return 0;
}
@@ -730,8 +730,8 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel)
/* clear possibly pending completion interrupt */
edma_shadow0_write_array(ecc, SH_ICR, j, mask);
- pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ecc, SH_EER, j));
+ dev_dbg(ecc->dev, "EER%d %08x\n", j,
+ edma_shadow0_read_array(ecc, SH_EER, j));
/* REVISIT: consider guarding against inappropriate event
* chaining by overwriting with dummy_paramset.
@@ -800,8 +800,8 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel)
edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
- pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
- edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
+ dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
+ edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
return 0;
}
@@ -831,8 +831,8 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
int j = (channel >> 5);
unsigned int mask = BIT(channel & 0x1f);
- pr_debug("EDMA: EMR%d %08x\n", j,
- edma_read_array(ecc, EDMA_EMR, j));
+ dev_dbg(ecc->dev, "EMR%d %08x\n", j,
+ edma_read_array(ecc, EDMA_EMR, j));
edma_shadow0_write_array(ecc, SH_ECR, j, mask);
/* Clear the corresponding EMR bits */
edma_write_array(ecc, EDMA_EMCR, j, mask);
--
2.6.1
--
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 13:50 +0200 |
| Subject | [PATCH v5 21/24] dmaengine: edma: Simplify and optimize ccerr interrupt handler |
| Message-ID | <qjsJd-5OD-59@gated-at.bofh.it> |
| In reply to | #1246586 |
No need to run through the bits in QEMR and CCERR events since they will
not trigger any action, so just clearing the errors there is fine.
In case of the missed event the loop can be optimized so we spend less time
to handle the event.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 82 +++++++++++++++++++++++-------------------------------
1 file changed, 35 insertions(+), 47 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 84b98a01993a..d105d1ae0f13 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -1640,9 +1640,10 @@ static inline bool edma_error_pending(struct edma_cc *ecc)
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
struct edma_cc *ecc = data;
- int i;
+ int i, j;
int ctlr;
unsigned int cnt = 0;
+ unsigned int val;
ctlr = ecc->id;
if (ctlr < 0)
@@ -1654,57 +1655,44 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
return IRQ_NONE;
while (1) {
- int j = -1;
-
- if (edma_read_array(ecc, EDMA_EMR, 0))
- j = 0;
- else if (edma_read_array(ecc, EDMA_EMR, 1))
- j = 1;
- if (j >= 0) {
- dev_dbg(ecc->dev, "EMR%d %08x\n", j,
- edma_read_array(ecc, EDMA_EMR, j));
- for (i = 0; i < 32; i++) {
+ /* Event missed register(s) */
+ for (j = 0; j < 2; j++) {
+ unsigned long emr;
+
+ val = edma_read_array(ecc, EDMA_EMR, j);
+ if (!val)
+ continue;
+
+ dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
+ emr = val;
+ for (i = find_next_bit(&emr, 32, 0); i < 32;
+ i = find_next_bit(&emr, 32, i + 1)) {
int k = (j << 5) + i;
- if (edma_read_array(ecc, EDMA_EMR, j) &
- BIT(i)) {
- /* Clear the corresponding EMR bits */
- edma_write_array(ecc, EDMA_EMCR, j,
+ /* Clear the corresponding EMR bits */
+ edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
+ /* Clear any SER */
+ edma_shadow0_write_array(ecc, SH_SECR, j,
BIT(i));
- /* Clear any SER */
- edma_shadow0_write_array(ecc, SH_SECR,
- j, BIT(i));
- edma_error_handler(&ecc->slave_chans[k]);
- }
- }
- } else if (edma_read(ecc, EDMA_QEMR)) {
- dev_dbg(ecc->dev, "QEMR %02x\n",
- edma_read(ecc, EDMA_QEMR));
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_QEMCR, BIT(i));
- edma_shadow0_write(ecc, SH_QSECR,
- BIT(i));
-
- /* NOTE: not reported!! */
- }
- }
- } else if (edma_read(ecc, EDMA_CCERR)) {
- dev_dbg(ecc->dev, "CCERR %08x\n",
- edma_read(ecc, EDMA_CCERR));
- /* FIXME: CCERR.BIT(16) ignored! much better
- * to just write CCERRCLR with CCERR value...
- */
- for (i = 0; i < 8; i++) {
- if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
- /* Clear the corresponding IPR bits */
- edma_write(ecc, EDMA_CCERRCLR, BIT(i));
-
- /* NOTE: not reported!! */
- }
+ edma_error_handler(&ecc->slave_chans[k]);
}
}
+
+ val = edma_read(ecc, EDMA_QEMR);
+ if (val) {
+ dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
+ /* Not reported, just clear the interrupt reason. */
+ edma_write(ecc, EDMA_QEMCR, val);
+ edma_shadow0_write(ecc, SH_QSECR, val);
+ }
+
+ val = edma_read(ecc, EDMA_CCERR);
+ if (val) {
+ dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
+ /* Not reported, just clear the interrupt reason. */
+ edma_write(ecc, EDMA_CCERRCLR, val);
+ }
+
if (!edma_error_pending(ecc))
break;
cnt++;
--
2.6.1
--
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 13:50 +0200 |
| Subject | [PATCH v5 13/24] dmaengine: edma: Use devm_kcalloc when possible |
| Message-ID | <qjsJd-5OD-61@gated-at.bofh.it> |
| In reply to | #1246586 |
When allocating a memory for number of items it is better (looks better) to use devm_kcalloc. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> --- drivers/dma/edma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index d5a76c67f83f..95c10373168d 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -2055,7 +2055,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata, * priority. So Q0 is the highest priority queue and the last queue has * the lowest priority. */ - queue_priority_map = devm_kzalloc(dev, (ecc->num_tc + 1) * sizeof(s8), + queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), GFP_KERNEL); if (!queue_priority_map) return -ENOMEM; @@ -2086,7 +2086,7 @@ static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata, u32 shift, offset, mux; int ret, i; - xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL); + xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL); if (!xbar_chans) return -ENOMEM; -- 2.6.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 13:50 +0200 |
| Subject | [PATCH v5 24/24] dmaengine: edma: Dynamic paRAM slot handling if HW supports it |
| Message-ID | <qjsJd-5OD-57@gated-at.bofh.it> |
| In reply to | #1246586 |
If the eDMA3 has support for channel paRAM slot mapping we can utilize it
to allocate slots on demand and save precious slots for real transfers.
On am335x the eDMA has 64 channels which means we can unlock 64 paRAM
slots out from the available 256.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 101 +++++++++++++++++++++++++++--------------------------
1 file changed, 52 insertions(+), 49 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 8d9169b7f208..7eefbf1e1c94 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -413,12 +413,13 @@ static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
}
-static void edma_direct_dmach_to_param_mapping(struct edma_cc *ecc)
+static void edma_set_chmap(struct edma_cc *ecc, int channel, int slot)
{
- int i;
-
- for (i = 0; i < ecc->num_channels; i++)
- edma_write_array(ecc, EDMA_DCHMAP, i, (i << 5));
+ if (ecc->chmap_exist) {
+ channel = EDMA_CHAN_SLOT(channel);
+ slot = EDMA_CHAN_SLOT(slot);
+ edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
+ }
}
static int prepare_unused_channel_list(struct device *dev, void *data)
@@ -528,10 +529,18 @@ static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
*/
static int edma_alloc_slot(struct edma_cc *ecc, int slot)
{
- if (slot > 0)
+ if (slot > 0) {
slot = EDMA_CHAN_SLOT(slot);
+ /* Requesting entry paRAM slot for a HW triggered channel. */
+ if (ecc->chmap_exist && slot < ecc->num_channels)
+ slot = EDMA_SLOT_ANY;
+ }
+
if (slot < 0) {
- slot = ecc->num_channels;
+ if (ecc->chmap_exist)
+ slot = 0;
+ else
+ slot = ecc->num_channels;
for (;;) {
slot = find_next_zero_bit(ecc->slot_inuse,
ecc->num_slots,
@@ -541,7 +550,7 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot)
if (!test_and_set_bit(slot, ecc->slot_inuse))
break;
}
- } else if (slot < ecc->num_channels || slot >= ecc->num_slots) {
+ } else if (slot >= ecc->num_slots) {
return -EINVAL;
} else if (test_and_set_bit(slot, ecc->slot_inuse)) {
return -EBUSY;
@@ -555,7 +564,7 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot)
static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
{
slot = EDMA_CHAN_SLOT(slot);
- if (slot < ecc->num_channels || slot >= ecc->num_slots)
+ if (slot >= ecc->num_slots)
return;
edma_write_slot(ecc, slot, &dummy_paramset);
@@ -806,7 +815,6 @@ static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
static int edma_alloc_channel(struct edma_cc *ecc, int channel,
enum dma_event_q eventq_no)
{
- unsigned done = 0;
int ret = 0;
if (!ecc->unused_chan_list_done) {
@@ -833,24 +841,12 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel,
}
if (channel < 0) {
- channel = 0;
- for (;;) {
- channel = find_next_bit(ecc->channel_unused,
- ecc->num_channels, channel);
- if (channel == ecc->num_channels)
- break;
- if (!test_and_set_bit(channel, ecc->slot_inuse)) {
- done = 1;
- break;
- }
- channel++;
- }
- if (!done)
- return -ENOMEM;
+ channel = find_next_bit(ecc->channel_unused, ecc->num_channels,
+ 0);
+ if (channel == ecc->num_channels)
+ return -EBUSY;
} else if (channel >= ecc->num_channels) {
return -EINVAL;
- } else if (test_and_set_bit(channel, ecc->slot_inuse)) {
- return -EBUSY;
}
/* ensure access through shadow region 0 */
@@ -858,7 +854,6 @@ static int edma_alloc_channel(struct edma_cc *ecc, int channel,
/* ensure no events are pending */
edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel));
- edma_write_slot(ecc, channel, &dummy_paramset);
edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true);
@@ -891,11 +886,8 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
if (channel >= ecc->num_channels)
return;
- edma_setup_interrupt(ecc, channel, false);
/* REVISIT should probably take out of shadow region 0 */
-
- edma_write_slot(ecc, channel, &dummy_paramset);
- clear_bit(channel, ecc->slot_inuse);
+ edma_setup_interrupt(ecc, channel, false);
}
/* Move channel to a specific event queue */
@@ -1729,7 +1721,15 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
}
echan->alloced = true;
- echan->slot[0] = echan->ch_num;
+ echan->slot[0] = edma_alloc_slot(echan->ecc, echan->ch_num);
+ if (echan->slot[0] < 0) {
+ dev_err(dev, "Entry slot allocation failed for channel %u\n",
+ EDMA_CHAN_SLOT(echan->ch_num));
+ goto err_wrong_chan;
+ }
+
+ /* Set up channel -> slot mapping for the entry slot */
+ edma_set_chmap(echan->ecc, echan->ch_num, echan->slot[0]);
dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num,
EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
@@ -1754,13 +1754,16 @@ static void edma_free_chan_resources(struct dma_chan *chan)
vchan_free_chan_resources(&echan->vchan);
/* Free EDMA PaRAM slots */
- for (i = 1; i < EDMA_MAX_SLOTS; i++) {
+ for (i = 0; i < EDMA_MAX_SLOTS; i++) {
if (echan->slot[i] >= 0) {
edma_free_slot(echan->ecc, echan->slot[i]);
echan->slot[i] = -1;
}
}
+ /* Set entry slot to the dummy slot */
+ edma_set_chmap(echan->ecc, echan->ch_num, echan->ecc->dummy_slot);
+
/* Free EDMA channel */
if (echan->alloced) {
edma_free_channel(echan->ecc, echan->ch_num);
@@ -2217,8 +2220,18 @@ static int edma_probe(struct platform_device *pdev)
}
}
- for (i = 0; i < ecc->num_channels; i++)
+ ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
+ if (ecc->dummy_slot < 0) {
+ dev_err(dev, "Can't allocate PaRAM dummy slot\n");
+ return ecc->dummy_slot;
+ }
+
+ for (i = 0; i < ecc->num_channels; i++) {
+ /* Assign all channels to the default queue */
edma_map_dmach_to_queue(ecc, i, info->default_queue);
+ /* Set entry slot to the dummy slot */
+ edma_set_chmap(ecc, i, ecc->dummy_slot);
+ }
queue_priority_mapping = info->queue_priority_mapping;
@@ -2227,10 +2240,6 @@ static int edma_probe(struct platform_device *pdev)
edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
queue_priority_mapping[i][1]);
- /* Map the channel to param entry if channel mapping logic exist */
- if (ecc->chmap_exist)
- edma_direct_dmach_to_param_mapping(ecc);
-
for (i = 0; i < ecc->num_region; i++) {
edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
@@ -2238,12 +2247,6 @@ static int edma_probe(struct platform_device *pdev)
}
ecc->info = info;
- ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
- if (ecc->dummy_slot < 0) {
- dev_err(dev, "Can't allocate PaRAM dummy slot\n");
- return ecc->dummy_slot;
- }
-
dma_cap_zero(ecc->dma_slave.cap_mask);
dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask);
@@ -2287,6 +2290,7 @@ static int edma_remove(struct platform_device *pdev)
static int edma_pm_resume(struct device *dev)
{
struct edma_cc *ecc = dev_get_drvdata(dev);
+ struct edma_chan *echan = ecc->slave_chans;
int i;
s8 (*queue_priority_mapping)[2];
@@ -2297,18 +2301,17 @@ static int edma_pm_resume(struct device *dev)
edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
queue_priority_mapping[i][1]);
- /* Map the channel to param entry if channel mapping logic */
- if (ecc->chmap_exist)
- edma_direct_dmach_to_param_mapping(ecc);
-
for (i = 0; i < ecc->num_channels; i++) {
- if (test_bit(i, ecc->slot_inuse)) {
+ if (echan[i].alloced) {
/* ensure access through shadow region 0 */
edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
BIT(i & 0x1f));
edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i),
true);
+
+ /* Set up channel -> slot mapping for the entry slot */
+ edma_set_chmap(ecc, echan[i].ch_num, echan[i].slot[0]);
}
}
--
2.6.1
--
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 14:00 +0200 |
| Subject | [PATCH v5 10/24] ARM: davinci: Add dma_mask to eDMA devices |
| Message-ID | <qjsSR-5ZS-5@gated-at.bofh.it> |
| In reply to | #1246586 |
The upcoming change to merge the arch/arm/common/edma.c into
drivers/dma/edma.c will need this change when booting daVinci devices in
no DT mode.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm/mach-davinci/devices-da8xx.c | 2 ++
arch/arm/mach-davinci/dm355.c | 1 +
arch/arm/mach-davinci/dm644x.c | 1 +
arch/arm/mach-davinci/dm646x.c | 1 +
4 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 9f7d266faa0c..28c90bc372bd 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -216,6 +216,7 @@ static struct resource da850_edma1_resources[] = {
static const struct platform_device_info da8xx_edma0_device __initconst = {
.name = "edma",
.id = 0,
+ .dma_mask = DMA_BIT_MASK(32),
.res = da8xx_edma0_resources,
.num_res = ARRAY_SIZE(da8xx_edma0_resources),
.data = &da8xx_edma0_pdata,
@@ -225,6 +226,7 @@ static const struct platform_device_info da8xx_edma0_device __initconst = {
static const struct platform_device_info da850_edma1_device __initconst = {
.name = "edma",
.id = 1,
+ .dma_mask = DMA_BIT_MASK(32),
.res = da850_edma1_resources,
.num_res = ARRAY_SIZE(da850_edma1_resources),
.data = &da850_edma1_pdata,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 5f10c6695e31..609950b8c191 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -616,6 +616,7 @@ static struct resource edma_resources[] = {
static const struct platform_device_info dm355_edma_device __initconst = {
.name = "edma",
.id = 0,
+ .dma_mask = DMA_BIT_MASK(32),
.res = edma_resources,
.num_res = ARRAY_SIZE(edma_resources),
.data = &dm355_edma_pdata,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index aa3453b40d5f..d38f5049d56e 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -545,6 +545,7 @@ static struct resource edma_resources[] = {
static const struct platform_device_info dm644x_edma_device __initconst = {
.name = "edma",
.id = 0,
+ .dma_mask = DMA_BIT_MASK(32),
.res = edma_resources,
.num_res = ARRAY_SIZE(edma_resources),
.data = &dm644x_edma_pdata,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 79c1d8917dd3..70eb42725eec 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -592,6 +592,7 @@ static struct resource edma_resources[] = {
static const struct platform_device_info dm646x_edma_device __initconst = {
.name = "edma",
.id = 0,
+ .dma_mask = DMA_BIT_MASK(32),
.res = edma_resources,
.num_res = ARRAY_SIZE(edma_resources),
.data = &dm646x_edma_pdata,
--
2.6.1
--
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 14:00 +0200 |
| Subject | [PATCH v5 08/24] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers |
| Message-ID | <qjsSS-5ZS-11@gated-at.bofh.it> |
| In reply to | #1246586 |
Since the driver stack no longer depends on lookup with id number in a
global array of pointers, the limitation for the number of eDMAs are no
longer needed. We can handle as many eDMAs in legacy and DT boot as we have
memory for them to allocate the needed structures.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 22 +++++-----------------
drivers/dma/edma.c | 17 ++++++++---------
2 files changed, 13 insertions(+), 26 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 03692520812a..5b747f1bc8b5 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1227,24 +1227,7 @@ static int edma_probe(struct platform_device *pdev)
.parent = &pdev->dev,
};
- /* When booting with DT the pdev->id is -1 */
- if (dev_id < 0)
- dev_id = arch_num_cc;
-
- if (dev_id >= EDMA_MAX_CC) {
- dev_err(dev,
- "eDMA3 with device id 0 and 1 is supported (id: %d)\n",
- dev_id);
- return -EINVAL;
- }
-
if (node) {
- /* Check if this is a second instance registered */
- if (arch_num_cc) {
- dev_err(dev, "only one EDMA instance is supported via DT\n");
- return -ENODEV;
- }
-
info = edma_setup_info_from_dt(dev, node);
if (IS_ERR(info)) {
dev_err(dev, "failed to get DT data\n");
@@ -1278,6 +1261,11 @@ static int edma_probe(struct platform_device *pdev)
cc->dev = dev;
cc->id = dev_id;
+ /* When booting with DT the pdev->id is -1 */
+ if (dev_id < 0) {
+ cc->id = 0;
+ dev_id = arch_num_cc;
+ }
dev_set_drvdata(dev, cc);
cc->base = devm_ioremap_resource(dev, mem);
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 53d48b2a700d..fc91ab9dd1bb 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -991,14 +991,12 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
INIT_LIST_HEAD(&dma->channels);
}
-static struct of_dma_filter_info edma_filter_info = {
- .filter_fn = edma_filter_fn,
-};
-
static int edma_probe(struct platform_device *pdev)
{
struct edma_cc *ecc;
struct device_node *parent_node = pdev->dev.parent->of_node;
+ struct platform_device *parent_pdev =
+ to_platform_device(pdev->dev.parent);
int ret;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
@@ -1015,7 +1013,10 @@ static int edma_probe(struct platform_device *pdev)
if (!ecc->cc)
return -ENODEV;
- ecc->ctlr = pdev->id;
+ ecc->ctlr = parent_pdev->id;
+ if (ecc->ctlr < 0)
+ ecc->ctlr = 0;
+
ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY);
if (ecc->dummy_slot < 0) {
dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
@@ -1038,10 +1039,8 @@ static int edma_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ecc);
if (parent_node) {
- dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
- dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
- of_dma_controller_register(parent_node, of_dma_simple_xlate,
- &edma_filter_info);
+ of_dma_controller_register(parent_node, of_dma_xlate_by_chan_id,
+ &ecc->dma_slave);
}
dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
--
2.6.1
--
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 14:00 +0200 |
| Subject | [PATCH v5 07/24] ARM/dmaengine: edma: Public API to use private struct pointer |
| Message-ID | <qjsSS-5ZS-15@gated-at.bofh.it> |
| In reply to | #1246586 |
Instead of relying on indexes pointing to edma private date in the global
pointer array, pass the private data pointer via the public API.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 305 ++++++++++++++++++-------------------
drivers/dma/edma.c | 79 +++++-----
include/linux/platform_data/edma.h | 38 +++--
3 files changed, 214 insertions(+), 208 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 0b4c0ee59ed9..03692520812a 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -130,7 +130,7 @@ struct edma {
struct edma_soc_info *info;
int id;
-
+ bool unused_chan_list_done;
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
@@ -264,7 +264,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p)
}
/*****************************************************************************/
-static struct edma *edma_cc[EDMA_MAX_CC];
static int arch_num_cc;
/* dummy param set used to (re)initialize parameter RAM slots */
@@ -490,14 +489,18 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
- int i, count, ctlr;
+ struct edma *cc = data;
+ int i, count;
struct of_phandle_args dma_spec;
if (dev->of_node) {
+ struct platform_device *dma_pdev;
+
count = of_property_count_strings(dev->of_node, "dma-names");
if (count < 0)
return 0;
for (i = 0; i < count; i++) {
+
if (of_parse_phandle_with_args(dev->of_node, "dmas",
"#dma-cells", i,
&dma_spec))
@@ -508,8 +511,12 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
continue;
}
+ dma_pdev = of_find_device_by_node(dma_spec.np);
+ if (&dma_pdev->dev != cc->dev)
+ continue;
+
clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
- edma_cc[0]->edma_unused);
+ cc->edma_unused);
of_node_put(dma_spec.np);
}
return 0;
@@ -517,11 +524,11 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
/* For non-OF case */
for (i = 0; i < pdev->num_resources; i++) {
- if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
- (int)pdev->resource[i].start >= 0) {
- ctlr = EDMA_CTLR(pdev->resource[i].start);
+ struct resource *res = &pdev->resource[i];
+
+ if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) {
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
- edma_cc[ctlr]->edma_unused);
+ cc->edma_unused);
}
}
@@ -530,8 +537,6 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
/*-----------------------------------------------------------------------*/
-static bool unused_chan_list_done;
-
/* Resource alloc/free: dma channels, parameter RAM slots */
/**
@@ -564,77 +569,73 @@ static bool unused_chan_list_done;
*
* Returns the number of the channel, else negative errno.
*/
-int edma_alloc_channel(int channel,
+int edma_alloc_channel(struct edma *cc, int channel,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data,
enum dma_event_q eventq_no)
{
- unsigned i, done = 0, ctlr = 0;
+ unsigned done = 0;
int ret = 0;
- if (!unused_chan_list_done) {
+ if (!cc->unused_chan_list_done) {
/*
* Scan all the platform devices to find out the EDMA channels
* used and clear them in the unused list, making the rest
* available for ARM usage.
*/
- ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
- prepare_unused_channel_list);
+ ret = bus_for_each_dev(&platform_bus_type, NULL, cc,
+ prepare_unused_channel_list);
if (ret < 0)
return ret;
- unused_chan_list_done = true;
+ cc->unused_chan_list_done = true;
}
if (channel >= 0) {
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n",
+ __func__, cc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
channel = EDMA_CHAN_SLOT(channel);
}
if (channel < 0) {
- for (i = 0; i < arch_num_cc; i++) {
- channel = 0;
- for (;;) {
- channel = find_next_bit(edma_cc[i]->edma_unused,
- edma_cc[i]->num_channels,
- channel);
- if (channel == edma_cc[i]->num_channels)
- break;
- if (!test_and_set_bit(channel,
- edma_cc[i]->edma_inuse)) {
- done = 1;
- ctlr = i;
- break;
- }
- channel++;
- }
- if (done)
+ channel = 0;
+ for (;;) {
+ channel = find_next_bit(cc->edma_unused,
+ cc->num_channels, channel);
+ if (channel == cc->num_channels)
+ break;
+ if (!test_and_set_bit(channel, cc->edma_inuse)) {
+ done = 1;
break;
+ }
+ channel++;
}
if (!done)
return -ENOMEM;
- } else if (channel >= edma_cc[ctlr]->num_channels) {
+ } else if (channel >= cc->num_channels) {
return -EINVAL;
- } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
+ } else if (test_and_set_bit(channel, cc->edma_inuse)) {
return -EBUSY;
}
/* ensure access through shadow region 0 */
- edma_or_array2(edma_cc[ctlr], EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+ edma_or_array2(cc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
/* ensure no events are pending */
- edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ edma_stop(cc, EDMA_CTLR_CHAN(cc->id, channel));
+ memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset,
PARM_SIZE);
if (callback)
- setup_dma_interrupt(edma_cc[ctlr],
- EDMA_CTLR_CHAN(ctlr, channel), callback,
- data);
+ setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, channel),
+ callback, data);
- map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
+ map_dmach_queue(cc, channel, eventq_no);
- return EDMA_CTLR_CHAN(ctlr, channel);
+ return EDMA_CTLR_CHAN(cc->id, channel);
}
EXPORT_SYMBOL(edma_alloc_channel);
@@ -650,22 +651,25 @@ EXPORT_SYMBOL(edma_alloc_channel);
* will not be reactivated by linking, chaining, or software calls to
* edma_start().
*/
-void edma_free_channel(unsigned channel)
+void edma_free_channel(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel >= edma_cc[ctlr]->num_channels)
+ if (channel >= cc->num_channels)
return;
- setup_dma_interrupt(edma_cc[ctlr], channel, NULL, NULL);
+ setup_dma_interrupt(cc, channel, NULL, NULL);
/* REVISIT should probably take out of shadow region 0 */
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset,
PARM_SIZE);
- clear_bit(channel, edma_cc[ctlr]->edma_inuse);
+ clear_bit(channel, cc->edma_inuse);
}
EXPORT_SYMBOL(edma_free_channel);
@@ -683,35 +687,29 @@ EXPORT_SYMBOL(edma_free_channel);
*
* Returns the number of the slot, else negative errno.
*/
-int edma_alloc_slot(unsigned ctlr, int slot)
+int edma_alloc_slot(struct edma *cc, int slot)
{
- if (!edma_cc[ctlr])
- return -EINVAL;
-
- if (slot >= 0)
+ if (slot > 0)
slot = EDMA_CHAN_SLOT(slot);
-
if (slot < 0) {
- slot = edma_cc[ctlr]->num_channels;
+ slot = cc->num_channels;
for (;;) {
- slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
- edma_cc[ctlr]->num_slots, slot);
- if (slot == edma_cc[ctlr]->num_slots)
+ slot = find_next_zero_bit(cc->edma_inuse, cc->num_slots,
+ slot);
+ if (slot == cc->num_slots)
return -ENOMEM;
- if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
+ if (!test_and_set_bit(slot, cc->edma_inuse))
break;
}
- } else if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots) {
+ } else if (slot < cc->num_channels || slot >= cc->num_slots) {
return -EINVAL;
- } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
+ } else if (test_and_set_bit(slot, cc->edma_inuse)) {
return -EBUSY;
}
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
- PARM_SIZE);
+ memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE);
- return EDMA_CTLR_CHAN(ctlr, slot);
+ return slot;
}
EXPORT_SYMBOL(edma_alloc_slot);
@@ -723,20 +721,15 @@ EXPORT_SYMBOL(edma_alloc_slot);
* Callers are responsible for ensuring the slot is inactive, and will
* not be activated.
*/
-void edma_free_slot(unsigned slot)
+void edma_free_slot(struct edma *cc, unsigned slot)
{
- unsigned ctlr;
- ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots)
+ if (slot < cc->num_channels || slot >= cc->num_slots)
return;
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
- PARM_SIZE);
- clear_bit(slot, edma_cc[ctlr]->edma_inuse);
+ memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE);
+ clear_bit(slot, cc->edma_inuse);
}
EXPORT_SYMBOL(edma_free_slot);
@@ -751,16 +744,15 @@ EXPORT_SYMBOL(edma_free_slot);
*
* Returns the position of the current active slot
*/
-dma_addr_t edma_get_position(unsigned slot, bool dst)
+dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst)
{
- u32 offs, ctlr = EDMA_CTLR(slot);
+ u32 offs;
slot = EDMA_CHAN_SLOT(slot);
-
offs = PARM_OFFSET(slot);
offs += dst ? PARM_DST : PARM_SRC;
- return edma_read(edma_cc[ctlr], offs);
+ return edma_read(cc, offs);
}
/**
@@ -770,21 +762,15 @@ dma_addr_t edma_get_position(unsigned slot, bool dst)
*
* The originating slot should not be part of any active DMA transfer.
*/
-void edma_link(unsigned from, unsigned to)
+void edma_link(struct edma *cc, unsigned from, unsigned to)
{
- unsigned ctlr_from, ctlr_to;
-
- ctlr_from = EDMA_CTLR(from);
from = EDMA_CHAN_SLOT(from);
- ctlr_to = EDMA_CTLR(to);
to = EDMA_CHAN_SLOT(to);
-
- if (from >= edma_cc[ctlr_from]->num_slots)
+ if (from >= cc->num_slots || to >= cc->num_slots)
return;
- if (to >= edma_cc[ctlr_to]->num_slots)
- return;
- edma_parm_modify(edma_cc[ctlr_from], PARM_LINK_BCNTRLD, from, 0xffff0000,
- PARM_OFFSET(to));
+
+ edma_parm_modify(cc, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ PARM_OFFSET(to));
}
EXPORT_SYMBOL(edma_link);
@@ -802,16 +788,13 @@ EXPORT_SYMBOL(edma_link);
* calls to set up those parameters in small pieces, and provides
* complete control over all transfer options.
*/
-void edma_write_slot(unsigned slot, const struct edmacc_param *param)
+void edma_write_slot(struct edma *cc, unsigned slot,
+ const struct edmacc_param *param)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
-
- if (slot >= edma_cc[ctlr]->num_slots)
+ if (slot >= cc->num_slots)
return;
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), param, PARM_SIZE);
+ memcpy_toio(cc->base + PARM_OFFSET(slot), param, PARM_SIZE);
}
EXPORT_SYMBOL(edma_write_slot);
@@ -823,17 +806,12 @@ EXPORT_SYMBOL(edma_write_slot);
* Use this to read data from a parameter RAM slot, perhaps to
* save them as a template for later reuse.
*/
-void edma_read_slot(unsigned slot, struct edmacc_param *param)
+void edma_read_slot(struct edma *cc, unsigned slot, struct edmacc_param *param)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
-
- if (slot >= edma_cc[ctlr]->num_slots)
+ if (slot >= cc->num_slots)
return;
- memcpy_fromio(param, edma_cc[ctlr]->base + PARM_OFFSET(slot),
- PARM_SIZE);
+ memcpy_fromio(param, cc->base + PARM_OFFSET(slot), PARM_SIZE);
}
EXPORT_SYMBOL(edma_read_slot);
@@ -848,18 +826,19 @@ EXPORT_SYMBOL(edma_read_slot);
* This temporarily disables EDMA hardware events on the specified channel,
* preventing them from triggering new transfers on its behalf
*/
-void edma_pause(unsigned channel)
+void edma_pause(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
+ if (channel < cc->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(edma_cc[ctlr], SH_EECR, channel >> 5,
- mask);
+ edma_shadow0_write_array(cc, SH_EECR, channel >> 5, mask);
}
}
EXPORT_SYMBOL(edma_pause);
@@ -870,36 +849,39 @@ EXPORT_SYMBOL(edma_pause);
*
* This re-enables EDMA hardware events on the specified channel.
*/
-void edma_resume(unsigned channel)
+void edma_resume(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
+ if (channel < cc->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(edma_cc[ctlr], SH_EESR, channel >> 5,
- mask);
+ edma_shadow0_write_array(cc, SH_EESR, channel >> 5, mask);
}
}
EXPORT_SYMBOL(edma_resume);
-int edma_trigger_channel(unsigned channel)
+int edma_trigger_channel(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
unsigned int mask;
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
channel = EDMA_CHAN_SLOT(channel);
mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(edma_cc[ctlr], SH_ESR, (channel >> 5), mask);
+ edma_shadow0_write_array(cc, SH_ESR, (channel >> 5), mask);
pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
- edma_shadow0_read_array(edma_cc[ctlr], SH_ESR,
- (channel >> 5)));
+ edma_shadow0_read_array(cc, SH_ESR, (channel >> 5)));
return 0;
}
EXPORT_SYMBOL(edma_trigger_channel);
@@ -915,15 +897,16 @@ EXPORT_SYMBOL(edma_trigger_channel);
*
* Returns zero on success, else negative errno.
*/
-int edma_start(unsigned channel)
+int edma_start(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
- struct edma *cc = edma_cc[ctlr];
+ if (channel < cc->num_channels) {
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
@@ -962,15 +945,16 @@ EXPORT_SYMBOL(edma_start);
* may not be resumed, and the channel's Parameter RAM should be
* reinitialized before being reused.
*/
-void edma_stop(unsigned channel)
+void edma_stop(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
- struct edma *cc = edma_cc[ctlr];
+ if (channel < cc->num_channels) {
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
@@ -1005,15 +989,16 @@ EXPORT_SYMBOL(edma_stop);
*
*****************************************************************************/
-void edma_clean_channel(unsigned channel)
+void edma_clean_channel(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
- struct edma *cc = edma_cc[ctlr];
+ if (channel < cc->num_channels) {
int j = (channel >> 5);
unsigned int mask = BIT(channel & 0x1f);
@@ -1037,26 +1022,35 @@ EXPORT_SYMBOL(edma_clean_channel);
*
* Can be used to move a channel to a selected event queue.
*/
-void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
+void edma_assign_channel_eventq(struct edma *cc, unsigned channel,
+ enum dma_event_q eventq_no)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel >= edma_cc[ctlr]->num_channels)
+ if (channel >= cc->num_channels)
return;
/* default to low priority queue */
if (eventq_no == EVENTQ_DEFAULT)
- eventq_no = edma_cc[ctlr]->default_queue;
- if (eventq_no >= edma_cc[ctlr]->num_tc)
+ eventq_no = cc->default_queue;
+ if (eventq_no >= cc->num_tc)
return;
- map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
+ map_dmach_queue(cc, channel, eventq_no);
}
EXPORT_SYMBOL(edma_assign_channel_eventq);
+struct edma *edma_get_data(struct device *edma_dev)
+{
+ return dev_get_drvdata(edma_dev);
+}
+
+
static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
struct edma *edma_cc, int cc_id)
{
@@ -1278,11 +1272,10 @@ static int edma_probe(struct platform_device *pdev)
}
}
- edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
- if (!edma_cc[dev_id])
+ cc = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
+ if (!cc)
return -ENOMEM;
- cc = edma_cc[dev_id];
cc->dev = dev;
cc->id = dev_id;
dev_set_drvdata(dev, cc);
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index fcb4680efed7..53d48b2a700d 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -119,6 +119,7 @@ struct edma_chan {
};
struct edma_cc {
+ struct edma *cc;
int ctlr;
struct dma_device dma_slave;
struct edma_chan slave_chans[EDMA_CHANS];
@@ -150,6 +151,7 @@ static void edma_desc_free(struct virt_dma_desc *vdesc)
/* Dispatch a queued descriptor to the controller (caller holds lock) */
static void edma_execute(struct edma_chan *echan)
{
+ struct edma *cc = echan->ecc->cc;
struct virt_dma_desc *vdesc;
struct edma_desc *edesc;
struct device *dev = echan->vchan.chan.device->dev;
@@ -174,7 +176,7 @@ static void edma_execute(struct edma_chan *echan)
/* Write descriptor PaRAM set(s) */
for (i = 0; i < nslots; i++) {
j = i + edesc->processed;
- edma_write_slot(echan->slot[i], &edesc->pset[j].param);
+ edma_write_slot(cc, echan->slot[i], &edesc->pset[j].param);
edesc->sg_len += edesc->pset[j].len;
dev_vdbg(echan->vchan.chan.device->dev,
"\n pset[%d]:\n"
@@ -199,7 +201,7 @@ static void edma_execute(struct edma_chan *echan)
edesc->pset[j].param.link_bcntrld);
/* Link to the previous slot if not the last set */
if (i != (nslots - 1))
- edma_link(echan->slot[i], echan->slot[i+1]);
+ edma_link(cc, echan->slot[i], echan->slot[i+1]);
}
edesc->processed += nslots;
@@ -211,9 +213,9 @@ static void edma_execute(struct edma_chan *echan)
*/
if (edesc->processed == edesc->pset_nr) {
if (edesc->cyclic)
- edma_link(echan->slot[nslots-1], echan->slot[1]);
+ edma_link(cc, echan->slot[nslots-1], echan->slot[1]);
else
- edma_link(echan->slot[nslots-1],
+ edma_link(cc, echan->slot[nslots-1],
echan->ecc->dummy_slot);
}
@@ -224,19 +226,19 @@ static void edma_execute(struct edma_chan *echan)
* transfers of MAX_NR_SG
*/
dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
- edma_clean_channel(echan->ch_num);
- edma_stop(echan->ch_num);
- edma_start(echan->ch_num);
- edma_trigger_channel(echan->ch_num);
+ edma_clean_channel(cc, echan->ch_num);
+ edma_stop(cc, echan->ch_num);
+ edma_start(cc, echan->ch_num);
+ edma_trigger_channel(cc, echan->ch_num);
echan->missed = 0;
} else if (edesc->processed <= MAX_NR_SG) {
dev_dbg(dev, "first transfer starting on channel %d\n",
echan->ch_num);
- edma_start(echan->ch_num);
+ edma_start(cc, echan->ch_num);
} else {
dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
echan->ch_num, edesc->processed);
- edma_resume(echan->ch_num);
+ edma_resume(cc, echan->ch_num);
}
}
@@ -254,10 +256,11 @@ static int edma_terminate_all(struct dma_chan *chan)
* echan->edesc is NULL and exit.)
*/
if (echan->edesc) {
- edma_stop(echan->ch_num);
+ edma_stop(echan->ecc->cc, echan->ch_num);
/* Move the cyclic channel back to default queue */
if (echan->edesc->cyclic)
- edma_assign_channel_eventq(echan->ch_num,
+ edma_assign_channel_eventq(echan->ecc->cc,
+ echan->ch_num,
EVENTQ_DEFAULT);
/*
* free the running request descriptor
@@ -295,7 +298,7 @@ static int edma_dma_pause(struct dma_chan *chan)
if (!echan->edesc)
return -EINVAL;
- edma_pause(echan->ch_num);
+ edma_pause(echan->ecc->cc, echan->ch_num);
return 0;
}
@@ -303,7 +306,7 @@ static int edma_dma_resume(struct dma_chan *chan)
{
struct edma_chan *echan = to_edma_chan(chan);
- edma_resume(echan->ch_num);
+ edma_resume(echan->ecc->cc, echan->ch_num);
return 0;
}
@@ -485,8 +488,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
for (i = 0; i < nslots; i++) {
if (echan->slot[i] < 0) {
echan->slot[i] =
- edma_alloc_slot(EDMA_CTLR(echan->ch_num),
- EDMA_SLOT_ANY);
+ edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY);
if (echan->slot[i] < 0) {
kfree(edesc);
dev_err(dev, "%s: Failed to allocate slot\n",
@@ -641,8 +643,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
/* Allocate a PaRAM slot, if needed */
if (echan->slot[i] < 0) {
echan->slot[i] =
- edma_alloc_slot(EDMA_CTLR(echan->ch_num),
- EDMA_SLOT_ANY);
+ edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY);
if (echan->slot[i] < 0) {
kfree(edesc);
dev_err(dev, "%s: Failed to allocate slot\n",
@@ -703,7 +704,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
}
/* Place the cyclic channel to highest priority queue */
- edma_assign_channel_eventq(echan->ch_num, EVENTQ_0);
+ edma_assign_channel_eventq(echan->ecc->cc, echan->ch_num, EVENTQ_0);
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}
@@ -711,6 +712,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
{
struct edma_chan *echan = data;
+ struct edma *cc = echan->ecc->cc;
struct device *dev = echan->vchan.chan.device->dev;
struct edma_desc *edesc;
struct edmacc_param p;
@@ -727,13 +729,13 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
} else if (edesc->processed == edesc->pset_nr) {
dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
edesc->residue = 0;
- edma_stop(echan->ch_num);
+ edma_stop(cc, echan->ch_num);
vchan_cookie_complete(&edesc->vdesc);
echan->edesc = NULL;
} else {
dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
- edma_pause(echan->ch_num);
+ edma_pause(cc, echan->ch_num);
/* Update statistics for tx_status */
edesc->residue -= edesc->sg_len;
@@ -744,7 +746,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
}
break;
case EDMA_DMA_CC_ERROR:
- edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
+ edma_read_slot(cc, echan->slot[0], &p);
/*
* Issue later based on missed flag which will be sure
@@ -767,10 +769,10 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
* missed, so its safe to issue it here.
*/
dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
- edma_clean_channel(echan->ch_num);
- edma_stop(echan->ch_num);
- edma_start(echan->ch_num);
- edma_trigger_channel(echan->ch_num);
+ edma_clean_channel(cc, echan->ch_num);
+ edma_stop(cc, echan->ch_num);
+ edma_start(cc, echan->ch_num);
+ edma_trigger_channel(cc, echan->ch_num);
}
break;
default:
@@ -789,8 +791,8 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
int a_ch_num;
LIST_HEAD(descs);
- a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
- echan, EVENTQ_DEFAULT);
+ a_ch_num = edma_alloc_channel(echan->ecc->cc, echan->ch_num,
+ edma_callback, echan, EVENTQ_DEFAULT);
if (a_ch_num < 0) {
ret = -ENODEV;
@@ -814,7 +816,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
return 0;
err_wrong_chan:
- edma_free_channel(a_ch_num);
+ edma_free_channel(echan->ecc->cc, a_ch_num);
err_no_chan:
return ret;
}
@@ -827,21 +829,21 @@ static void edma_free_chan_resources(struct dma_chan *chan)
int i;
/* Terminate transfers */
- edma_stop(echan->ch_num);
+ edma_stop(echan->ecc->cc, echan->ch_num);
vchan_free_chan_resources(&echan->vchan);
/* Free EDMA PaRAM slots */
for (i = 1; i < EDMA_MAX_SLOTS; i++) {
if (echan->slot[i] >= 0) {
- edma_free_slot(echan->slot[i]);
+ edma_free_slot(echan->ecc->cc, echan->slot[i]);
echan->slot[i] = -1;
}
}
/* Free EDMA channel */
if (echan->alloced) {
- edma_free_channel(echan->ch_num);
+ edma_free_channel(echan->ecc->cc, echan->ch_num);
echan->alloced = false;
}
@@ -871,7 +873,8 @@ static u32 edma_residue(struct edma_desc *edesc)
* We always read the dst/src position from the first RamPar
* pset. That's the one which is active now.
*/
- pos = edma_get_position(edesc->echan->slot[0], dst);
+ pos = edma_get_position(edesc->echan->ecc->cc, edesc->echan->slot[0],
+ dst);
/*
* Cyclic is simple. Just subtract pset[0].addr from pos.
@@ -1008,8 +1011,12 @@ static int edma_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ ecc->cc = edma_get_data(pdev->dev.parent);
+ if (!ecc->cc)
+ return -ENODEV;
+
ecc->ctlr = pdev->id;
- ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
+ ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY);
if (ecc->dummy_slot < 0) {
dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
return ecc->dummy_slot;
@@ -1042,7 +1049,7 @@ static int edma_probe(struct platform_device *pdev)
return 0;
err_reg1:
- edma_free_slot(ecc->dummy_slot);
+ edma_free_slot(ecc->cc, ecc->dummy_slot);
return ret;
}
@@ -1055,7 +1062,7 @@ static int edma_remove(struct platform_device *pdev)
if (parent_node)
of_dma_controller_free(parent_node);
dma_async_device_unregister(&ecc->dma_slave);
- edma_free_slot(ecc->dummy_slot);
+ edma_free_slot(ecc->cc, ecc->dummy_slot);
return 0;
}
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index c1862423b356..466021c03169 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -92,32 +92,40 @@ enum dma_event_q {
#define EDMA_MAX_CC 2
+struct edma;
+
+struct edma *edma_get_data(struct device *edma_dev);
+
/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(int channel,
+int edma_alloc_channel(struct edma *cc, int channel,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data, enum dma_event_q);
-void edma_free_channel(unsigned channel);
+void edma_free_channel(struct edma *cc, unsigned channel);
/* alloc/free parameter RAM slots */
-int edma_alloc_slot(unsigned ctlr, int slot);
-void edma_free_slot(unsigned slot);
+int edma_alloc_slot(struct edma *cc, int slot);
+void edma_free_slot(struct edma *cc, unsigned slot);
/* calls that operate on part of a parameter RAM slot */
-dma_addr_t edma_get_position(unsigned slot, bool dst);
-void edma_link(unsigned from, unsigned to);
+dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst);
+void edma_link(struct edma *cc, unsigned from, unsigned to);
/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-void edma_read_slot(unsigned slot, struct edmacc_param *params);
+void edma_write_slot(struct edma *cc, unsigned slot,
+ const struct edmacc_param *params);
+void edma_read_slot(struct edma *cc, unsigned slot,
+ struct edmacc_param *params);
/* channel control operations */
-int edma_start(unsigned channel);
-void edma_stop(unsigned channel);
-void edma_clean_channel(unsigned channel);
-void edma_pause(unsigned channel);
-void edma_resume(unsigned channel);
+int edma_start(struct edma *cc, unsigned channel);
+void edma_stop(struct edma *cc, unsigned channel);
+void edma_clean_channel(struct edma *cc, unsigned channel);
+void edma_pause(struct edma *cc, unsigned channel);
+void edma_resume(struct edma *cc, unsigned channel);
+int edma_trigger_channel(struct edma *cc, unsigned channel);
-void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no);
+void edma_assign_channel_eventq(struct edma *cc, unsigned channel,
+ enum dma_event_q eventq_no);
struct edma_rsv_info {
@@ -141,6 +149,4 @@ struct edma_soc_info {
const s16 (*xbar_chans)[2];
};
-int edma_trigger_channel(unsigned);
-
#endif
--
2.6.1
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[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 14:00 +0200 |
| Subject | [PATCH v5 02/24] ARM: common: edma: Remove unused functions |
| Message-ID | <qjsSS-5ZS-27@gated-at.bofh.it> |
| In reply to | #1246586 |
We no longer have users for these functions so they can be removed.
Remove also unused enums from the header file.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 376 -------------------------------------
include/linux/platform_data/edma.h | 33 ----
2 files changed, 409 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 56fc339571f9..e9c4cb16a47e 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -510,62 +510,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
return IRQ_HANDLED;
}
-static int reserve_contiguous_slots(int ctlr, unsigned int id,
- unsigned int num_slots,
- unsigned int start_slot)
-{
- int i, j;
- unsigned int count = num_slots;
- int stop_slot = start_slot;
- DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
-
- for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
- j = EDMA_CHAN_SLOT(i);
- if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
- /* Record our current beginning slot */
- if (count == num_slots)
- stop_slot = i;
-
- count--;
- set_bit(j, tmp_inuse);
-
- if (count == 0)
- break;
- } else {
- clear_bit(j, tmp_inuse);
-
- if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
- stop_slot = i;
- break;
- } else {
- count = num_slots;
- }
- }
- }
-
- /*
- * We have to clear any bits that we set
- * if we run out parameter RAM slots, i.e we do find a set
- * of contiguous parameter RAM slots but do not find the exact number
- * requested as we may reach the total number of parameter RAM slots
- */
- if (i == edma_cc[ctlr]->num_slots)
- stop_slot = i;
-
- j = start_slot;
- for_each_set_bit_from(j, tmp_inuse, stop_slot)
- clear_bit(j, edma_cc[ctlr]->edma_inuse);
-
- if (count)
- return -EBUSY;
-
- for (j = i - num_slots + 1; j <= i; ++j)
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
- &dummy_paramset, PARM_SIZE);
-
- return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
-}
-
static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -818,186 +762,11 @@ void edma_free_slot(unsigned slot)
}
EXPORT_SYMBOL(edma_free_slot);
-
-/**
- * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
- * The API will return the starting point of a set of
- * contiguous parameter RAM slots that have been requested
- *
- * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
- * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- * @count: number of contiguous Paramter RAM slots
- * @slot - the start value of Parameter RAM slot that should be passed if id
- * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- *
- * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
- * contiguous Parameter RAM slots from parameter RAM 64 in the case of
- * DaVinci SOCs and 32 in the case of DA8xx SOCs.
- *
- * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
- * set of contiguous parameter RAM slots from the "slot" that is passed as an
- * argument to the API.
- *
- * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
- * starts looking for a set of contiguous parameter RAMs from the "slot"
- * that is passed as an argument to the API. On failure the API will try to
- * find a set of contiguous Parameter RAM slots from the remaining Parameter
- * RAM slots
- */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
-{
- /*
- * The start slot requested should be greater than
- * the number of channels and lesser than the total number
- * of slots
- */
- if ((id != EDMA_CONT_PARAMS_ANY) &&
- (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots))
- return -EINVAL;
-
- /*
- * The number of parameter RAM slots requested cannot be less than 1
- * and cannot be more than the number of slots minus the number of
- * channels
- */
- if (count < 1 || count >
- (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
- return -EINVAL;
-
- switch (id) {
- case EDMA_CONT_PARAMS_ANY:
- return reserve_contiguous_slots(ctlr, id, count,
- edma_cc[ctlr]->num_channels);
- case EDMA_CONT_PARAMS_FIXED_EXACT:
- case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
- return reserve_contiguous_slots(ctlr, id, count, slot);
- default:
- return -EINVAL;
- }
-
-}
-EXPORT_SYMBOL(edma_alloc_cont_slots);
-
-/**
- * edma_free_cont_slots - deallocate DMA parameter RAM slots
- * @slot: first parameter RAM of a set of parameter RAM slots to be freed
- * @count: the number of contiguous parameter RAM slots to be freed
- *
- * This deallocates the parameter RAM slots allocated by
- * edma_alloc_cont_slots.
- * Callers/applications need to keep track of sets of contiguous
- * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
- * API.
- * Callers are responsible for ensuring the slots are inactive, and will
- * not be activated.
- */
-int edma_free_cont_slots(unsigned slot, int count)
-{
- unsigned ctlr, slot_to_free;
- int i;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots ||
- count < 1)
- return -EINVAL;
-
- for (i = slot; i < slot + count; ++i) {
- ctlr = EDMA_CTLR(i);
- slot_to_free = EDMA_CHAN_SLOT(i);
-
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
- &dummy_paramset, PARM_SIZE);
- clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
- }
-
- return 0;
-}
-EXPORT_SYMBOL(edma_free_cont_slots);
-
/*-----------------------------------------------------------------------*/
/* Parameter RAM operations (i) -- read/write partial slots */
/**
- * edma_set_src - set initial DMA source address in parameter RAM slot
- * @slot: parameter RAM slot being configured
- * @src_port: physical address of source (memory, controller FIFO, etc)
- * @addressMode: INCR, except in very rare cases
- * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- *
- * Note that the source address is modified during the DMA transfer
- * according to edma_set_src_index().
- */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
- enum address_mode mode, enum fifo_width width)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-
- if (mode) {
- /* set SAM and program FWID */
- i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
- } else {
- /* clear SAM */
- i &= ~SAM;
- }
- edma_parm_write(ctlr, PARM_OPT, slot, i);
-
- /* set the source port address
- in source register of param structure */
- edma_parm_write(ctlr, PARM_SRC, slot, src_port);
- }
-}
-EXPORT_SYMBOL(edma_set_src);
-
-/**
- * edma_set_dest - set initial DMA destination address in parameter RAM slot
- * @slot: parameter RAM slot being configured
- * @dest_port: physical address of destination (memory, controller FIFO, etc)
- * @addressMode: INCR, except in very rare cases
- * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- *
- * Note that the destination address is modified during the DMA transfer
- * according to edma_set_dest_index().
- */
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- enum address_mode mode, enum fifo_width width)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-
- if (mode) {
- /* set DAM and program FWID */
- i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
- } else {
- /* clear DAM */
- i &= ~DAM;
- }
- edma_parm_write(ctlr, PARM_OPT, slot, i);
- /* set the destination port address
- in dest register of param structure */
- edma_parm_write(ctlr, PARM_DST, slot, dest_port);
- }
-}
-EXPORT_SYMBOL(edma_set_dest);
-
-/**
* edma_get_position - returns the current transfer point
* @slot: parameter RAM slot being examined
* @dst: true selects the dest position, false the source
@@ -1017,110 +786,6 @@ dma_addr_t edma_get_position(unsigned slot, bool dst)
}
/**
- * edma_set_src_index - configure DMA source address indexing
- * @slot: parameter RAM slot being configured
- * @src_bidx: byte offset between source arrays in a frame
- * @src_cidx: byte offset between source frames in a block
- *
- * Offsets are specified to support either contiguous or discontiguous
- * memory transfers, or repeated access to a hardware register, as needed.
- * When accessing hardware registers, both offsets are normally zero.
- */
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- 0xffff0000, src_bidx);
- edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- 0xffff0000, src_cidx);
- }
-}
-EXPORT_SYMBOL(edma_set_src_index);
-
-/**
- * edma_set_dest_index - configure DMA destination address indexing
- * @slot: parameter RAM slot being configured
- * @dest_bidx: byte offset between destination arrays in a frame
- * @dest_cidx: byte offset between destination frames in a block
- *
- * Offsets are specified to support either contiguous or discontiguous
- * memory transfers, or repeated access to a hardware register, as needed.
- * When accessing hardware registers, both offsets are normally zero.
- */
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- 0x0000ffff, dest_bidx << 16);
- edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- 0x0000ffff, dest_cidx << 16);
- }
-}
-EXPORT_SYMBOL(edma_set_dest_index);
-
-/**
- * edma_set_transfer_params - configure DMA transfer parameters
- * @slot: parameter RAM slot being configured
- * @acnt: how many bytes per array (at least one)
- * @bcnt: how many arrays per frame (at least one)
- * @ccnt: how many frames per block (at least one)
- * @bcnt_rld: used only for A-Synchronized transfers; this specifies
- * the value to reload into bcnt when it decrements to zero
- * @sync_mode: ASYNC or ABSYNC
- *
- * See the EDMA3 documentation to understand how to configure and link
- * transfers using the fields in PaRAM slots. If you are not doing it
- * all at once with edma_write_slot(), you will use this routine
- * plus two calls each for source and destination, setting the initial
- * address and saying how to index that address.
- *
- * An example of an A-Synchronized transfer is a serial link using a
- * single word shift register. In that case, @acnt would be equal to
- * that word size; the serial controller issues a DMA synchronization
- * event to transfer each word, and memory access by the DMA transfer
- * controller will be word-at-a-time.
- *
- * An example of an AB-Synchronized transfer is a device using a FIFO.
- * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
- * The controller with the FIFO issues DMA synchronization events when
- * the FIFO threshold is reached, and the DMA transfer controller will
- * transfer one frame to (or from) the FIFO. It will probably use
- * efficient burst modes to access memory.
- */
-void edma_set_transfer_params(unsigned slot,
- u16 acnt, u16 bcnt, u16 ccnt,
- u16 bcnt_rld, enum sync_dimension sync_mode)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
- 0x0000ffff, bcnt_rld << 16);
- if (sync_mode == ASYNC)
- edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
- else
- edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
- /* Set the acount, bcount, ccount registers */
- edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
- edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
- }
-}
-EXPORT_SYMBOL(edma_set_transfer_params);
-
-/**
* edma_link - link one parameter RAM slot to another
* @from: parameter RAM slot originating the link
* @to: parameter RAM slot which is the link target
@@ -1145,26 +810,6 @@ void edma_link(unsigned from, unsigned to)
}
EXPORT_SYMBOL(edma_link);
-/**
- * edma_unlink - cut link from one parameter RAM slot
- * @from: parameter RAM slot originating the link
- *
- * The originating slot should not be part of any active DMA transfer.
- * Its link is set to 0xffff.
- */
-void edma_unlink(unsigned from)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(from);
- from = EDMA_CHAN_SLOT(from);
-
- if (from >= edma_cc[ctlr]->num_slots)
- return;
- edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
-}
-EXPORT_SYMBOL(edma_unlink);
-
/*-----------------------------------------------------------------------*/
/* Parameter RAM operations (ii) -- read/write whole parameter sets */
@@ -1402,27 +1047,6 @@ void edma_clean_channel(unsigned channel)
EXPORT_SYMBOL(edma_clean_channel);
/*
- * edma_clear_event - clear an outstanding event on the DMA channel
- * Arguments:
- * channel - channel number
- */
-void edma_clear_event(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel >= edma_cc[ctlr]->num_channels)
- return;
- if (channel < 32)
- edma_write(ctlr, EDMA_ECR, BIT(channel));
- else
- edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
-}
-EXPORT_SYMBOL(edma_clear_event);
-
-/*
* edma_assign_channel_eventq - move given channel to desired eventq
* Arguments:
* channel - channel number
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index bdb2710e2aab..c1862423b356 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -72,20 +72,6 @@ struct edmacc_param {
#define EDMA_DMA_TC1_ERROR 3
#define EDMA_DMA_TC2_ERROR 4
-enum address_mode {
- INCR = 0,
- FIFO = 1
-};
-
-enum fifo_width {
- W8BIT = 0,
- W16BIT = 1,
- W32BIT = 2,
- W64BIT = 3,
- W128BIT = 4,
- W256BIT = 5
-};
-
enum dma_event_q {
EVENTQ_0 = 0,
EVENTQ_1 = 1,
@@ -94,11 +80,6 @@ enum dma_event_q {
EVENTQ_DEFAULT = -1
};
-enum sync_dimension {
- ASYNC = 0,
- ABSYNC = 1
-};
-
#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
#define EDMA_CTLR(i) ((i) >> 16)
#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
@@ -121,22 +102,9 @@ void edma_free_channel(unsigned channel);
int edma_alloc_slot(unsigned ctlr, int slot);
void edma_free_slot(unsigned slot);
-/* alloc/free a set of contiguous parameter RAM slots */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-int edma_free_cont_slots(unsigned slot, int count);
-
/* calls that operate on part of a parameter RAM slot */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
- enum address_mode mode, enum fifo_width);
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- enum address_mode mode, enum fifo_width);
dma_addr_t edma_get_position(unsigned slot, bool dst);
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
- u16 bcnt_rld, enum sync_dimension sync_mode);
void edma_link(unsigned from, unsigned to);
-void edma_unlink(unsigned from);
/* calls that operate on an entire parameter RAM slot */
void edma_write_slot(unsigned slot, const struct edmacc_param *params);
@@ -146,7 +114,6 @@ void edma_read_slot(unsigned slot, struct edmacc_param *params);
int edma_start(unsigned channel);
void edma_stop(unsigned channel);
void edma_clean_channel(unsigned channel);
-void edma_clear_event(unsigned channel);
void edma_pause(unsigned channel);
void edma_resume(unsigned channel);
--
2.6.1
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-14 14:00 +0200 |
| Subject | [PATCH v5 12/24] dmaengine: edma: Allocate memory dynamically for bitmaps and structures |
| Message-ID | <qjsSS-5ZS-31@gated-at.bofh.it> |
| In reply to | #1246586 |
Instead of using defines to specify the size of different arrays and
bitmaps, allocate the memory for them based on the information we get from
the HW itself.
Since these defines are set based on the worst case, there are devices
where they are not valid.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 62 ++++++++++++++++++++++++++++++------------------------
1 file changed, 34 insertions(+), 28 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index aeb67e0cc523..d5a76c67f83f 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -113,23 +113,6 @@
#define CHMAP_EXIST BIT(24)
/*
- * This will go away when the private EDMA API is folded
- * into this driver and the platform device(s) are
- * instantiated in the arch code. We can only get away
- * with this simplification because DA8XX may not be built
- * in the same kernel image with other DaVinci parts. This
- * avoids having to sprinkle dmaengine driver platform devices
- * and data throughout all the existing board files.
- */
-#ifdef CONFIG_ARCH_DAVINCI_DA8XX
-#define EDMA_CTLRS 2
-#define EDMA_CHANS 32
-#else
-#define EDMA_CTLRS 1
-#define EDMA_CHANS 64
-#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
-
-/*
* Max of 20 segments per channel to conserve PaRAM slots
* Also note that MAX_NR_SG should be atleast the no.of periods
* that are required for ASoC, otherwise DMA prep calls will
@@ -140,16 +123,12 @@
#define EDMA_MAX_SLOTS MAX_NR_SG
#define EDMA_DESCRIPTORS 16
-#define EDMA_MAX_PARAMENTRY 512
-
#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
#define EDMA_CONT_PARAMS_ANY 1001
#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-#define EDMA_MAX_CC 2
-
/* PaRAM slots are laid out like this */
struct edmacc_param {
u32 opt;
@@ -256,22 +235,22 @@ struct edma_cc {
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
- DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+ unsigned long *edma_inuse;
/* The edma_unused bit for each channel is clear unless
* it is not being used on this platform. It uses a bit
* of SOC-specific initialization code.
*/
- DECLARE_BITMAP(edma_unused, EDMA_CHANS);
+ unsigned long *edma_unused;
struct dma_interrupt_data {
void (*callback)(unsigned channel, unsigned short ch_status,
void *data);
void *data;
- } intr_data[EDMA_CHANS];
+ } *intr_data;
struct dma_device dma_slave;
- struct edma_chan slave_chans[EDMA_CHANS];
+ struct edma_chan *slave_chans;
int dummy_slot;
};
@@ -457,6 +436,8 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
struct edma_cc *ecc = data;
+ int dma_req_min = EDMA_CTLR_CHAN(ecc->id, 0);
+ int dma_req_max = dma_req_min + ecc->num_channels;
int i, count;
struct of_phandle_args dma_spec;
@@ -491,11 +472,15 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
/* For non-OF case */
for (i = 0; i < pdev->num_resources; i++) {
struct resource *res = &pdev->resource[i];
+ int dma_req;
+
+ if (!(res->flags & IORESOURCE_DMA))
+ continue;
- if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) {
+ dma_req = (int)res->start;
+ if (dma_req >= dma_req_min && dma_req < dma_req_max)
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
ecc->edma_unused);
- }
}
return 0;
@@ -1978,7 +1963,7 @@ static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma,
{
int i, j;
- for (i = 0; i < EDMA_CHANS; i++) {
+ for (i = 0; i < ecc->num_channels; i++) {
struct edma_chan *echan = &echans[i];
echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
echan->ecc = ecc;
@@ -2247,6 +2232,27 @@ static int edma_probe(struct platform_device *pdev)
if (ret)
return ret;
+ /* Allocate memory based on the information we got from the IP */
+ ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
+ sizeof(*ecc->slave_chans), GFP_KERNEL);
+ if (!ecc->slave_chans)
+ return -ENOMEM;
+
+ ecc->intr_data = devm_kcalloc(dev, ecc->num_channels,
+ sizeof(*ecc->intr_data), GFP_KERNEL);
+ if (!ecc->intr_data)
+ return -ENOMEM;
+
+ ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels),
+ sizeof(unsigned long), GFP_KERNEL);
+ if (!ecc->edma_unused)
+ return -ENOMEM;
+
+ ecc->edma_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
+ sizeof(unsigned long), GFP_KERNEL);
+ if (!ecc->edma_inuse)
+ return -ENOMEM;
+
ecc->default_queue = info->default_queue;
for (i = 0; i < ecc->num_slots; i++)
--
2.6.1
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| From | Vinod Koul <vinod.koul@intel.com> |
|---|---|
| Date | 2015-10-14 16:30 +0200 |
| Message-ID | <qjve3-17o-37@gated-at.bofh.it> |
| In reply to | #1246586 |
On Wed, Oct 14, 2015 at 02:42:42PM +0300, Peter Ujfalusi wrote: > Hi, > > Cover letter: > > with this series the edma two driver setup will be changed to have only one > driver to support eDMA3. The legacy edma interface will be removed and eDMA can > only be used via dmaengine API from this point on. > In order to do the merge the following improvements has been done: > - One driver instance per eDMA: > - Any number of eDMA instances are supported (both legacy and DT boot) > - Not relying on global variables, arrays, etc > - Code simplification and optimizations in several places > > This change will also help us to do bigger changes in the eDMA driver since, > since now we have only one driver to work with. I have applied this now. I got a conlfict on 3rd one while applying and also I got conflict while merging to next Pls verify all is well! -- ~Vinod -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-10-15 09:20 +0200 |
| Message-ID | <qjKZs-7If-23@gated-at.bofh.it> |
| In reply to | #1246827 |
On 10/14/2015 05:31 PM, Vinod Koul wrote: > On Wed, Oct 14, 2015 at 02:42:42PM +0300, Peter Ujfalusi wrote: >> Hi, >> >> Cover letter: >> >> with this series the edma two driver setup will be changed to have only one >> driver to support eDMA3. The legacy edma interface will be removed and eDMA can >> only be used via dmaengine API from this point on. >> In order to do the merge the following improvements has been done: >> - One driver instance per eDMA: >> - Any number of eDMA instances are supported (both legacy and DT boot) >> - Not relying on global variables, arrays, etc >> - Code simplification and optimizations in several places >> >> This change will also help us to do bigger changes in the eDMA driver since, >> since now we have only one driver to work with. > > I have applied this now. I got a conlfict on 3rd one while applying and also > I got conflict while merging to next > > Pls verify all is well! Thanks Vinod, It looks fine. It is strange since I'm working on top of linux-next as well. The following commit caused the conflict: ddfe4d0cce78 dmaengine: edma: remove redundant conditions I have it in my linux-next, but for some reason it is missing from your topic/edma, so the series applied with conflicts there and when merging on top of linux-next there were again conflict. Thank you, Péter -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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