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[PATCH v5 22/24] dmaengine: edma: Read channel mapping support only once from HW

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Instead of directly reading it from CCCFG register take the information out
once when we set up the configuration from the HW.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 drivers/dma/edma.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index d105d1ae0f13..4b2ccc9de0ad 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -223,6 +223,7 @@ struct edma_cc {
 	unsigned			num_region;
 	unsigned			num_slots;
 	unsigned			num_tc;
+	bool				chmap_exist;
 	enum dma_event_q		default_queue;
 
 	bool				unused_chan_list_done;
@@ -1930,11 +1931,14 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
 	value = GET_NUM_EVQUE(cccfg);
 	ecc->num_tc = value + 1;
 
+	ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
+
 	dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
 	dev_dbg(dev, "num_region: %u\n", ecc->num_region);
 	dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
 	dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
 	dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
+	dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
 
 	/* Nothing need to be done if queue priority is provided */
 	if (pdata->queue_priority_mapping)
@@ -2223,7 +2227,7 @@ static int edma_probe(struct platform_device *pdev)
 					      queue_priority_mapping[i][1]);
 
 	/* Map the channel to param entry if channel mapping logic exist */
-	if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST)
+	if (ecc->chmap_exist)
 		edma_direct_dmach_to_param_mapping(ecc);
 
 	for (i = 0; i < ecc->num_region; i++) {
@@ -2293,7 +2297,7 @@ static int edma_pm_resume(struct device *dev)
 					      queue_priority_mapping[i][1]);
 
 	/* Map the channel to param entry if channel mapping logic */
-	if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST)
+	if (ecc->chmap_exist)
 		edma_direct_dmach_to_param_mapping(ecc);
 
 	for (i = 0; i < ecc->num_channels; i++) {
-- 
2.6.1

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Thread

[PATCH v5 00/24] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
  [PATCH v5 22/24] dmaengine: edma: Read channel mapping support only once from HW Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
  [PATCH v5 19/24] dmaengine: edma: Simplify the interrupt handling Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
  [PATCH v5 05/24] ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine driver Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
  [PATCH v5 15/24] dmaengine: edma: Use dev_dbg instead pr_debug Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
  [PATCH v5 21/24] dmaengine: edma: Simplify and optimize ccerr interrupt handler Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
  [PATCH v5 13/24] dmaengine: edma: Use devm_kcalloc when possible Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
  [PATCH v5 24/24] dmaengine: edma: Dynamic paRAM slot handling if HW supports it Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 13:50 +0200
  [PATCH v5 10/24] ARM: davinci: Add dma_mask to eDMA devices Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
  [PATCH v5 08/24] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
  [PATCH v5 07/24] ARM/dmaengine: edma: Public API to use private struct pointer Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
  [PATCH v5 02/24] ARM: common: edma: Remove unused functions Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
  [PATCH v5 12/24] dmaengine: edma: Allocate memory dynamically for bitmaps and structures Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-14 14:00 +0200
  Re: [PATCH v5 00/24] dmaengine/ARM: Merge the edma drivers into one Vinod Koul <vinod.koul@intel.com> - 2015-10-14 16:30 +0200
    Re: [PATCH v5 00/24] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-10-15 09:20 +0200

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