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Groups > linux.kernel > #1243029 > unrolled thread
| Started by | Leo Yan <leo.yan@linaro.org> |
|---|---|
| First post | 2015-10-09 06:40 +0200 |
| Last post | 2015-10-09 06:40 +0200 |
| Articles | 12 — 4 participants |
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[PATCH 0/4] arm64: Hi6220: enable CPU idle states Leo Yan <leo.yan@linaro.org> - 2015-10-09 06:40 +0200
[PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 Leo Yan <leo.yan@linaro.org> - 2015-10-09 06:40 +0200
Re: [PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 Rob Herring <robherring2@gmail.com> - 2015-10-09 15:20 +0200
Re: [PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 Mark Rutland <mark.rutland@arm.com> - 2015-10-09 15:40 +0200
Re: [PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 Rob Herring <robherring2@gmail.com> - 2015-10-09 16:00 +0200
Re: [PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 Leo Yan <leo.yan@linaro.org> - 2015-10-09 16:30 +0200
[PATCH 4/4] arm64: dts: enable idle states for Hi6220 Leo Yan <leo.yan@linaro.org> - 2015-10-09 06:40 +0200
Re: [PATCH 4/4] arm64: dts: enable idle states for Hi6220 Sudeep Holla <sudeep.holla@arm.com> - 2015-10-09 10:50 +0200
Re: [PATCH 4/4] arm64: dts: enable idle states for Hi6220 Leo Yan <leo.yan@linaro.org> - 2015-10-09 11:00 +0200
[PATCH 3/4] arm64: dts: add sp804 timer node for Hi6220 Leo Yan <leo.yan@linaro.org> - 2015-10-09 06:40 +0200
Re: [PATCH 3/4] arm64: dts: add sp804 timer node for Hi6220 Rob Herring <robherring2@gmail.com> - 2015-10-09 15:20 +0200
[PATCH 2/4] arm64: Kconfig: select sp804 timer for ARCH_HISI Leo Yan <leo.yan@linaro.org> - 2015-10-09 06:40 +0200
| From | Leo Yan <leo.yan@linaro.org> |
|---|---|
| Date | 2015-10-09 06:40 +0200 |
| Subject | [PATCH 0/4] arm64: Hi6220: enable CPU idle states |
| Message-ID | <qhxDk-8kk-5@gated-at.bofh.it> |
This patch series is to enable CPU idle states for Hi6220. Hi6220 uses PSCIv0.2 compliance interface, so directly use ARM's generic CPUIdle driver. Patch 1 is to reserve memory regions so make sure MCU can work well to handle power controlling; Patch 2/3 enable sp804 timer as broadcast timer during idle states; Patch 4 registers CPU power down state and cluster power down state. Leo Yan (4): arm64: dts: Reserve memory regions for hi6220 arm64: Kconfig: select sp804 timer for ARCH_HISI arm64: dts: add sp804 timer node for Hi6220 arm64: dts: enable idle states for Hi6220 arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 16 ++++++++--- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 40 ++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 4 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Leo Yan <leo.yan@linaro.org> |
|---|---|
| Date | 2015-10-09 06:40 +0200 |
| Subject | [PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 |
| Message-ID | <qhxDk-8kk-9@gated-at.bofh.it> |
| In reply to | #1243029 |
On Hi6220, below memory regions in DDR have specific purpose:
0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
0x06df,f000 - 0x06df,ffff: For mailbox message data;
0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
0x3e00,0000 - 0x3fff,ffff: For OP-TEE.
This patch reserves these memory regions in DT.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
index e36a539..e3f4cb3 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@@ -7,9 +7,6 @@
/dts-v1/;
-/*Reserved 1MB memory for MCU*/
-/memreserve/ 0x05e00000 0x00100000;
-
#include "hi6220.dtsi"
/ {
@@ -24,8 +21,19 @@
stdout-path = "serial0:115200n8";
};
+ /*
+ * Reserve below regions from memory node:
+ *
+ * - 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
+ * - 0x06df,f000 - 0x06df,ffff: Mailbox message data
+ * - 0x0740,f000 - 0x0740,ffff: MCU firmware section
+ * - 0x3e00,0000 - 0x3fff,ffff: OP-TEE
+ */
memory@0 {
device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
+ reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
+ <0x00000000 0x05f00000 0x00000000 0x00eff000>,
+ <0x00000000 0x06e00000 0x00000000 0x0060f000>,
+ <0x00000000 0x07410000 0x00000000 0x36bf0000>;
};
};
--
1.9.1
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| From | Rob Herring <robherring2@gmail.com> |
|---|---|
| Date | 2015-10-09 15:20 +0200 |
| Subject | Re: [PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 |
| Message-ID | <qhFKz-3bI-57@gated-at.bofh.it> |
| In reply to | #1243030 |
On Thu, Oct 8, 2015 at 11:36 PM, Leo Yan <leo.yan@linaro.org> wrote:
> On Hi6220, below memory regions in DDR have specific purpose:
>
> 0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
> 0x06df,f000 - 0x06df,ffff: For mailbox message data;
> 0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
> 0x3e00,0000 - 0x3fff,ffff: For OP-TEE.
>
> This patch reserves these memory regions in DT.
>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
> arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
> index e36a539..e3f4cb3 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
> @@ -7,9 +7,6 @@
>
> /dts-v1/;
>
> -/*Reserved 1MB memory for MCU*/
> -/memreserve/ 0x05e00000 0x00100000;
> -
Why does memreserve not work for you? You can have multiple entries.
> #include "hi6220.dtsi"
>
> / {
> @@ -24,8 +21,19 @@
> stdout-path = "serial0:115200n8";
> };
>
> + /*
> + * Reserve below regions from memory node:
> + *
> + * - 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
> + * - 0x06df,f000 - 0x06df,ffff: Mailbox message data
> + * - 0x0740,f000 - 0x0740,ffff: MCU firmware section
> + * - 0x3e00,0000 - 0x3fff,ffff: OP-TEE
> + */
> memory@0 {
> device_type = "memory";
> - reg = <0x0 0x0 0x0 0x40000000>;
> + reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
> + <0x00000000 0x05f00000 0x00000000 0x00eff000>,
> + <0x00000000 0x06e00000 0x00000000 0x0060f000>,
> + <0x00000000 0x07410000 0x00000000 0x36bf0000>;
No, don't do this. Please use memreserve or reserved-memory binding[1]
or combination of both. Probably reserved-memory if you need the
kernel to access some of these regions.
Rob
[1] Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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| From | Mark Rutland <mark.rutland@arm.com> |
|---|---|
| Date | 2015-10-09 15:40 +0200 |
| Subject | Re: [PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 |
| Message-ID | <qhG3T-3xZ-15@gated-at.bofh.it> |
| In reply to | #1243361 |
On Fri, Oct 09, 2015 at 08:17:16AM -0500, Rob Herring wrote:
> On Thu, Oct 8, 2015 at 11:36 PM, Leo Yan <leo.yan@linaro.org> wrote:
> > On Hi6220, below memory regions in DDR have specific purpose:
> >
> > 0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
> > 0x06df,f000 - 0x06df,ffff: For mailbox message data;
> > 0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
> > 0x3e00,0000 - 0x3fff,ffff: For OP-TEE.
> >
> > This patch reserves these memory regions in DT.
> >
> > Signed-off-by: Leo Yan <leo.yan@linaro.org>
> > ---
> > arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 16 ++++++++++++----
> > 1 file changed, 12 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
> > index e36a539..e3f4cb3 100644
> > --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
> > +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
> > @@ -7,9 +7,6 @@
> >
> > /dts-v1/;
> >
> > -/*Reserved 1MB memory for MCU*/
> > -/memreserve/ 0x05e00000 0x00100000;
> > -
>
> Why does memreserve not work for you? You can have multiple entries.
>
> > #include "hi6220.dtsi"
> >
> > / {
> > @@ -24,8 +21,19 @@
> > stdout-path = "serial0:115200n8";
> > };
> >
> > + /*
> > + * Reserve below regions from memory node:
> > + *
> > + * - 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
> > + * - 0x06df,f000 - 0x06df,ffff: Mailbox message data
> > + * - 0x0740,f000 - 0x0740,ffff: MCU firmware section
> > + * - 0x3e00,0000 - 0x3fff,ffff: OP-TEE
> > + */
> > memory@0 {
> > device_type = "memory";
> > - reg = <0x0 0x0 0x0 0x40000000>;
> > + reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
> > + <0x00000000 0x05f00000 0x00000000 0x00eff000>,
> > + <0x00000000 0x06e00000 0x00000000 0x0060f000>,
> > + <0x00000000 0x07410000 0x00000000 0x36bf0000>;
>
> No, don't do this. Please use memreserve or reserved-memory binding[1]
> or combination of both. Probably reserved-memory if you need the
> kernel to access some of these regions.
I disagree at least for those portions owned by the secure world. The
kernel shouldn't map those at all, so memreserve isn't appropriate. That
covers OP-TEE and the MCU firmware regions, and I'd expec the EFI memory
map to not list those as available to the kernel.
For the mailbox memory reserved-memory should be OK.
Thanks,
Mark.
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| From | Rob Herring <robherring2@gmail.com> |
|---|---|
| Date | 2015-10-09 16:00 +0200 |
| Subject | Re: [PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 |
| Message-ID | <qhGnf-3UO-13@gated-at.bofh.it> |
| In reply to | #1243372 |
On Fri, Oct 9, 2015 at 8:30 AM, Mark Rutland <mark.rutland@arm.com> wrote:
> On Fri, Oct 09, 2015 at 08:17:16AM -0500, Rob Herring wrote:
>> On Thu, Oct 8, 2015 at 11:36 PM, Leo Yan <leo.yan@linaro.org> wrote:
>> > On Hi6220, below memory regions in DDR have specific purpose:
>> >
>> > 0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
>> > 0x06df,f000 - 0x06df,ffff: For mailbox message data;
>> > 0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
>> > 0x3e00,0000 - 0x3fff,ffff: For OP-TEE.
>> >
>> > This patch reserves these memory regions in DT.
>> >
>> > Signed-off-by: Leo Yan <leo.yan@linaro.org>
>> > ---
>> > arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 16 ++++++++++++----
>> > 1 file changed, 12 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
>> > index e36a539..e3f4cb3 100644
>> > --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
>> > +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
>> > @@ -7,9 +7,6 @@
>> >
>> > /dts-v1/;
>> >
>> > -/*Reserved 1MB memory for MCU*/
>> > -/memreserve/ 0x05e00000 0x00100000;
>> > -
>>
>> Why does memreserve not work for you? You can have multiple entries.
>>
>> > #include "hi6220.dtsi"
>> >
>> > / {
>> > @@ -24,8 +21,19 @@
>> > stdout-path = "serial0:115200n8";
>> > };
>> >
>> > + /*
>> > + * Reserve below regions from memory node:
>> > + *
>> > + * - 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
>> > + * - 0x06df,f000 - 0x06df,ffff: Mailbox message data
>> > + * - 0x0740,f000 - 0x0740,ffff: MCU firmware section
>> > + * - 0x3e00,0000 - 0x3fff,ffff: OP-TEE
>> > + */
>> > memory@0 {
>> > device_type = "memory";
>> > - reg = <0x0 0x0 0x0 0x40000000>;
>> > + reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
>> > + <0x00000000 0x05f00000 0x00000000 0x00eff000>,
>> > + <0x00000000 0x06e00000 0x00000000 0x0060f000>,
>> > + <0x00000000 0x07410000 0x00000000 0x36bf0000>;
>>
>> No, don't do this. Please use memreserve or reserved-memory binding[1]
>> or combination of both. Probably reserved-memory if you need the
>> kernel to access some of these regions.
>
> I disagree at least for those portions owned by the secure world. The
> kernel shouldn't map those at all, so memreserve isn't appropriate. That
> covers OP-TEE and the MCU firmware regions, and I'd expec the EFI memory
> map to not list those as available to the kernel.
I'm fine carving out the beginning or end, but otherwise think memory
should correspond to the physical memory. We have a way to describe
holes to keep out, so we should use them. If secure world uses the DT,
then it would either want to know its region in memory or add the DT
data to say what it is using. We need that to be easy to find or easy
to set, respectively. The size secure world needs could vary as well.
The fact that the kernel maps the memory is the kernel's problem, not
a DT problem.
>
> For the mailbox memory reserved-memory should be OK.
That only gets us from 4 regions to 3.
Rob
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| From | Leo Yan <leo.yan@linaro.org> |
|---|---|
| Date | 2015-10-09 16:30 +0200 |
| Subject | Re: [PATCH 1/4] arm64: dts: Reserve memory regions for hi6220 |
| Message-ID | <qhGQk-4IM-45@gated-at.bofh.it> |
| In reply to | #1243390 |
Hi Rob,
On Fri, Oct 09, 2015 at 08:50:13AM -0500, Rob Herring wrote:
> On Fri, Oct 9, 2015 at 8:30 AM, Mark Rutland <mark.rutland@arm.com> wrote:
> > On Fri, Oct 09, 2015 at 08:17:16AM -0500, Rob Herring wrote:
> >> On Thu, Oct 8, 2015 at 11:36 PM, Leo Yan <leo.yan@linaro.org> wrote:
> >> > On Hi6220, below memory regions in DDR have specific purpose:
> >> >
> >> > 0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
> >> > 0x06df,f000 - 0x06df,ffff: For mailbox message data;
> >> > 0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
> >> > 0x3e00,0000 - 0x3fff,ffff: For OP-TEE.
> >> >
> >> > This patch reserves these memory regions in DT.
> >> >
> >> > Signed-off-by: Leo Yan <leo.yan@linaro.org>
> >> > ---
> >> > arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 16 ++++++++++++----
> >> > 1 file changed, 12 insertions(+), 4 deletions(-)
> >> >
> >> > diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
> >> > index e36a539..e3f4cb3 100644
> >> > --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
> >> > +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
> >> > @@ -7,9 +7,6 @@
> >> >
> >> > /dts-v1/;
> >> >
> >> > -/*Reserved 1MB memory for MCU*/
> >> > -/memreserve/ 0x05e00000 0x00100000;
> >> > -
> >>
> >> Why does memreserve not work for you? You can have multiple entries.
> >>
> >> > #include "hi6220.dtsi"
> >> >
> >> > / {
> >> > @@ -24,8 +21,19 @@
> >> > stdout-path = "serial0:115200n8";
> >> > };
> >> >
> >> > + /*
> >> > + * Reserve below regions from memory node:
> >> > + *
> >> > + * - 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
> >> > + * - 0x06df,f000 - 0x06df,ffff: Mailbox message data
> >> > + * - 0x0740,f000 - 0x0740,ffff: MCU firmware section
> >> > + * - 0x3e00,0000 - 0x3fff,ffff: OP-TEE
> >> > + */
> >> > memory@0 {
> >> > device_type = "memory";
> >> > - reg = <0x0 0x0 0x0 0x40000000>;
> >> > + reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
> >> > + <0x00000000 0x05f00000 0x00000000 0x00eff000>,
> >> > + <0x00000000 0x06e00000 0x00000000 0x0060f000>,
> >> > + <0x00000000 0x07410000 0x00000000 0x36bf0000>;
> >>
> >> No, don't do this. Please use memreserve or reserved-memory binding[1]
> >> or combination of both. Probably reserved-memory if you need the
> >> kernel to access some of these regions.
> >
> > I disagree at least for those portions owned by the secure world. The
> > kernel shouldn't map those at all, so memreserve isn't appropriate. That
> > covers OP-TEE and the MCU firmware regions, and I'd expec the EFI memory
> > map to not list those as available to the kernel.
>
> I'm fine carving out the beginning or end, but otherwise think memory
> should correspond to the physical memory. We have a way to describe
> holes to keep out, so we should use them. If secure world uses the DT,
> then it would either want to know its region in memory or add the DT
> data to say what it is using. We need that to be easy to find or easy
> to set, respectively. The size secure world needs could vary as well.
>
> The fact that the kernel maps the memory is the kernel's problem, not
> a DT problem.
>
Just give more input here. In previous time, we have long discussion [1];
So actually your suggestion is exactly same what my old patch.
From previous discussion, i think here have an assumtion: Use UEFI as
bootloader, the kernel will ignore (or remove) memreserve and reserved-memory
nodes, so just like Mark said "the EFI memory map to not list those
as available to the kernel". My new patch is just to follow this and
also make sure they have same behavior for different bootloader
(between UEFI and uboot).
[1] http://archive.arm.linux.org.uk/lurker/thread/20150819.093735.59724a58.en.html#i20150819.093735.59724a58
Thanks,
Leo Yan
> >
> > For the mailbox memory reserved-memory should be OK.
>
> That only gets us from 4 regions to 3.
>
> Rob
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| From | Leo Yan <leo.yan@linaro.org> |
|---|---|
| Date | 2015-10-09 06:40 +0200 |
| Subject | [PATCH 4/4] arm64: dts: enable idle states for Hi6220 |
| Message-ID | <qhxDk-8kk-13@gated-at.bofh.it> |
| In reply to | #1243029 |
Add cpu and cluster level's low power state for Hi6220.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 7edbe42..e83802a 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -52,11 +52,35 @@
};
};
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <700>;
+ exit-latency-us = <250>;
+ min-residency-us = <1000>;
+ };
+
+ CLUSTER_SLEEP: cluster-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+ };
+
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu1: cpu@1 {
@@ -64,6 +88,7 @@
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu2: cpu@2 {
@@ -71,6 +96,7 @@
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu3: cpu@3 {
@@ -78,6 +104,7 @@
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu4: cpu@100 {
@@ -85,6 +112,7 @@
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu5: cpu@101 {
@@ -92,6 +120,7 @@
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu6: cpu@102 {
@@ -99,6 +128,7 @@
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu7: cpu@103 {
@@ -106,6 +136,7 @@
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
};
--
1.9.1
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| From | Sudeep Holla <sudeep.holla@arm.com> |
|---|---|
| Date | 2015-10-09 10:50 +0200 |
| Subject | Re: [PATCH 4/4] arm64: dts: enable idle states for Hi6220 |
| Message-ID | <qhBxh-5rH-27@gated-at.bofh.it> |
| In reply to | #1243032 |
On 09/10/15 05:36, Leo Yan wrote:
> Add cpu and cluster level's low power state for Hi6220.
>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> index 7edbe42..e83802a 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> @@ -52,11 +52,35 @@
> };
> };
>
> + idle-states {
> + entry-method = "arm,psci";
Please refer the bindings: ^ should be just "psci"
Otherwise looks good.
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Regards,
Sudeep
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| From | Leo Yan <leo.yan@linaro.org> |
|---|---|
| Date | 2015-10-09 11:00 +0200 |
| Subject | Re: [PATCH 4/4] arm64: dts: enable idle states for Hi6220 |
| Message-ID | <qhBGW-5Da-21@gated-at.bofh.it> |
| In reply to | #1243140 |
Hi Sudeep,
On Fri, Oct 09, 2015 at 09:48:17AM +0100, Sudeep Holla wrote:
>
>
> On 09/10/15 05:36, Leo Yan wrote:
> >Add cpu and cluster level's low power state for Hi6220.
> >
> >Signed-off-by: Leo Yan <leo.yan@linaro.org>
> >---
> > arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 31 +++++++++++++++++++++++++++++++
> > 1 file changed, 31 insertions(+)
> >
> >diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> >index 7edbe42..e83802a 100644
> >--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> >+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> >@@ -52,11 +52,35 @@
> > };
> > };
> >
> >+ idle-states {
> >+ entry-method = "arm,psci";
>
> Please refer the bindings: ^ should be just "psci"
>
> Otherwise looks good.
> Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Will fix it, thanks for review.
Thanks,
Leo Yan
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| From | Leo Yan <leo.yan@linaro.org> |
|---|---|
| Date | 2015-10-09 06:40 +0200 |
| Subject | [PATCH 3/4] arm64: dts: add sp804 timer node for Hi6220 |
| Message-ID | <qhxDk-8kk-15@gated-at.bofh.it> |
| In reply to | #1243029 |
Add sp804 timer for hi6220, so it can be used as broadcast timer.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 3f03380..7edbe42 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -167,5 +167,14 @@
clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
clock-names = "uartclk", "apb_pclk";
};
+
+ dual_timer0: dual_timer@f8008000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0x0 0xf8008000 0x0 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ao_ctrl 27>, <&ao_ctrl 27>;
+ clock-names = "apb_pclk", "apb_pclk";
+ };
};
};
--
1.9.1
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| From | Rob Herring <robherring2@gmail.com> |
|---|---|
| Date | 2015-10-09 15:20 +0200 |
| Subject | Re: [PATCH 3/4] arm64: dts: add sp804 timer node for Hi6220 |
| Message-ID | <qhFKx-3bI-13@gated-at.bofh.it> |
| In reply to | #1243033 |
On Thu, Oct 8, 2015 at 11:36 PM, Leo Yan <leo.yan@linaro.org> wrote:
> Add sp804 timer for hi6220, so it can be used as broadcast timer.
>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
> arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> index 3f03380..7edbe42 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> @@ -167,5 +167,14 @@
> clocks = <&ao_ctrl 36>, <&ao_ctrl 36>;
> clock-names = "uartclk", "apb_pclk";
> };
> +
> + dual_timer0: dual_timer@f8008000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0x0 0xf8008000 0x0 0x1000>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ao_ctrl 27>, <&ao_ctrl 27>;
> + clock-names = "apb_pclk", "apb_pclk";
These should not have the same name and should be 3 clocks. The
binding doc is not clear what the names should be, but follow the
example.
The vexpress-v2p-ca9, hi3620 and hip04 are wrong too (in different ways).
Rob
> + };
> };
> };
> --
> 1.9.1
>
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| From | Leo Yan <leo.yan@linaro.org> |
|---|---|
| Date | 2015-10-09 06:40 +0200 |
| Subject | [PATCH 2/4] arm64: Kconfig: select sp804 timer for ARCH_HISI |
| Message-ID | <qhxDk-8kk-17@gated-at.bofh.it> |
| In reply to | #1243029 |
Select sp804 timer for ARCH_HISI, which is used as broadcast timer. Signed-off-by: Leo Yan <leo.yan@linaro.org> --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 23800a1..6d730fb 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -35,6 +35,7 @@ config ARCH_FSL_LS2085A config ARCH_HISI bool "Hisilicon SoC Family" + select ARM_TIMER_SP804 help This enables support for Hisilicon ARMv8 SoC family -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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