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Groups > linux.kernel > #1234091 > unrolled thread
| Started by | Peter Griffin <peter.griffin@linaro.org> |
|---|---|
| First post | 2015-09-28 14:40 +0200 |
| Last post | 2015-09-30 10:40 +0200 |
| Articles | 10 — 3 participants |
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[PATCH v2 00/11] Hi Maxime / Patrice / Srini, Peter Griffin <peter.griffin@linaro.org> - 2015-09-28 14:40 +0200
[PATCH v2 06/11] ARM: DT: STiH407: Add NAND flash controller pin configuration Peter Griffin <peter.griffin@linaro.org> - 2015-09-28 14:40 +0200
[PATCH v2 04/11] ARM: DT: STiH407: Add serial3 pinctrl configuration Peter Griffin <peter.griffin@linaro.org> - 2015-09-28 14:40 +0200
[PATCH v2 03/11] ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs Peter Griffin <peter.griffin@linaro.org> - 2015-09-28 14:40 +0200
[PATCH v2 05/11] ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config Peter Griffin <peter.griffin@linaro.org> - 2015-09-28 14:40 +0200
[PATCH v2 09/11] ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX Peter Griffin <peter.griffin@linaro.org> - 2015-09-28 14:50 +0200
[PATCH v2 02/11] ARM: STi: DT: STiH407: Add i2c3 alternate pin configs Peter Griffin <peter.griffin@linaro.org> - 2015-09-28 14:50 +0200
Re: [PATCH v2 00/11] Hi Maxime / Patrice / Srini, Lee Jones <lee.jones@linaro.org> - 2015-09-28 17:40 +0200
Re: [PATCH v2 00/11] Hi Maxime / Patrice / Srini, Lee Jones <lee.jones@linaro.org> - 2015-09-28 17:50 +0200
Re: [PATCH v2 00/11] Hi Maxime / Patrice / Srini, Maxime Coquelin <maxime.coquelin@st.com> - 2015-09-30 10:40 +0200
| From | Peter Griffin <peter.griffin@linaro.org> |
|---|---|
| Date | 2015-09-28 14:40 +0200 |
| Subject | [PATCH v2 00/11] Hi Maxime / Patrice / Srini, |
| Message-ID | <qdFSN-5O5-3@gated-at.bofh.it> |
This series makes a series of updates to the stih407 pinctrl groups and makes the upstream kernel more closely aligned in terms of pin configuration to the vendor kernel. A number of new periphs are added such as spi fsm, nand, cec0, and for others such as SPI the various alternate function pin muxings have been added. Finally for SPI the controller nodes have been updated to have the default pin assignment in the controller node. Changes since v1: - Rebase on v4.3-rc3 - Remove some SoBs (Lee) - Collect up Acks kind regards, Peter. Peter Griffin (11): ARM: STi: DT: STiH407: Add a cec0 pin definition ARM: STi: DT: STiH407: Add i2c3 alternate pin configs ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs ARM: DT: STiH407: Add serial3 pinctrl configuration ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config ARM: DT: STiH407: Add NAND flash controller pin configuration ARM: DT: STiH407: Add systrace pin configuration ARM: DT: STiH407: Add SD pinctrl config for mmc0 controller ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX ARM: DT: STiH407: Add RMII pinctrl support ARM: STi: STiH407: Add spi default pinctrl groups. arch/arm/boot/dts/stih407-family.dtsi | 14 ++ arch/arm/boot/dts/stih407-pinctrl.dtsi | 378 ++++++++++++++++++++++++++++++++- 2 files changed, 387 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Peter Griffin <peter.griffin@linaro.org> |
|---|---|
| Date | 2015-09-28 14:40 +0200 |
| Subject | [PATCH v2 06/11] ARM: DT: STiH407: Add NAND flash controller pin configuration |
| Message-ID | <qdFSP-5O5-25@gated-at.bofh.it> |
| In reply to | #1234091 |
This patch adds NAND flash support controller pin configuration
for STiH407 family silicon.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index b7a405f..d281f9c 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -1085,6 +1085,29 @@
};
};
};
+
+ nand {
+ pinctrl_nand: nand {
+ st,pins {
+ nand_cs1 = <&pio40 6 ALT3 OUT>;
+ nand_cs0 = <&pio40 7 ALT3 OUT>;
+ nand_d0 = <&pio41 0 ALT3 BIDIR>;
+ nand_d1 = <&pio41 1 ALT3 BIDIR>;
+ nand_d2 = <&pio41 2 ALT3 BIDIR>;
+ nand_d3 = <&pio41 3 ALT3 BIDIR>;
+ nand_d4 = <&pio41 4 ALT3 BIDIR>;
+ nand_d5 = <&pio41 5 ALT3 BIDIR>;
+ nand_d6 = <&pio41 6 ALT3 BIDIR>;
+ nand_d7 = <&pio41 7 ALT3 BIDIR>;
+ nand_we = <&pio42 0 ALT3 OUT>;
+ nand_dqs = <&pio42 1 ALT3 OUT>;
+ nand_ale = <&pio42 2 ALT3 OUT>;
+ nand_cle = <&pio42 3 ALT3 OUT>;
+ nand_rnb = <&pio42 4 ALT3 IN>;
+ nand_oe = <&pio42 5 ALT3 OUT>;
+ };
+ };
+ };
};
};
};
--
1.9.1
--
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| From | Peter Griffin <peter.griffin@linaro.org> |
|---|---|
| Date | 2015-09-28 14:40 +0200 |
| Subject | [PATCH v2 04/11] ARM: DT: STiH407: Add serial3 pinctrl configuration |
| Message-ID | <qdFSP-5O5-29@gated-at.bofh.it> |
| In reply to | #1234091 |
Add missing serial 3 pinctrl config. This can be used
on b2206 HVK, where it defaults to PIO31[3] & PIO31[4],
alternate 1.
Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Acked-by: Carmelo Amoroso <carmelo.amoroso@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 2248e44..5d725fe 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -1009,6 +1009,15 @@
};
};
};
+
+ serial3 {
+ pinctrl_serial3: serial3-0 {
+ st,pins {
+ tx = <&pio31 3 ALT1 OUT>;
+ rx = <&pio31 4 ALT1 IN>;
+ };
+ };
+ };
};
pin-controller-flash {
--
1.9.1
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| From | Peter Griffin <peter.griffin@linaro.org> |
|---|---|
| Date | 2015-09-28 14:40 +0200 |
| Subject | [PATCH v2 03/11] ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs |
| Message-ID | <qdFSP-5O5-33@gated-at.bofh.it> |
| In reply to | #1234091 |
This patch adds the spi pinctrl configurations for all SPI
controllers, and also the alternate muxings which
can be used depending on board design.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 239 ++++++++++++++++++++++++++++++++-
1 file changed, 235 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 135920e..2248e44 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -262,6 +262,57 @@
};
};
};
+
+ spi10 {
+ pinctrl_spi10_default: spi10-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio4 6 ALT1 OUT>;
+ mrst = <&pio4 7 ALT1 IN>;
+ scl = <&pio4 5 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio4 6 ALT1 BIDIR_PU>;
+ scl = <&pio4 5 ALT1 OUT>;
+ };
+ };
+ };
+
+ spi11 {
+ pinctrl_spi11_default: spi11-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio3 1 ALT2 OUT>;
+ mrst = <&pio3 0 ALT2 IN>;
+ scl = <&pio3 2 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
+ st,pins {
+ mtsr = <&pio3 1 ALT2 BIDIR_PU>;
+ scl = <&pio3 2 ALT2 OUT>;
+ };
+ };
+ };
+
+ spi12 {
+ pinctrl_spi12_default: spi12-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio3 6 ALT2 OUT>;
+ mrst = <&pio3 4 ALT2 IN>;
+ scl = <&pio3 7 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
+ st,pins {
+ mtsr = <&pio3 6 ALT2 BIDIR_PU>;
+ scl = <&pio3 7 ALT2 OUT>;
+ };
+ };
+ };
};
pin-controller-front0 {
@@ -451,11 +502,159 @@
};
spi0 {
- pinctrl_spi0_default: spi0-default {
+ pinctrl_spi0_default: spi0-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio10 6 ALT2 OUT>;
+ mrst = <&pio10 7 ALT2 IN>;
+ scl = <&pio10 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
st,pins {
- mtsr = <&pio12 6 ALT2 BIDIR>;
- mrst = <&pio12 7 ALT2 BIDIR>;
- scl = <&pio12 5 ALT2 BIDIR>;
+ mtsr = <&pio10 6 ALT2 BIDIR_PU>;
+ scl = <&pio10 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio19 7 ALT1 OUT>;
+ mrst = <&pio19 5 ALT1 IN>;
+ scl = <&pio19 6 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio19 7 ALT1 BIDIR_PU>;
+ scl = <&pio19 6 ALT1 OUT>;
+ };
+ };
+ };
+
+ spi1 {
+ pinctrl_spi1_default: spi1-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio11 1 ALT2 OUT>;
+ mrst = <&pio11 2 ALT2 IN>;
+ scl = <&pio11 0 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
+ st,pins {
+ mtsr = <&pio11 1 ALT2 BIDIR_PU>;
+ scl = <&pio11 0 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio14 3 ALT1 OUT>;
+ mrst = <&pio14 4 ALT1 IN>;
+ scl = <&pio14 2 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio14 3 ALT1 BIDIR_PU>;
+ scl = <&pio14 2 ALT1 OUT>;
+ };
+ };
+ };
+
+ spi2 {
+ pinctrl_spi2_default: spi2-4w-alt2-0 {
+ st,pins {
+ mtsr = <&pio12 6 ALT2 OUT>;
+ mrst = <&pio12 7 ALT2 IN>;
+ scl = <&pio12 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
+ st,pins {
+ mtsr = <&pio12 6 ALT2 BIDIR_PU>;
+ scl = <&pio12 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio14 6 ALT1 OUT>;
+ mrst = <&pio14 7 ALT1 IN>;
+ scl = <&pio14 5 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio14 6 ALT1 BIDIR_PU>;
+ scl = <&pio14 5 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
+ st,pins {
+ mtsr = <&pio15 6 ALT2 OUT>;
+ mrst = <&pio15 7 ALT2 IN>;
+ scl = <&pio15 5 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
+ st,pins {
+ mtsr = <&pio15 6 ALT2 BIDIR_PU>;
+ scl = <&pio15 5 ALT2 OUT>;
+ };
+ };
+ };
+
+ spi3 {
+ pinctrl_spi3_default: spi3-4w-alt3-0 {
+ st,pins {
+ mtsr = <&pio13 6 ALT3 OUT>;
+ mrst = <&pio13 7 ALT3 IN>;
+ scl = <&pio13 5 ALT3 OUT>;
+ };
+ };
+
+ pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
+ st,pins {
+ mtsr = <&pio13 6 ALT3 BIDIR_PU>;
+ scl = <&pio13 5 ALT3 OUT>;
+ };
+ };
+
+ pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio17 7 ALT1 OUT>;
+ mrst = <&pio17 5 ALT1 IN>;
+ scl = <&pio17 6 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio17 7 ALT1 BIDIR_PU>;
+ scl = <&pio17 6 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
+ st,pins {
+ mtsr = <&pio18 6 ALT1 OUT>;
+ mrst = <&pio18 7 ALT1 IN>;
+ scl = <&pio18 5 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
+ st,pins {
+ mtsr = <&pio18 6 ALT1 BIDIR_PU>;
+ scl = <&pio18 5 ALT1 OUT>;
};
};
};
@@ -778,6 +977,38 @@
};
};
};
+
+ spi4 {
+ pinctrl_spi4_default: spi4-4w-alt1-0 {
+ st,pins {
+ mtsr = <&pio30 1 ALT1 OUT>;
+ mrst = <&pio30 2 ALT1 IN>;
+ scl = <&pio30 0 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
+ st,pins {
+ mtsr = <&pio30 1 ALT1 BIDIR_PU>;
+ scl = <&pio30 0 ALT1 OUT>;
+ };
+ };
+
+ pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
+ st,pins {
+ mtsr = <&pio34 1 ALT3 OUT>;
+ mrst = <&pio34 2 ALT3 IN>;
+ scl = <&pio34 0 ALT3 OUT>;
+ };
+ };
+
+ pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
+ st,pins {
+ mtsr = <&pio34 1 ALT3 BIDIR_PU>;
+ scl = <&pio34 0 ALT3 OUT>;
+ };
+ };
+ };
};
pin-controller-flash {
--
1.9.1
--
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| From | Peter Griffin <peter.griffin@linaro.org> |
|---|---|
| Date | 2015-09-28 14:40 +0200 |
| Subject | [PATCH v2 05/11] ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config |
| Message-ID | <qdFSP-5O5-41@gated-at.bofh.it> |
| In reply to | #1234091 |
This patch adds the pin configuration for the NOR flash controller.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 5d725fe..b7a405f 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -1072,6 +1072,19 @@
};
};
};
+
+ fsm {
+ pinctrl_fsm: fsm {
+ st,pins {
+ spi-fsm-clk = <&pio40 1 ALT1 OUT>;
+ spi-fsm-cs = <&pio40 0 ALT1 OUT>;
+ spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
+ spi-fsm-miso = <&pio40 3 ALT1 IN>;
+ spi-fsm-hol = <&pio40 5 ALT1 OUT>;
+ spi-fsm-wp = <&pio40 4 ALT1 OUT>;
+ };
+ };
+ };
};
};
};
--
1.9.1
--
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| From | Peter Griffin <peter.griffin@linaro.org> |
|---|---|
| Date | 2015-09-28 14:50 +0200 |
| Subject | [PATCH v2 09/11] ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX |
| Message-ID | <qdG2u-5Zh-19@gated-at.bofh.it> |
| In reply to | #1234091 |
This patch adds the pinconfig for IRB TX and IRB UHF.
Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 352fe98..9daab1f 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -121,6 +121,24 @@
ir = <&pio4 0 ALT2 IN>;
};
};
+
+ pinctrl_uhf: uhf0 {
+ st,pins {
+ ir = <&pio4 1 ALT2 IN>;
+ };
+ };
+
+ pinctrl_tx: tx0 {
+ st,pins {
+ tx = <&pio4 2 ALT2 OUT>;
+ };
+ };
+
+ pinctrl_tx_od: tx_od0 {
+ st,pins {
+ tx_od = <&pio4 3 ALT2 OUT>;
+ };
+ };
};
/* SBC_ASC0 - UART10 */
--
1.9.1
--
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| From | Peter Griffin <peter.griffin@linaro.org> |
|---|---|
| Date | 2015-09-28 14:50 +0200 |
| Subject | [PATCH v2 02/11] ARM: STi: DT: STiH407: Add i2c3 alternate pin configs |
| Message-ID | <qdG2v-5Zh-37@gated-at.bofh.it> |
| In reply to | #1234091 |
i2c3 controller can use several sets of pins depending
on board design. This patch adds the missing alternate
pinconfigs.
Signed-off-by: Seraphin Bonnaffe <seraphin.bonnaffe@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 30db453..135920e 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -430,12 +430,24 @@
};
i2c3 {
- pinctrl_i2c3_default: i2c3-default {
+ pinctrl_i2c3_default: i2c3-alt1-0 {
st,pins {
sda = <&pio18 6 ALT1 BIDIR>;
scl = <&pio18 5 ALT1 BIDIR>;
};
};
+ pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
+ st,pins {
+ sda = <&pio17 7 ALT1 BIDIR>;
+ scl = <&pio17 6 ALT1 BIDIR>;
+ };
+ };
+ pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
+ st,pins {
+ sda = <&pio13 6 ALT3 BIDIR>;
+ scl = <&pio13 5 ALT3 BIDIR>;
+ };
+ };
};
spi0 {
--
1.9.1
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| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2015-09-28 17:40 +0200 |
| Message-ID | <qdIH0-3xT-5@gated-at.bofh.it> |
| In reply to | #1234091 |
On Mon, 28 Sep 2015, Peter Griffin wrote: > This series makes a series of updates to the stih407 pinctrl groups > and makes the upstream kernel more closely aligned in terms of pin > configuration to the vendor kernel. > > A number of new periphs are added such as spi fsm, nand, cec0, and > for others such as SPI the various alternate function pin muxings have > been added. Finally for SPI the controller nodes have been updated > to have the default pin assignment in the controller node. > > Changes since v1: > - Rebase on v4.3-rc3 > - Remove some SoBs (Lee) > - Collect up Acks > > kind regards, > > Peter. > > Peter Griffin (11): > ARM: STi: DT: STiH407: Add a cec0 pin definition > ARM: STi: DT: STiH407: Add i2c3 alternate pin configs > ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs > ARM: DT: STiH407: Add serial3 pinctrl configuration > ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config > ARM: DT: STiH407: Add NAND flash controller pin configuration > ARM: DT: STiH407: Add systrace pin configuration > ARM: DT: STiH407: Add SD pinctrl config for mmc0 controller > ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX > ARM: DT: STiH407: Add RMII pinctrl support > ARM: STi: STiH407: Add spi default pinctrl groups. > > arch/arm/boot/dts/stih407-family.dtsi | 14 ++ > arch/arm/boot/dts/stih407-pinctrl.dtsi | 378 ++++++++++++++++++++++++++++++++- > 2 files changed, 387 insertions(+), 5 deletions(-) I'll do this privately, so as not to unnecessarily delay the acceptance of the set. I'm a big fan of keeping the *-by's in chronological order. It does help to provide an insight to the history of the patch. -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Lee Jones <lee.jones@linaro.org> |
|---|---|
| Date | 2015-09-28 17:50 +0200 |
| Message-ID | <qdIQF-3Jd-7@gated-at.bofh.it> |
| In reply to | #1234255 |
On Mon, 28 Sep 2015, Lee Jones wrote: > On Mon, 28 Sep 2015, Peter Griffin wrote: > > > This series makes a series of updates to the stih407 pinctrl groups > > and makes the upstream kernel more closely aligned in terms of pin > > configuration to the vendor kernel. > > > > A number of new periphs are added such as spi fsm, nand, cec0, and > > for others such as SPI the various alternate function pin muxings have > > been added. Finally for SPI the controller nodes have been updated > > to have the default pin assignment in the controller node. > > > > Changes since v1: > > - Rebase on v4.3-rc3 > > - Remove some SoBs (Lee) > > - Collect up Acks > > > > kind regards, > > > > Peter. > > > > Peter Griffin (11): > > ARM: STi: DT: STiH407: Add a cec0 pin definition > > ARM: STi: DT: STiH407: Add i2c3 alternate pin configs > > ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs > > ARM: DT: STiH407: Add serial3 pinctrl configuration > > ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config > > ARM: DT: STiH407: Add NAND flash controller pin configuration > > ARM: DT: STiH407: Add systrace pin configuration > > ARM: DT: STiH407: Add SD pinctrl config for mmc0 controller > > ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX > > ARM: DT: STiH407: Add RMII pinctrl support > > ARM: STi: STiH407: Add spi default pinctrl groups. > > > > arch/arm/boot/dts/stih407-family.dtsi | 14 ++ > > arch/arm/boot/dts/stih407-pinctrl.dtsi | 378 ++++++++++++++++++++++++++++++++- > > 2 files changed, 387 insertions(+), 5 deletions(-) > > I'll do this privately, so as not to unnecessarily delay the > acceptance of the set. Whoops! Fingers faster than brain. Sorry folks. Maxime, Please do not slow up the acceptance of this set due to my comments. > I'm a big fan of keeping the *-by's in chronological order. It does > help to provide an insight to the history of the patch. -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Maxime Coquelin <maxime.coquelin@st.com> |
|---|---|
| Date | 2015-09-30 10:40 +0200 |
| Message-ID | <qel5E-85q-15@gated-at.bofh.it> |
| In reply to | #1234091 |
Hi Peter, On 09/28/2015 02:37 PM, Peter Griffin wrote: > This series makes a series of updates to the stih407 pinctrl groups > and makes the upstream kernel more closely aligned in terms of pin > configuration to the vendor kernel. > > A number of new periphs are added such as spi fsm, nand, cec0, and > for others such as SPI the various alternate function pin muxings have > been added. Finally for SPI the controller nodes have been updated > to have the default pin assignment in the controller node. > > Changes since v1: > - Rebase on v4.3-rc3 > - Remove some SoBs (Lee) > - Collect up Acks > > kind regards, > > Peter. > > Peter Griffin (11): > ARM: STi: DT: STiH407: Add a cec0 pin definition > ARM: STi: DT: STiH407: Add i2c3 alternate pin configs > ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs > ARM: DT: STiH407: Add serial3 pinctrl configuration > ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config > ARM: DT: STiH407: Add NAND flash controller pin configuration > ARM: DT: STiH407: Add systrace pin configuration > ARM: DT: STiH407: Add SD pinctrl config for mmc0 controller > ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX > ARM: DT: STiH407: Add RMII pinctrl support > ARM: STi: STiH407: Add spi default pinctrl groups. > > arch/arm/boot/dts/stih407-family.dtsi | 14 ++ > arch/arm/boot/dts/stih407-pinctrl.dtsi | 378 ++++++++++++++++++++++++++++++++- > 2 files changed, 387 insertions(+), 5 deletions(-) > Series applied to sti-dt-for-v4.4. Thanks! Maxime -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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