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[PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes

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  [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware  reset and HS-DDR for eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Hans de Goede <hdegoede@redhat.com> - 2016-01-21 12:20 +0100
        Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 13:30 +0100
          Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Hans de Goede <hdegoede@redhat.com> - 2016-01-21 13:30 +0100
            Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 13:30 +0100
              Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Hans de Goede <hdegoede@redhat.com> - 2016-01-21 13:40 +0100
      Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:40 +0100
        Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-23 05:30 +0100
          Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc  compatible Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:50 +0100
        Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible Chen-Yu Tsai <wens@csie.org> - 2016-01-23 12:00 +0100
    [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset  and HS-DDR for eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:50 +0100
    [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in  mmc2_8bit_pins Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 01/15] mmc: sunxi: Document host init sequence Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in  mmc2_8bit_pins Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 07/15] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Hans de Goede <hdegoede@redhat.com> - 2016-01-21 12:20 +0100
        Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 13:00 +0100
          Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Hans de Goede <hdegoede@redhat.com> - 2016-01-21 13:30 +0100
    [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:40 +0100
        Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Chen-Yu Tsai <wens@csie.org> - 2016-01-23 12:10 +0100
          Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware  reset and HS-DDR for eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    Re: [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC  DDR modes Hans de Goede <hdegoede@redhat.com> - 2016-01-21 12:20 +0100

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#1313906 — [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes

Hi everyone,

This series adds support for vqmmc regulator and eMMC DDR modes for
sunxi-mmc. Allwinner's MMC controller supports eMMC 4.41 on earlier
SoCs, and up to 5.0 on latest ones. UHS-1 modes are also supported
by the hardware, but these are not covered in this series, as no
boards have dedicated regulators for vqmmc.

To support these faster modes, these patches adds vqmmc regulator
support, which is used by the mmc core to switch to faster modes,
even if the signaling voltage is fixed. Signal voltage switching
support is also added, but not tested, as no available hardware has
a dedicated vqmmc regulator.

Support for eMMC reset in the controller, vs a GPIO and pwrseq, is
also added where applicable.

Patch 1 documents the mmc host init sequence. When the driver was
ported, this part was copied verbatim and not documented. With inline
comments from later SDKs and datasheet register definitions, this part
is now clearer.

Patch 2 makes the .set_ios callback return on errors from
mmc_regulator_set_ocr.

Patch 3 adds support (enabling/disable, and voltage control) for vqmmc
regulator to sunxi-mmc.

Patch 4 adds support signal voltage switch for the mmc controller. The
Allwinner MMC controller uses a special bit for sending signal voltage
switching command.

Patch 5 adds timing delays for MMC_DDR52 mode.

Patch 6 adds support for 8 bit eMMC DDR52 mode. Under this mode, the
controller must run at twice the card clock, and different timing delays
are needed.

Patch 7 enables eMMC HS-DDR for sunxi-mmc.

Patch 8 adds mmc3 pins for 8 bit emmc for A31/A31s.

Patch 9 switches from mmc2 to mmc3 for the onboard eMMC on Sinlinx
SinA31s. According to Allwinner, only mmc3 supports eMMC DDR52 on
A31/A31s.

Patch 10 adds the eMMC reset pin to the emmc pingroup for A23/A33.

Patch 11 enables eMMC hardware reset and eMMC DDR52 mode for SinA33.

Patch 12 switches A80 to sun9i specific mmc compatible. A80 has different
timing delays, and a larger FIFO (TODO).

Patch 13 adds the eMMC reset pin to the emmc pingroup for A80.

Patch 14 enables eMMC hardware reset and eMMC DDR52 mode for A80 Optimus.

Patch 15 enables eMMC hardware reset and eMMC DDR52 mode for Cubieboard4.

Chen-Yu Tsai (15):
  mmc: sunxi: Document host init sequence
  mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios
    op
  mmc: sunxi: Block signal voltage switching (CMD11)
  mmc: sunxi: Support vqmmc regulator
  mmc: sunxi: Support MMC_DDR52 timing modes
  mmc: sunxi: Support 8 bit eMMC DDR transfer modes
  mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support
  ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc
  ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC
  ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins
  ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC
  ARM: dts: sun9i: Use sun9i specific mmc compatible
  ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins
  ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for
    eMMC
  ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for
    eMMC

 arch/arm/boot/dts/sun6i-a31.dtsi               | 10 +++
 arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi |  6 +-
 arch/arm/boot/dts/sun8i-a23-a33.dtsi           |  2 +-
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts |  3 +
 arch/arm/boot/dts/sun9i-a80-cubieboard4.dts    |  6 ++
 arch/arm/boot/dts/sun9i-a80-optimus.dts        |  6 ++
 arch/arm/boot/dts/sun9i-a80.dtsi               | 11 +--
 drivers/mmc/host/sunxi-mmc.c                   | 98 +++++++++++++++++++++++---
 8 files changed, 126 insertions(+), 16 deletions(-)

-- 
2.7.0.rc3

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#1313907 — [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC

mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.

Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 382bd9fc5647..eb2ccd0a3bd5 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -111,9 +111,15 @@
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
+&mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
 &r_ir {
 	status = "okay";
 };
-- 
2.7.0.rc3

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#1315930 — Re: [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC

[Multipart message — attachments visible in raw view] — view raw

On Thu, Jan 21, 2016 at 01:26:42PM +0800, Chen-Yu Tsai wrote:
> mmc2 has a special pin for eMMC hardware reset, which is controllable
> from the controller. Add the "mmc-cap-hw-reset" property to denote that
> this controller supports this function, and the pins are actually used.
> 
> Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
> support.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1313908 — [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
instance can use eMMC hardware reset.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
index ea69fb8ad4d8..4ec0c8679b2e 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
@@ -61,12 +61,14 @@
 };
 
 /* eMMC on core board */
-&mmc2 {
+&mmc3 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
+	pinctrl-0 = <&mmc3_8bit_emmc_pins>;
 	vmmc-supply = <&reg_dcdc1>;
+	vqmmc-supply = <&reg_dcdc1>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
-- 
2.7.0.rc3

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#1314111 — Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

Hi,

On 21-01-16 06:26, Chen-Yu Tsai wrote:
> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
> instance can use eMMC hardware reset.

This is going to need some more explanation, does this mean
that the old dtsi is wrong and the emmc does not work there are all ?

Regards,

Hans


>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>   arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> index ea69fb8ad4d8..4ec0c8679b2e 100644
> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> @@ -61,12 +61,14 @@
>   };
>
>   /* eMMC on core board */
> -&mmc2 {
> +&mmc3 {
>   	pinctrl-names = "default";
> -	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
> +	pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>   	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_dcdc1>;
>   	bus-width = <8>;
>   	non-removable;
> +	cap-mmc-hw-reset;
>   	status = "okay";
>   };
>
>

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#1314151 — Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>
>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>> instance can use eMMC hardware reset.
>
>
> This is going to need some more explanation, does this mean
> that the old dtsi is wrong and the emmc does not work there are all ?

mmc2 works fine for either 4 bit SDR/DDR or 8 bit SDR only. It does
not work for 8 bit DDR. I actually tested all the above combinations.

Also see https://groups.google.com/d/msg/linux-sunxi/pMzwMWwLALw/6WGgCN1eAQAJ

About old DTs not working:

a) The old DT will not work with the mmc patches, as it will try 8 bit DDR
   and fail. Also, the old DT does not use the highest drive strength for
   the mmc pins, meaning it might not work for the other chip families.

b) Old DT + old kernel works fine (8 bit high-speed), just slower.

An alternative would be to drop MMC_CAP_1_8V_DDR from the driver, and
use the "mmc-ddr-1_8v" DT capability flag at the dtsi or board level.
There's no real way to describe "don't use 8 bit with MMC DDR" in the DT.


Regards
ChenYu

>
> Regards,
>
> Hans
>
>
>
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>   arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> @@ -61,12 +61,14 @@
>>   };
>>
>>   /* eMMC on core board */
>> -&mmc2 {
>> +&mmc3 {
>>         pinctrl-names = "default";
>> -       pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>> +       pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>         vmmc-supply = <&reg_dcdc1>;
>> +       vqmmc-supply = <&reg_dcdc1>;
>>         bus-width = <8>;
>>         non-removable;
>> +       cap-mmc-hw-reset;
>>         status = "okay";
>>   };
>>
>>
>

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#1314152 — Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

Hi,

On 21-01-16 13:23, Chen-Yu Tsai wrote:
> On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>>
>>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>>> instance can use eMMC hardware reset.
>>
>>
>> This is going to need some more explanation, does this mean
>> that the old dtsi is wrong and the emmc does not work there are all ?
>
> mmc2 works fine for either 4 bit SDR/DDR or 8 bit SDR only. It does
> not work for 8 bit DDR. I actually tested all the above combinations.
>
> Also see https://groups.google.com/d/msg/linux-sunxi/pMzwMWwLALw/6WGgCN1eAQAJ
>
> About old DTs not working:
>
> a) The old DT will not work with the mmc patches, as it will try 8 bit DDR
>     and fail. Also, the old DT does not use the highest drive strength for
>     the mmc pins, meaning it might not work for the other chip families.
>
> b) Old DT + old kernel works fine (8 bit high-speed), just slower.
>
> An alternative would be to drop MMC_CAP_1_8V_DDR from the driver, and
> use the "mmc-ddr-1_8v" DT capability flag at the dtsi or board level.
> There's no real way to describe "don't use 8 bit with MMC DDR" in the DT.

OK, so what is confusing me, is how can we choose between the emmc being
connected to mmc2 resp mmc3, are there dipswitches on the board? Or can both
mmc controllers be routed to the outside on the same port/pins ?

Regards,

Hans


>
>
> Regards
> ChenYu
>
>>
>> Regards,
>>
>> Hans
>>
>>
>>
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> ---
>>>    arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>>    1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>> b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>> @@ -61,12 +61,14 @@
>>>    };
>>>
>>>    /* eMMC on core board */
>>> -&mmc2 {
>>> +&mmc3 {
>>>          pinctrl-names = "default";
>>> -       pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>>> +       pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>>          vmmc-supply = <&reg_dcdc1>;
>>> +       vqmmc-supply = <&reg_dcdc1>;
>>>          bus-width = <8>;
>>>          non-removable;
>>> +       cap-mmc-hw-reset;
>>>          status = "okay";
>>>    };
>>>
>>>
>>

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#1314157 — Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

On Thu, Jan 21, 2016 at 8:25 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 21-01-16 13:23, Chen-Yu Tsai wrote:
>>
>> On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdegoede@redhat.com>
>> wrote:
>>>
>>> Hi,
>>>
>>> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>>>
>>>>
>>>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>>>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>>>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>>>> instance can use eMMC hardware reset.
>>>
>>>
>>>
>>> This is going to need some more explanation, does this mean
>>> that the old dtsi is wrong and the emmc does not work there are all ?
>>
>>
>> mmc2 works fine for either 4 bit SDR/DDR or 8 bit SDR only. It does
>> not work for 8 bit DDR. I actually tested all the above combinations.
>>
>> Also see
>> https://groups.google.com/d/msg/linux-sunxi/pMzwMWwLALw/6WGgCN1eAQAJ
>>
>> About old DTs not working:
>>
>> a) The old DT will not work with the mmc patches, as it will try 8 bit DDR
>>     and fail. Also, the old DT does not use the highest drive strength for
>>     the mmc pins, meaning it might not work for the other chip families.
>>
>> b) Old DT + old kernel works fine (8 bit high-speed), just slower.
>>
>> An alternative would be to drop MMC_CAP_1_8V_DDR from the driver, and
>> use the "mmc-ddr-1_8v" DT capability flag at the dtsi or board level.
>> There's no real way to describe "don't use 8 bit with MMC DDR" in the DT.
>
>
> OK, so what is confusing me, is how can we choose between the emmc being
> connected to mmc2 resp mmc3, are there dipswitches on the board? Or can both
> mmc controllers be routed to the outside on the same port/pins ?

They are on the same pins, just with a different mux value/function.
I believe the previous patch explains this.

ChenYu

>
> Regards,
>
> Hans
>
>
>
>>
>>
>> Regards
>> ChenYu
>>
>>>
>>> Regards,
>>>
>>> Hans
>>>
>>>
>>>
>>>>
>>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>>> ---
>>>>    arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>>>    1 file changed, 4 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>> b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>>>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>> @@ -61,12 +61,14 @@
>>>>    };
>>>>
>>>>    /* eMMC on core board */
>>>> -&mmc2 {
>>>> +&mmc3 {
>>>>          pinctrl-names = "default";
>>>> -       pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>>>> +       pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>>>          vmmc-supply = <&reg_dcdc1>;
>>>> +       vqmmc-supply = <&reg_dcdc1>;
>>>>          bus-width = <8>;
>>>>          non-removable;
>>>> +       cap-mmc-hw-reset;
>>>>          status = "okay";
>>>>    };
>>>>
>>>>
>>>
>

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#1314162 — Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

Hi,

On 21-01-16 13:28, Chen-Yu Tsai wrote:
> On Thu, Jan 21, 2016 at 8:25 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 21-01-16 13:23, Chen-Yu Tsai wrote:
>>>
>>> On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede <hdegoede@redhat.com>
>>> wrote:
>>>>
>>>> Hi,
>>>>
>>>> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>>>>
>>>>>
>>>>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>>>>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>>>>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>>>>> instance can use eMMC hardware reset.
>>>>
>>>>
>>>>
>>>> This is going to need some more explanation, does this mean
>>>> that the old dtsi is wrong and the emmc does not work there are all ?
>>>
>>>
>>> mmc2 works fine for either 4 bit SDR/DDR or 8 bit SDR only. It does
>>> not work for 8 bit DDR. I actually tested all the above combinations.
>>>
>>> Also see
>>> https://groups.google.com/d/msg/linux-sunxi/pMzwMWwLALw/6WGgCN1eAQAJ
>>>
>>> About old DTs not working:
>>>
>>> a) The old DT will not work with the mmc patches, as it will try 8 bit DDR
>>>      and fail. Also, the old DT does not use the highest drive strength for
>>>      the mmc pins, meaning it might not work for the other chip families.
>>>
>>> b) Old DT + old kernel works fine (8 bit high-speed), just slower.
>>>
>>> An alternative would be to drop MMC_CAP_1_8V_DDR from the driver, and
>>> use the "mmc-ddr-1_8v" DT capability flag at the dtsi or board level.
>>> There's no real way to describe "don't use 8 bit with MMC DDR" in the DT.
>>
>>
>> OK, so what is confusing me, is how can we choose between the emmc being
>> connected to mmc2 resp mmc3, are there dipswitches on the board? Or can both
>> mmc controllers be routed to the outside on the same port/pins ?
>
> They are on the same pins, just with a different mux value/function.
> I believe the previous patch explains this.

Ah yes, I see the remark about them sharing pins in the previous
patch commit msg now, weird.

Regards,

Hans


>
> ChenYu
>
>>
>> Regards,
>>
>> Hans
>>
>>
>>
>>>
>>>
>>> Regards
>>> ChenYu
>>>
>>>>
>>>> Regards,
>>>>
>>>> Hans
>>>>
>>>>
>>>>
>>>>>
>>>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>>>> ---
>>>>>     arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>>>>     1 file changed, 4 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>>> b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>>>>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>>>>> @@ -61,12 +61,14 @@
>>>>>     };
>>>>>
>>>>>     /* eMMC on core board */
>>>>> -&mmc2 {
>>>>> +&mmc3 {
>>>>>           pinctrl-names = "default";
>>>>> -       pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>>>>> +       pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>>>>           vmmc-supply = <&reg_dcdc1>;
>>>>> +       vqmmc-supply = <&reg_dcdc1>;
>>>>>           bus-width = <8>;
>>>>>           non-removable;
>>>>> +       cap-mmc-hw-reset;
>>>>>           status = "okay";
>>>>>     };
>>>>>
>>>>>
>>>>
>>

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#1315261 — Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Multipart message — attachments visible in raw view] — view raw

Hi,

On Thu, Jan 21, 2016 at 01:26:36PM +0800, Chen-Yu Tsai wrote:
> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
> instance can use eMMC hardware reset.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> index ea69fb8ad4d8..4ec0c8679b2e 100644
> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> @@ -61,12 +61,14 @@
>  };
>  
>  /* eMMC on core board */
> -&mmc2 {
> +&mmc3 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&mmc2_8bit_emmc_pins>;
> +	pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>  	vmmc-supply = <&reg_dcdc1>;
> +	vqmmc-supply = <&reg_dcdc1>;

That seems odd. IIRC the VCC was supposed to be fixed and VCCQ could
be either at 1.8 or 3V. Having the same regulator on both would make
VCCQ forced to 3.3V, which seems to go against your commit log.

What's the catch ? :)

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1315515 — Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

On Sat, Jan 23, 2016 at 4:39 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Thu, Jan 21, 2016 at 01:26:36PM +0800, Chen-Yu Tsai wrote:
>> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
>> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
>> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
>> instance can use eMMC hardware reset.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> index ea69fb8ad4d8..4ec0c8679b2e 100644
>> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
>> @@ -61,12 +61,14 @@
>>  };
>>
>>  /* eMMC on core board */
>> -&mmc2 {
>> +&mmc3 {
>>       pinctrl-names = "default";
>> -     pinctrl-0 = <&mmc2_8bit_emmc_pins>;
>> +     pinctrl-0 = <&mmc3_8bit_emmc_pins>;
>>       vmmc-supply = <&reg_dcdc1>;
>> +     vqmmc-supply = <&reg_dcdc1>;
>
> That seems odd. IIRC the VCC was supposed to be fixed and VCCQ could
> be either at 1.8 or 3V. Having the same regulator on both would make
> VCCQ forced to 3.3V, which seems to go against your commit log.
>
> What's the catch ? :)

That is how the board is routed. Which means the only use for
vqmmc-supply is the driver will know that it can only do 3.3V,
i.e. voltage sensing.

It is the reason I requested Olimex to look into this. Allwinner
reference designs all tie vqmmc directly to 3.3V.

Actually with the latest driver patches, this is not even needed. To
make the driver backward compatible, if no vqmmc-supply is given, it
just assumes 3.3V signaling.

Regards
ChenYu

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#1315932 — Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

[Multipart message — attachments visible in raw view] — view raw

Hi,

On Sat, Jan 23, 2016 at 12:21:55PM +0800, Chen-Yu Tsai wrote:
> On Sat, Jan 23, 2016 at 4:39 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi,
> >
> > On Thu, Jan 21, 2016 at 01:26:36PM +0800, Chen-Yu Tsai wrote:
> >> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
> >> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
> >> voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
> >> instance can use eMMC hardware reset.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >>  arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi | 6 ++++--
> >>  1 file changed, 4 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> >> index ea69fb8ad4d8..4ec0c8679b2e 100644
> >> --- a/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> >> +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi
> >> @@ -61,12 +61,14 @@
> >>  };
> >>
> >>  /* eMMC on core board */
> >> -&mmc2 {
> >> +&mmc3 {
> >>       pinctrl-names = "default";
> >> -     pinctrl-0 = <&mmc2_8bit_emmc_pins>;
> >> +     pinctrl-0 = <&mmc3_8bit_emmc_pins>;
> >>       vmmc-supply = <&reg_dcdc1>;
> >> +     vqmmc-supply = <&reg_dcdc1>;
> >
> > That seems odd. IIRC the VCC was supposed to be fixed and VCCQ could
> > be either at 1.8 or 3V. Having the same regulator on both would make
> > VCCQ forced to 3.3V, which seems to go against your commit log.
> >
> > What's the catch ? :)
> 
> That is how the board is routed. Which means the only use for
> vqmmc-supply is the driver will know that it can only do 3.3V,
> i.e. voltage sensing.
> 
> It is the reason I requested Olimex to look into this. Allwinner
> reference designs all tie vqmmc directly to 3.3V.
> 
> Actually with the latest driver patches, this is not even needed. To
> make the driver backward compatible, if no vqmmc-supply is given, it
> just assumes 3.3V signaling.

Ok. I've applied this patch and changed the commit log to remove the
voltage switching mention then, since it won't happen.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1313910 — [PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op

Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a
proper voltage for vmmc.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index cce5ca540857..790f01662b4e 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -711,7 +711,10 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		break;
 
 	case MMC_POWER_UP:
-		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
+		host->ferror = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
+						     ios->vdd);
+		if (host->ferror)
+			return;
 
 		host->ferror = sunxi_mmc_init_host(mmc);
 		if (host->ferror)
-- 
2.7.0.rc3

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#1313911 — [PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes

Allwinner's MMC controller needs to run at double the card clock rate
for 8 bit DDR transfer modes. Interestingly, this is not needed for
4 bit DDR transfers.

Different clock delays are needed for 8 bit eMMC DDR, due to the
increased module clock rate. For the A80 though, the same values for
4 bit and 8 bit are shared. The new values for the other SoCs were from
A83T user manual's "new timing mode" default values, which describes
them in clock phase, rather than delay periods. These values were used
without any modification. They may not be correct, but they work.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 33 ++++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index b403a2433eec..d05928091b34 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -215,6 +215,7 @@
 #define SDXC_CLK_25M		1
 #define SDXC_CLK_50M		2
 #define SDXC_CLK_50M_DDR	3
+#define SDXC_CLK_50M_DDR_8BIT	4
 
 struct sunxi_mmc_clk_delay {
 	u32 output;
@@ -656,11 +657,17 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 				  struct mmc_ios *ios)
 {
 	u32 rate, oclk_dly, rval, sclk_dly;
+	u32 clock = ios->clock;
 	int ret;
 
-	rate = clk_round_rate(host->clk_mmc, ios->clock);
+	/* 8 bit DDR requires a higher module clock */
+	if (ios->timing == MMC_TIMING_MMC_DDR52 &&
+	    ios->bus_width == MMC_BUS_WIDTH_8)
+		clock <<= 1;
+
+	rate = clk_round_rate(host->clk_mmc, clock);
 	dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
-		ios->clock, rate);
+		clock, rate);
 
 	/* setting clock rate */
 	ret = clk_set_rate(host->clk_mmc, rate);
@@ -677,6 +684,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 	/* clear internal divider */
 	rval = mmc_readl(host, REG_CLKCR);
 	rval &= ~0xff;
+	/* set internal divider for 8 bit eMMC DDR, so card clock is right */
+	if (ios->timing == MMC_TIMING_MMC_DDR52 &&
+	    ios->bus_width == MMC_BUS_WIDTH_8) {
+		rval |= 1;
+		rate >>= 1;
+	}
 	mmc_writel(host, REG_CLKCR, rval);
 
 	/* determine delays */
@@ -687,13 +700,16 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 		oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
 		sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
 	} else if (rate <= 50000000) {
-		if (ios->timing == MMC_TIMING_UHS_DDR50 ||
-		    ios->timing == MMC_TIMING_MMC_DDR52) {
-			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
-			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
-		} else {
+		if (ios->timing != MMC_TIMING_UHS_DDR50 &&
+		    ios->timing != MMC_TIMING_MMC_DDR52) {
 			oclk_dly = host->clk_delays[SDXC_CLK_50M].output;
 			sclk_dly = host->clk_delays[SDXC_CLK_50M].sample;
+		} else if (ios->bus_width == MMC_BUS_WIDTH_8) {
+			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].output;
+			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR_8BIT].sample;
+		} else {
+			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
+			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
 		}
 	} else {
 		return -EINVAL;
@@ -965,6 +981,8 @@ static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
 	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },
 	[SDXC_CLK_50M]		= { .output =  90, .sample = 120 },
 	[SDXC_CLK_50M_DDR]	= { .output =  60, .sample = 120 },
+	/* Value from A83T "new timing mode". Works but might not be right. */
+	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  90, .sample = 180 },
 };
 
 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
@@ -972,6 +990,7 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
 	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },
 	[SDXC_CLK_50M]		= { .output = 150, .sample = 120 },
 	[SDXC_CLK_50M_DDR]	= { .output =  90, .sample = 120 },
+	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  90, .sample = 120 },
 };
 
 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
-- 
2.7.0.rc3

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#1313912 — [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible

sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
trigger levels can be increased. Also, the mmc module clock parent
has a higher clock rate, and the sample and output delay phases
are different.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index e838f206f2a0..f4f61b02be1a 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -543,7 +543,7 @@
 		};
 
 		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c0f000 0x1000>;
 			clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
 				 <&mmc0_clk 1>, <&mmc0_clk 2>;
@@ -557,7 +557,7 @@
 		};
 
 		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c10000 0x1000>;
 			clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
 				 <&mmc1_clk 1>, <&mmc1_clk 2>;
@@ -571,7 +571,7 @@
 		};
 
 		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c11000 0x1000>;
 			clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
 				 <&mmc2_clk 1>, <&mmc2_clk 2>;
@@ -585,7 +585,7 @@
 		};
 
 		mmc3: mmc@01c12000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+			compatible = "allwinner,sun9i-a80-mmc";
 			reg = <0x01c12000 0x1000>;
 			clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
 				 <&mmc3_clk 1>, <&mmc3_clk 2>;
-- 
2.7.0.rc3

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#1315264 — Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible

[Multipart message — attachments visible in raw view] — view raw

On Thu, Jan 21, 2016 at 01:26:39PM +0800, Chen-Yu Tsai wrote:
> sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
> trigger levels can be increased. Also, the mmc module clock parent
> has a higher clock rate, and the sample and output delay phases
> are different.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Does that count as a fix, or does the A80 board can safely operate
without it?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1315574 — Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible

On Sat, Jan 23, 2016 at 4:44 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, Jan 21, 2016 at 01:26:39PM +0800, Chen-Yu Tsai wrote:
>> sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
>> trigger levels can be increased. Also, the mmc module clock parent
>> has a higher clock rate, and the sample and output delay phases
>> are different.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> Applied, thanks!
>
> Does that count as a fix, or does the A80 board can safely operate
> without it?

The compatible was added in v4.3, in commit 51424b286067 ("mmc:
sunxi: Fix clk-delay settings").

I've not tested using the old compatibles with 50/52 MHz DDR. They
do work just fine with the transfer modes we already supported.

Either way its been there for a while so i don't see any need to
pick it out as a fix.

ChenYu

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#1313914 — [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC

mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.

Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 13ce68f06dd6..bd2a3beb4629 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -109,10 +109,13 @@
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
 &mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 	/* eMMC is missing pull-ups */
 	allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 };
-- 
2.7.0.rc3

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#1315266 — Re: [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC

[Multipart message — attachments visible in raw view] — view raw

On Thu, Jan 21, 2016 at 01:26:38PM +0800, Chen-Yu Tsai wrote:
> mmc2 has a special pin for eMMC hardware reset, which is controllable
> from the controller. Add the "mmc-cap-hw-reset" property to denote that
> this controller supports this function, and the pins are actually used.
> 
> Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
> support.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1313915 — [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins

mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
The MMC controller also has a reset output that is supported.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 6f88fb0ddbc7..7e05e09e61c7 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -381,7 +381,7 @@
 				allwinner,pins = "PC5", "PC6", "PC8",
 						 "PC9", "PC10", "PC11",
 						 "PC12", "PC13", "PC14",
-						 "PC15";
+						 "PC15", "PC16";
 				allwinner,function = "mmc2";
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-- 
2.7.0.rc3

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