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[PATCH] net: macb: clear interrupts when disabling them

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  [PATCH] net: macb: clear interrupts when disabling them Nathan Sullivan <nathan.sullivan@ni.com> - 2016-01-14 21:50 +0100
    Re: [PATCH] net: macb: clear interrupts when disabling them Nicolas Ferre <nicolas.ferre@atmel.com> - 2016-01-15 09:30 +0100
    Re: [PATCH] net: macb: clear interrupts when disabling them David Miller <davem@davemloft.net> - 2016-01-15 20:50 +0100

#1309646 — [PATCH] net: macb: clear interrupts when disabling them

Disabling interrupts with the IDR register does not stop the macb hardware
from asserting its interrupt line if there are interrupts pending.  Always
clear the interrupts using ISR, and be sure to write it on hardware that
is not read-to-clear, like Zynq.  Not doing so will cause interrupts when
the driver doesn't expect them.

Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
---
 drivers/net/ethernet/cadence/macb.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
index c563475..9d9984a 100644
--- a/drivers/net/ethernet/cadence/macb.c
+++ b/drivers/net/ethernet/cadence/macb.c
@@ -1040,6 +1040,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
 		/* close possible race with dev_close */
 		if (unlikely(!netif_running(dev))) {
 			queue_writel(queue, IDR, -1);
+			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
+				queue_writel(queue, ISR, -1);
 			break;
 		}
 
@@ -1561,6 +1563,8 @@ static void macb_reset_hw(struct macb *bp)
 	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
 		queue_writel(queue, IDR, -1);
 		queue_readl(queue, ISR);
+		if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
+			queue_writel(queue, ISR, -1);
 	}
 }
 
-- 
1.7.10.4

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#1309947

Le 14/01/2016 20:27, Nathan Sullivan a écrit :
> Disabling interrupts with the IDR register does not stop the macb hardware
> from asserting its interrupt line if there are interrupts pending.  Always
> clear the interrupts using ISR, and be sure to write it on hardware that
> is not read-to-clear, like Zynq.  Not doing so will cause interrupts when
> the driver doesn't expect them.
> 
> Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>

It seems okay:
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

> ---
>  drivers/net/ethernet/cadence/macb.c |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c
> index c563475..9d9984a 100644
> --- a/drivers/net/ethernet/cadence/macb.c
> +++ b/drivers/net/ethernet/cadence/macb.c
> @@ -1040,6 +1040,8 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
>  		/* close possible race with dev_close */
>  		if (unlikely(!netif_running(dev))) {
>  			queue_writel(queue, IDR, -1);
> +			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> +				queue_writel(queue, ISR, -1);
>  			break;
>  		}
>  
> @@ -1561,6 +1563,8 @@ static void macb_reset_hw(struct macb *bp)
>  	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
>  		queue_writel(queue, IDR, -1);
>  		queue_readl(queue, ISR);
> +		if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
> +			queue_writel(queue, ISR, -1);
>  	}
>  }
>  
> 


-- 
Nicolas Ferre

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#1310410

From: Nathan Sullivan <nathan.sullivan@ni.com>
Date: Thu, 14 Jan 2016 13:27:27 -0600

> Disabling interrupts with the IDR register does not stop the macb hardware
> from asserting its interrupt line if there are interrupts pending.  Always
> clear the interrupts using ISR, and be sure to write it on hardware that
> is not read-to-clear, like Zynq.  Not doing so will cause interrupts when
> the driver doesn't expect them.
> 
> Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>

Applied, thanks.

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