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| Started by | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| First post | 2016-01-13 18:30 +0100 |
| Last post | 2016-01-13 18:30 +0100 |
| Articles | 1 — 1 participant |
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Re: [PATCH] clk: tegra: Fix clock sources for tegra210 EMC Thierry Reding <thierry.reding@gmail.com> - 2016-01-13 18:30 +0100
| From | Thierry Reding <thierry.reding@gmail.com> |
|---|---|
| Date | 2016-01-13 18:30 +0100 |
| Subject | Re: [PATCH] clk: tegra: Fix clock sources for tegra210 EMC |
| Message-ID | <qQxp9-2W5-19@gated-at.bofh.it> |
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On Fri, Dec 18, 2015 at 01:45:28PM +0000, Jon Hunter wrote: > The EMC clock sources for tegra210 currently incorrectly include pll_c2 > and pll_c3. However, both of these should have been pll_mb as shown in > the TRM. If tegra210 happens to be configured such that the pll_mb is the > default clock for the EMC, as configured by the bootloader, then this will > cause a system hang on boot. This is because the kernel will disable the > pll_mb when disabling unused clock as it appears to be unused when it is > not. > > Also add the additional pll_p clock source for the EMC. > > Signed-off-by: Jon Hunter <jonathanh@nvidia.com> > --- > drivers/clk/tegra/clk-tegra210.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Applied, thanks. Thierry
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