Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1305096 > unrolled thread
| Started by | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| First post | 2016-01-09 01:00 +0100 |
| Last post | 2016-01-09 05:50 +0100 |
| Articles | 2 — 2 participants |
Back to article view | Back to linux.kernel
[PATCH] arm64: dts: Add L2 cache node to msm8916 Stephen Boyd <sboyd@codeaurora.org> - 2016-01-09 01:00 +0100
Re: [PATCH] arm64: dts: Add L2 cache node to msm8916 Andy Gross <andy.gross@linaro.org> - 2016-01-09 05:50 +0100
| From | Stephen Boyd <sboyd@codeaurora.org> |
|---|---|
| Date | 2016-01-09 01:00 +0100 |
| Subject | [PATCH] arm64: dts: Add L2 cache node to msm8916 |
| Message-ID | <qOP6O-5zU-13@gated-at.bofh.it> |
The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
dtsi file so that the cache hierarchy can be probed.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index ba8184d0f948..42573a7d4a94 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -61,24 +61,33 @@
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
+ next-level-cache = <&L2_0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x1>;
+ next-level-cache = <&L2_0>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x2>;
+ next-level-cache = <&L2_0>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
};
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
[toc] | [next] | [standalone]
| From | Andy Gross <andy.gross@linaro.org> |
|---|---|
| Date | 2016-01-09 05:50 +0100 |
| Message-ID | <qOTDs-nH-7@gated-at.bofh.it> |
| In reply to | #1305096 |
On Fri, Jan 08, 2016 at 03:57:09PM -0800, Stephen Boyd wrote: > The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the > dtsi file so that the cache hierarchy can be probed. > > Cc: <devicetree@vger.kernel.org> > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> > --- Reviewed-by: Andy Gross <andy.gross@linaro.org>
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web