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Groups > linux.kernel > #1298396 > unrolled thread
| Started by | Noam Camus <noamc@ezchip.com> |
|---|---|
| First post | 2015-12-27 14:50 +0100 |
| Last post | 2016-01-01 11:40 +0100 |
| Articles | 10 — 2 participants |
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[PATCH v5 00/20] Adding plat-eznps to ARC Noam Camus <noamc@ezchip.com> - 2015-12-27 14:50 +0100
Re: [PATCH v5 09/20] ARC: IRQ: use device tree to get timer device configuration Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-12-28 12:50 +0100
Re: [PATCH v5 05/20] irqchip: add nps Internal and external irqchips Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-12-30 11:10 +0100
Re: [PATCH v5 10/20] ARC: IRQ: do not use hwirq directly at arch_do_IRQ() Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-12-30 11:20 +0100
Re: [PATCH v5 10/20] ARC: IRQ: do not use hwirq directly at arch_do_IRQ() Noam Camus <noamc@ezchip.com> - 2015-12-31 06:30 +0100
Re: [PATCH v5 11/20] ARC: IPI: do not use generic IRQ domain Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-12-30 11:20 +0100
Re: [PATCH v5 11/20] ARC: IPI: do not use generic IRQ domain Noam Camus <noamc@ezchip.com> - 2015-12-31 06:20 +0100
Re: [PATCH v5 05/20] irqchip: add nps Internal and external irqchips Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-12-30 11:50 +0100
Re: [PATCH v5 09/20] ARC: IRQ: use device tree to get timer device configuration Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-12-30 12:30 +0100
Re: [PATCH v5 04/20] clocksource: Add NPS400 timers driver Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2016-01-01 11:40 +0100
| From | Noam Camus <noamc@ezchip.com> |
|---|---|
| Date | 2015-12-27 14:50 +0100 |
| Subject | [PATCH v5 00/20] Adding plat-eznps to ARC |
| Message-ID | <qKjRT-7Gi-1@gated-at.bofh.it> |
From: Noam Camus <noamc@ezchip.com> v5: 1) irqchip -- work with handle_domain_irq(), and remove use of irq_set_default_host() 2) clocksource -- initialize clockevents as well by parsing interrupts node of DT 3) Do not use IPI with irq generic infrastructure v4: 1) irqchip -- use irq_domain_add_linear() 2) clocksource -- use of_clk_get() 3) New header at include/soc use by platform and drivers 4) update DTS file for above fixed drivers v3: 1) irqchip: use MACROS instead of structures to decribe registers. 2) clocksource: use 32bit counter and avoid 2 halfs read of 64bit dance. v2: 1) Remove out of tree platform include path 2) Move atomic/bitop/cmpxchg for platform to end. Remove macro duplication. Fix some bad implementation. 3) define cpu_relax_lowlatency() for platform. 4) rename init_irq_cpu() to init_per_cpu() reorder call to init_per_cpu() for secondary use it instead of init_cpu_smp(). 5) set res_service to call stext 6) fix build failure for CTOP_AUX_BASE at assembly code 7) Use ilog2 for mtm_init_nat() 8) Add CLKSRC_NPS option to Kconfig change nps_clksrc_read() to be more readable. General summay: This set introduce new platform to ARC architecture. Platform name called "eznps" for working with EZchip NPS400 Network Proccessor. NPS400 is targeted to service "fast path" network applications. NPS400 got mesh of 256 extended ARC cores (AKA CTOP), each core got 16 HW threads. This is basically SMT core where at any point of time only one HW thread is active. Each core have HW scheduler that round robin between eligible HW threads. Totaly, kernel sees 4096 CPUs which I belive is a high record. There is no cache coherency between cores so generic user applications and kernel do not use D$. Cores got special memory mappings for huge pages (8MB). Mapping is static and should provide application enough memory without any "TLB miss". This mapping is on top of TLB mapping. This is a basic set that will later be followed with additional set of patches with all advanced features. Many thanks to all people helping to make this happen. Regards, Noam Camus Noam Camus (19): Documentation: Add EZchip vendor to binding list soc: Support for EZchip SoC ARC: [plat-eznps] define IPI_IRQ clocksource: Add NPS400 timers driver irqchip: add nps Internal and external irqchips ARC: Set vmalloc size from configuration ARC: rwlock: disable interrupts in !LLSC variant ARC: Mark secondary cpu online only after all HW setup is done ARC: IRQ: use device tree to get timer device configuration ARC: IRQ: do not use hwirq directly at arch_do_IRQ() ARC: IPI: do not use generic IRQ domain ARC: [plat-eznps] Add eznps board defconfig and dts ARC: [plat-eznps] Add eznps platform ARC: [plat-eznps] Use dedicated user stack top ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg ARC: [plat-eznps] Use dedicated SMP barriers ARC: [plat-eznps] Use dedicated identity auxiliary register. ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE ARC: Add eznps platform to Kconfig and Makefile Tal Zilcer (1): ARC: [plat-eznps] Use dedicated cpu_relax() Documentation/devicetree/bindings/arc/eznps.txt | 7 + .../interrupt-controller/ezchip,nps400-ic.txt | 17 ++ .../bindings/timer/ezchip,nps400-timer.txt | 17 ++ .../devicetree/bindings/vendor-prefixes.txt | 1 + MAINTAINERS | 6 + arch/arc/Kconfig | 10 + arch/arc/Makefile | 5 + arch/arc/boot/dts/eznps.dts | 94 +++++++++ arch/arc/configs/nps_defconfig | 85 +++++++++ arch/arc/include/asm/Kbuild | 1 - arch/arc/include/asm/atomic.h | 79 ++++++++- arch/arc/include/asm/barrier.h | 8 + arch/arc/include/asm/bitops.h | 54 ++++++ arch/arc/include/asm/cmpxchg.h | 87 +++++++-- arch/arc/include/asm/entry-compact.h | 8 + arch/arc/include/asm/hardirq.h | 22 +++ arch/arc/include/asm/irq.h | 9 + arch/arc/include/asm/pgtable.h | 2 +- arch/arc/include/asm/processor.h | 36 +++- arch/arc/include/asm/setup.h | 4 + arch/arc/include/asm/smp.h | 6 + arch/arc/include/asm/spinlock.h | 14 ++ arch/arc/kernel/ctx_sw.c | 13 ++ arch/arc/kernel/irq.c | 25 +++ arch/arc/kernel/setup.c | 1 - arch/arc/kernel/smp.c | 39 ++++- arch/arc/kernel/time.c | 8 + arch/arc/mm/tlb.c | 12 ++ arch/arc/plat-eznps/Kconfig | 34 ++++ arch/arc/plat-eznps/Makefile | 7 + arch/arc/plat-eznps/entry.S | 70 +++++++ arch/arc/plat-eznps/include/plat/ctop.h | 198 +++++++++++++++++++ arch/arc/plat-eznps/include/plat/mtm.h | 60 ++++++ arch/arc/plat-eznps/include/plat/smp.h | 26 +++ arch/arc/plat-eznps/mtm.c | 133 +++++++++++++ arch/arc/plat-eznps/platform.c | 102 ++++++++++ arch/arc/plat-eznps/smp.c | 154 +++++++++++++++ drivers/clocksource/Kconfig | 7 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-nps.c | 199 ++++++++++++++++++++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-eznps.c | 139 ++++++++++++++ include/soc/nps/common.h | 123 ++++++++++++ 43 files changed, 1893 insertions(+), 31 deletions(-) create mode 100644 Documentation/devicetree/bindings/arc/eznps.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt create mode 100644 arch/arc/boot/dts/eznps.dts create mode 100644 arch/arc/configs/nps_defconfig create mode 100644 arch/arc/include/asm/hardirq.h create mode 100644 arch/arc/plat-eznps/Kconfig create mode 100644 arch/arc/plat-eznps/Makefile create mode 100644 arch/arc/plat-eznps/entry.S create mode 100644 arch/arc/plat-eznps/include/plat/ctop.h create mode 100644 arch/arc/plat-eznps/include/plat/mtm.h create mode 100644 arch/arc/plat-eznps/include/plat/smp.h create mode 100644 arch/arc/plat-eznps/mtm.c create mode 100644 arch/arc/plat-eznps/platform.c create mode 100644 arch/arc/plat-eznps/smp.c create mode 100644 drivers/clocksource/timer-nps.c create mode 100644 drivers/irqchip/irq-eznps.c create mode 100644 include/soc/nps/common.h -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Vineet Gupta <Vineet.Gupta1@synopsys.com> |
|---|---|
| Date | 2015-12-28 12:50 +0100 |
| Subject | Re: [PATCH v5 09/20] ARC: IRQ: use device tree to get timer device configuration |
| Message-ID | <qKEtk-1kL-7@gated-at.bofh.it> |
| In reply to | #1298396 |
On Sunday 27 December 2015 06:53 PM, Noam Camus wrote: > From: Noam Camus <noamc@ezchip.com> > > We've designated: > TIMER0 for events (clockevents) > TIMER1 for free running (clocksource) > > Till now timer configuration was done on arch/arc/kernel/time.c > with constant values. > > This commit add device tree support so we can do this work > at dedicated clocksource driver which parse the DT blob. > > Such driver will get clocksource rate as well as interrupt line > from DT and use them for setting clocksourcse and clockevents. > > Note that lately called of_clk_init() is moved before we call > clocksource_probe() since at that time device from DT > need a "provider" (clocks) which will be available only after > we call to of_clk_init(). > > Signed-off-by: Noam Camus <noamc@ezchip.com> > Acked-by: Vineet Gupta <vgupta@synopsys.com> For patches which change semantically, ACK should not be copied over from prev version. I do have some reservation with this patch. I think we should just fix ARC once and for all by removing the legacy registration. This would be a flag day change but I think we should be fine ! No point in keeping 2 implementations ! @Noam let me take a stab at it - OK ! -Vineet -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Vineet Gupta <Vineet.Gupta1@synopsys.com> |
|---|---|
| Date | 2015-12-30 11:10 +0100 |
| Subject | Re: [PATCH v5 05/20] irqchip: add nps Internal and external irqchips |
| Message-ID | <qLlRE-5fz-9@gated-at.bofh.it> |
| In reply to | #1298396 |
On Sunday 27 December 2015 06:53 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
[snip..]
> +
> +static int nps400_irq_map(struct irq_domain *d, unsigned int virq,
> + irq_hw_number_t hw)
> +{
> + switch (hw) {
> + case TIMER0_IRQ:
> + irq_set_percpu_devid(virq);
> + irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu,
> + handle_percpu_devid_irq);
> + break;
> + default:
> + irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi,
> + handle_fasteoi_irq);
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static const struct irq_domain_ops nps400_irq_ops = {
> + .xlate = irq_domain_xlate_onecell,
> + .map = nps400_irq_map,
> +};
> +
> +static struct irq_domain *nps400_root_domain;
> +
> +static void nps400_handle_irq(unsigned int hwirq, struct pt_regs *regs)
> +{
> + handle_domain_irq(nps400_root_domain, hwirq, regs);
> +}
> +
> +static int __init nps400_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + if (parent)
> + panic("DeviceTree incore ic not a root irq controller\n");
> +
> + nps400_root_domain = irq_domain_add_linear(node, NR_CPU_IRQS,
> + &nps400_irq_ops, NULL);
> +
> + if (!nps400_root_domain)
> + panic("nps400 root irq domain not avail\n");
> +
> + set_handle_irq(nps400_handle_irq);
Your series is NOT bisectable - u introduce this call later in series.
But do you need this song and dance anyways. Will handle_domain_irq() NOT work for
ARC in general for the core intc which are instantiated in legacy domain !
I'm ok with extra cost per int handling - given it is the right thing to do which
we've been missing so far !
> +
> + return 0;
> +}
> +IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
>
--
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| From | Vineet Gupta <Vineet.Gupta1@synopsys.com> |
|---|---|
| Date | 2015-12-30 11:20 +0100 |
| Subject | Re: [PATCH v5 10/20] ARC: IRQ: do not use hwirq directly at arch_do_IRQ() |
| Message-ID | <qLm1k-5j3-17@gated-at.bofh.it> |
| In reply to | #1298396 |
On Sunday 27 December 2015 06:53 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> ARC uses hwirq at arch_do_IRQ() to pass into generic_handle_irq().
> This is wrong since we need first to reverse map it into virq.
>
> Happily, if we use handle_domain_irq() we get all we need.
>
> Just like ARM I created a pointer to handler that should be filled
> by an interrupt controller driver from driver/irqchip/
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> ---
> arch/arc/Kconfig | 1 +
> arch/arc/include/asm/irq.h | 5 +++++
> arch/arc/kernel/irq.c | 14 ++++++++++++++
> 3 files changed, 20 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
> index 7be1020..079946e 100644
> --- a/arch/arc/Kconfig
> +++ b/arch/arc/Kconfig
> @@ -32,6 +32,7 @@ config ARC
> select HAVE_OPROFILE
> select HAVE_PERF_EVENTS
> select IRQ_DOMAIN
> + select HANDLE_DOMAIN_IRQ if ARC_PLAT_EZNPS
On same lines as prev comment - just do this unconditionally for ARC port -
assuming this works with legacy domain as well.
> select MODULES_USE_ELF_RELA
> select NO_BOOTMEM
> select OF
> diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
> index c5f8f0f..64226c9 100644
> --- a/arch/arc/include/asm/irq.h
> +++ b/arch/arc/include/asm/irq.h
> @@ -36,4 +36,9 @@ void arc_request_percpu_irq(int irq, int cpu,
> irqreturn_t (*isr)(int irq, void *dev),
> const char *irq_nm, void *percpu_dev);
>
> +#ifdef CONFIG_HANDLE_DOMAIN_IRQ
> +extern void set_handle_irq(void (*handle_irq)(unsigned int hwirq,
> + struct pt_regs *));
> +#endif
Not needed !
> +
> #endif
> diff --git a/arch/arc/kernel/irq.c b/arch/arc/kernel/irq.c
> index ba17f85..7ae5411 100644
> --- a/arch/arc/kernel/irq.c
> +++ b/arch/arc/kernel/irq.c
> @@ -41,6 +41,7 @@ void __init init_IRQ(void)
> * "C" Entry point for any ARC ISR, called from low level vector handler
> * @irq is the vector number read from ICAUSE reg of on-chip intc
> */
> +#ifndef CONFIG_HANDLE_DOMAIN_IRQ
> void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
> {
> struct pt_regs *old_regs = set_irq_regs(regs);
> @@ -50,6 +51,19 @@ void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
> irq_exit();
> set_irq_regs(old_regs);
> }
> +#else
> +void (*handle_arch_irq)(unsigned int hwirq, struct pt_regs *) = NULL;
> +void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
> +{
> + handle_arch_irq(irq, regs);
> +}
> +
> +void __init set_handle_irq(void (*handle_irq)(unsigned int hwirq,
> + struct pt_regs *))
> +{
> + handle_arch_irq = handle_irq;
> +}
> +#endif
>
> /*
> * API called for requesting percpu interrupts - called by each CPU
>
--
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| From | Noam Camus <noamc@ezchip.com> |
|---|---|
| Date | 2015-12-31 06:30 +0100 |
| Subject | Re: [PATCH v5 10/20] ARC: IRQ: do not use hwirq directly at arch_do_IRQ() |
| Message-ID | <qLDYd-g9-1@gated-at.bofh.it> |
| In reply to | #1299296 |
>From: Vineet Gupta <Vineet.Gupta1@synopsys.com> >Sent: Wednesday, December 30, 2015 12:10 PM >> --- a/arch/arc/Kconfig >> +++ b/arch/arc/Kconfig >> @@ -32,6 +32,7 @@ config ARC >> select HAVE_OPROFILE >> select HAVE_PERF_EVENTS >> select IRQ_DOMAIN >> + select HANDLE_DOMAIN_IRQ if ARC_PLAT_EZNPS >On same lines as prev comment - just do this unconditionally for ARC port - assuming this works with legacy domain as well. Yes it should work for legacy domain. On the other hand I can select it at the driver Kconfig itself and remove this line altogether. >> >> +#ifdef CONFIG_HANDLE_DOMAIN_IRQ >> +extern void set_handle_irq(void (*handle_irq)(unsigned int hwirq, >> + struct pt_regs *)); >> +#endif >Not needed ! I need to have it since we do not know at arch/arc/kernel/irq.c what is the domain allocated by the timer driver -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Vineet Gupta <Vineet.Gupta1@synopsys.com> |
|---|---|
| Date | 2015-12-30 11:20 +0100 |
| Subject | Re: [PATCH v5 11/20] ARC: IPI: do not use generic IRQ domain |
| Message-ID | <qLm1k-5j3-23@gated-at.bofh.it> |
| In reply to | #1298396 |
On Sunday 27 December 2015 06:53 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> This behaviour is the desired one as been seen on other arch's.
>
> We do not use generic irq domain and hence hwirq number is used
> directly by our code without any mapping to virq.
> In order to add IPI status to /proc/interrupts we use
> hardirq macros also we define arch_show_interrupts().
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> ---
> arch/arc/include/asm/Kbuild | 1 -
> arch/arc/include/asm/hardirq.h | 22 ++++++++++++++++++++++
> arch/arc/include/asm/smp.h | 6 ++++++
> arch/arc/kernel/irq.c | 13 ++++++++++++-
> arch/arc/kernel/smp.c | 27 +++++++++++++++++++++++++++
> 5 files changed, 67 insertions(+), 2 deletions(-)
> create mode 100644 arch/arc/include/asm/hardirq.h
>
> diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild
> index 0b10ef2..bbc3e4a 100644
> --- a/arch/arc/include/asm/Kbuild
> +++ b/arch/arc/include/asm/Kbuild
> @@ -10,7 +10,6 @@ generic-y += errno.h
> generic-y += fb.h
> generic-y += fcntl.h
> generic-y += ftrace.h
> -generic-y += hardirq.h
So this is going backwards - copy/paste generic code into arch header
I don't understand why you need this !
> generic-y += hw_irq.h
> generic-y += ioctl.h
> generic-y += ioctls.h
> diff --git a/arch/arc/include/asm/hardirq.h b/arch/arc/include/asm/hardirq.h
> new file mode 100644
> index 0000000..e83aa88
> --- /dev/null
> +++ b/arch/arc/include/asm/hardirq.h
> @@ -0,0 +1,22 @@
> +#ifndef __ASM_ARC_HARDIRQ_H
> +#define __ASM_ARC_HARDIRQ_H
> +
> +#include <linux/cache.h>
> +#include <linux/threads.h>
> +
> +typedef struct {
> + unsigned int __softirq_pending;
> +#ifdef CONFIG_SMP
> + unsigned int ipi_irqs;
> +#endif
> +} ____cacheline_aligned irq_cpustat_t;
> +
> +#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
> +#include <linux/irq.h>
> +
> +static inline void ack_bad_irq(unsigned int irq)
> +{
> + printk(KERN_CRIT "unexpected IRQ trap at vector %02x\n", irq);
> +}
> +
> +#endif /* __ASM_ARC_HARDIRQ_H */
> diff --git a/arch/arc/include/asm/smp.h b/arch/arc/include/asm/smp.h
> index 9913804..9e4ec48 100644
> --- a/arch/arc/include/asm/smp.h
> +++ b/arch/arc/include/asm/smp.h
> @@ -14,12 +14,16 @@
> #include <linux/types.h>
> #include <linux/init.h>
> #include <linux/threads.h>
> +#include <asm/ptrace.h>
>
> #define raw_smp_processor_id() (current_thread_info()->cpu)
>
> /* including cpumask.h leads to cyclic deps hence this Forward declaration */
> struct cpumask;
>
> +/* including seq_file.h leads to cyclic deps hence this Forward declaration */
> +struct seq_file;
> +
> /*
> * APIs provided by arch SMP code to generic code
> */
> @@ -32,6 +36,8 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
> extern void __init smp_init_cpus(void);
> extern void first_lines_of_secondary(void);
> extern const char *arc_platform_smp_cpuinfo(void);
> +extern void arch_do_IPI(unsigned int irq, struct pt_regs *regs);
> +extern void show_ipi_list(struct seq_file *, int);
>
> /*
> * API expected BY platform smp code (FROM arch smp code)
> diff --git a/arch/arc/kernel/irq.c b/arch/arc/kernel/irq.c
> index 7ae5411..c8d3c3d 100644
> --- a/arch/arc/kernel/irq.c
> +++ b/arch/arc/kernel/irq.c
> @@ -55,7 +55,10 @@ void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
> void (*handle_arch_irq)(unsigned int hwirq, struct pt_regs *) = NULL;
> void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
> {
> - handle_arch_irq(irq, regs);
> + if (irq == IPI_IRQ)
> + arch_do_IPI(irq, regs);
> + else
> + handle_arch_irq(irq, regs);
> }
>
> void __init set_handle_irq(void (*handle_irq)(unsigned int hwirq,
> @@ -65,6 +68,14 @@ void __init set_handle_irq(void (*handle_irq)(unsigned int hwirq,
> }
> #endif
>
> +int arch_show_interrupts(struct seq_file *p, int prec)
> +{
> +#ifdef CONFIG_SMP
> + show_ipi_list(p, prec);
> +#endif
> + return 0;
> +}
> +
> /*
> * API called for requesting percpu interrupts - called by each CPU
> * - For boot CPU, actually request the IRQ with genirq core + enables
> diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
> index ec6a5c1..8d37906 100644
> --- a/arch/arc/kernel/smp.c
> +++ b/arch/arc/kernel/smp.c
> @@ -22,6 +22,7 @@
> #include <linux/atomic.h>
> #include <linux/cpumask.h>
> #include <linux/reboot.h>
> +#include <linux/seq_file.h>
> #include <asm/processor.h>
> #include <asm/setup.h>
> #include <asm/mach_desc.h>
> @@ -349,6 +350,32 @@ irqreturn_t do_IPI(int irq, void *dev_id)
> return IRQ_HANDLED;
> }
>
> +void arch_do_IPI(unsigned int irq, struct pt_regs *regs)
> +{
> + struct pt_regs *old_regs = set_irq_regs(regs);
> + unsigned int cpu = smp_processor_id();
> +
> + __IRQ_STAT(cpu, ipi_irqs)++;
> +
> + irq_enter();
> + do_IPI(irq, NULL);
> + irq_exit();
> +
> + set_irq_regs(old_regs);
> +}
WHY ?
> +
> +void show_ipi_list(struct seq_file *p, int prec)
> +{
> + unsigned int cpu;
> +
> + seq_printf(p, "%*s: ", prec - 1, "IPI");
> +
> + for_each_online_cpu(cpu)
> + seq_printf(p, "%10u ", __IRQ_STAT(cpu, ipi_irqs));
> +
> + seq_printf(p, " %s\n", "IPI");
> +}
> +
> /*
> * API called by platform code to hookup arch-common ISR to their IPI IRQ
> */
>
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| From | Noam Camus <noamc@ezchip.com> |
|---|---|
| Date | 2015-12-31 06:20 +0100 |
| Subject | Re: [PATCH v5 11/20] ARC: IPI: do not use generic IRQ domain |
| Message-ID | <qLDOy-9q-5@gated-at.bofh.it> |
| In reply to | #1299297 |
>From: Vineet Gupta <Vineet.Gupta1@synopsys.com>
>Sent: Wednesday, December 30, 2015 12:13 PM
>> generic-y += fb.h
>> generic-y += fcntl.h
>> generic-y += ftrace.h
>> -generic-y += hardirq.h
>So this is going backwards - copy/paste generic code into arch header
I don't understand why you need this !
I need an extra field (ipi_irqs) at struct irq_cpustat_t and I cannot do this at asm-generic.
See below that how I use it to save and show status for each cpu
>> +void arch_do_IPI(unsigned int irq, struct pt_regs *regs)
>> +{
>> + struct pt_regs *old_regs = set_irq_regs(regs);
>> + unsigned int cpu = smp_processor_id();
>> +
>> + __IRQ_STAT(cpu, ipi_irqs)++;
>> +
>> + irq_enter();
>> + do_IPI(irq, NULL);
>> + irq_exit();
>> +
>> + set_irq_regs(old_regs);
>> +}
>WHY ?
Please explain
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| From | Vineet Gupta <Vineet.Gupta1@synopsys.com> |
|---|---|
| Date | 2015-12-30 11:50 +0100 |
| Subject | Re: [PATCH v5 05/20] irqchip: add nps Internal and external irqchips |
| Message-ID | <qLmul-5sY-3@gated-at.bofh.it> |
| In reply to | #1298396 |
On Sunday 27 December 2015 06:53 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
...
> +static struct irq_domain *nps400_root_domain;
This can simply be a local var now !
> +static void nps400_handle_irq(unsigned int hwirq, struct pt_regs *regs)
> +{
> + handle_domain_irq(nps400_root_domain, hwirq, regs);
> +}
> +
> +static int __init nps400_of_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + if (parent)
> + panic("DeviceTree incore ic not a root irq controller\n");
> +
> + nps400_root_domain = irq_domain_add_linear(node, NR_CPU_IRQS,
> + &nps400_irq_ops, NULL);
> +
> + if (!nps400_root_domain)
> + panic("nps400 root irq domain not avail\n");
> +
> + set_handle_irq(nps400_handle_irq);
> +
> + return 0;
> +}
> +IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", nps400_of_init);
>
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| From | Vineet Gupta <Vineet.Gupta1@synopsys.com> |
|---|---|
| Date | 2015-12-30 12:30 +0100 |
| Subject | Re: [PATCH v5 09/20] ARC: IRQ: use device tree to get timer device configuration |
| Message-ID | <qLn74-5Wu-19@gated-at.bofh.it> |
| In reply to | #1298396 |
On Sunday 27 December 2015 06:53 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> We've designated:
> TIMER0 for events (clockevents)
> TIMER1 for free running (clocksource)
>
> Till now timer configuration was done on arch/arc/kernel/time.c
> with constant values.
>
> This commit add device tree support so we can do this work
> at dedicated clocksource driver which parse the DT blob.
>
> Such driver will get clocksource rate as well as interrupt line
> from DT and use them for setting clocksourcse and clockevents.
Rephrase above part please...
Enable DT based clocksources/clockevents to be probed on ARC. Both clk and IRQ are
furnished by DT.
>
> Note that lately called of_clk_init() is moved before we call
> clocksource_probe() since at that time device from DT
> need a "provider" (clocks) which will be available only after
> we call to of_clk_init().
Rephrase...
Also move of_clk_init() from a late'ish arch_initcall into time_init() to ensure
clocksource_probe() gets the "provide" clocks.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Acked-by: Vineet Gupta <vgupta@synopsys.com>
> ---
> arch/arc/kernel/setup.c | 1 -
> arch/arc/kernel/smp.c | 2 ++
> arch/arc/kernel/time.c | 8 ++++++++
> 3 files changed, 10 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
> index e1b8744..4681e9c 100644
> --- a/arch/arc/kernel/setup.c
> +++ b/arch/arc/kernel/setup.c
> @@ -433,7 +433,6 @@ void __init setup_arch(char **cmdline_p)
>
> static int __init customize_machine(void)
> {
> - of_clk_init(NULL);
> /*
> * Traverses flattened DeviceTree - registering platform devices
> * (if any) complete with their resources
> diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
> index 2cfe135..ec6a5c1 100644
> --- a/arch/arc/kernel/smp.c
> +++ b/arch/arc/kernel/smp.c
> @@ -138,7 +138,9 @@ void start_kernel_secondary(void)
>
> pr_info("## CPU%u LIVE ##: Executing Code...\n", cpu);
>
> +#ifndef CONFIG_CLKSRC_OF
> arc_local_timer_setup();
> +#endif
>
> local_irq_enable();
> preempt_disable();
> diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
> index dfad287..be6dd9e 100644
> --- a/arch/arc/kernel/time.c
> +++ b/arch/arc/kernel/time.c
> @@ -38,6 +38,7 @@
> #include <linux/init.h>
> #include <linux/timex.h>
> #include <linux/profile.h>
> +#include <linux/clk-provider.h>
> #include <linux/clocksource.h>
> #include <linux/clockchips.h>
> #include <asm/irq.h>
> @@ -283,6 +284,13 @@ void __init time_init(void)
> */
> clocksource_register_hz(&arc_counter, arc_get_core_freq());
>
> +#ifdef CONFIG_COMMON_CLK
> + of_clk_init(NULL);
> +#endif
> +#ifdef CONFIG_CLKSRC_OF
> + clocksource_probe();
> +#else
You don't need the #ifdef for both as stub versions already exist.
> /* sets up the periodic event timer */
> arc_local_timer_setup();
simply do #ifndef CONFIG_CLKSRC_OF just as you do above.
I wanted to remove arc_local_timer_setup from ARC altogether and just switch over
to DT, but it seems I first need to figure out how the timer clk will work with
existing *hack* in plat-axs where we change the clk value for SMP / QUAD configs.
Perhaps needs a clk driver !
> +#endif
> }
>
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| From | Vineet Gupta <Vineet.Gupta1@synopsys.com> |
|---|---|
| Date | 2016-01-01 11:40 +0100 |
| Subject | Re: [PATCH v5 04/20] clocksource: Add NPS400 timers driver |
| Message-ID | <qM5hM-1eu-13@gated-at.bofh.it> |
| In reply to | #1298396 |
On Sunday 27 December 2015 06:53 PM, Noam Camus wrote:
> From: Noam Camus <noamc@ezchip.com>
>
> Add internal tick generator which is shared by all cores.
> Each cluster of cores view it through dedicated address.
> This is used for SMP system where all CPUs synced by same
> clock source.
>
> Signed-off-by: Noam Camus <noamc@ezchip.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: John Stultz <john.stultz@linaro.org>
> Acked-by: Vineet Gupta <vgupta@synopsys.com>
Not quite.
Also it would help if your individual patches record which changed vs. prev
version (vs. doing that just in cover letter).
So this patch is no longer clocksource as you introduce clockevent as well.
And that is a verbose copy/paste of clockevent in arch/arc/kerne/time.c
I do understand why you did this - since ARC timers have not been DT enabled so
far. But the copy/paste is simply *wrong*.
I'm doing a mini-series which fixes the issue at heart.
It will be a series with incremental changes so we clearly see what is being done.
> ---
> .../bindings/timer/ezchip,nps400-timer.txt | 17 ++
> drivers/clocksource/Kconfig | 7 +
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/timer-nps.c | 199 ++++++++++++++++++++
> 4 files changed, 224 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
> create mode 100644 drivers/clocksource/timer-nps.c
>
> diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
> new file mode 100644
> index 0000000..eeb26d7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
> @@ -0,0 +1,17 @@
> +NPS Network Processor
> +
> +Required properties:
> +
> +- compatible : should be "ezchip,nps400-timer"
> +
> +Clocks required for compatible = "ezchip,nps400-timer":
> +- clocks : Must contain a single entry describing the clock input
> +- interrupts : The interrupt of the first timer
> +
> +Example:
> +
> +timer {
> + compatible = "ezchip,nps400-timer";
> + clocks = <&sysclk>;
> + interrupts = <3>;
> +};
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 2eb5f0e..859e83d 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -132,6 +132,13 @@ config CLKSRC_TI_32K
> This option enables support for Texas Instruments 32.768 Hz clocksource
> available on many OMAP-like platforms.
>
> +config CLKSRC_NPS
> + bool "NPS400 clocksource driver" if COMPILE_TEST
> + select CLKSRC_OF if OF
> + help
> + NPS400 clocksource support.
> + Got 64 bit counter with update rate up to 1000MHz.
> +
> config CLKSRC_STM32
> bool "Clocksource for STM32 SoCs" if !ARCH_STM32
> depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 56bd16e..056cffd 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
> obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
> obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
> obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
> +obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o
>
> obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
> obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
> diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
> new file mode 100644
> index 0000000..b3fc9ba
> --- /dev/null
> +++ b/drivers/clocksource/timer-nps.c
> @@ -0,0 +1,199 @@
> +/*
> + * Copyright(c) 2015 EZchip Technologies.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * The full GNU General Public License is included in this distribution in
> + * the file called "COPYING".
> + */
> +
> +#include <linux/clocksource.h>
> +#include <linux/clockchips.h>
> +#include <linux/clk.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/cpu.h>
> +#include <soc/nps/common.h>
> +
> +#define NPS_MSU_TICK_LOW 0xC8
> +#define NPS_CLUSTER_OFFSET 8
> +#define NPS_CLUSTER_NUM 16
> +
> +/* Timer related Aux registers */
> +#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
> +#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
> +#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
> +
> +#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
> +#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
> +
> +/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
> +static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
> +
> +static unsigned long nps_timer_rate;
> +static int nps_timer_irq;
> +
> +static cycle_t nps_clksrc_read(struct clocksource *clksrc)
> +{
> + int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
> +
> + return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
> +}
> +
> +static struct clocksource nps_counter = {
> + .name = "EZnps-tick",
> + .rating = 301,
> + .read = nps_clksrc_read,
> + .mask = CLOCKSOURCE_MASK(32),
> + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> +};
> +
> +static void nps_timer_event_setup(unsigned int cycles)
> +{
> + write_aux_reg(ARC_REG_TIMER0_LIMIT, cycles);
> + write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
> +
> + write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
> +}
> +
> +static int nps_clkevent_set_next_event(unsigned long delta,
> + struct clock_event_device *dev)
> +{
> + nps_timer_event_setup(delta);
> + return 0;
> +}
> +
> +static int nps_clkevent_set_periodic(struct clock_event_device *dev)
> +{
> + /*
> + * At X Hz, 1 sec = 1000ms -> X cycles;
> + * 10ms -> X / 100 cycles
> + */
> + nps_timer_event_setup(nps_timer_rate / HZ);
> + return 0;
> +}
> +
> +static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
> + .name = "nps_sys_timer",
> + .features = CLOCK_EVT_FEAT_ONESHOT |
> + CLOCK_EVT_FEAT_PERIODIC,
> + .rating = 300,
> + .set_next_event = nps_clkevent_set_next_event,
> + .set_state_periodic = nps_clkevent_set_periodic,
> +};
> +
> +static int nps_timer_cpu_notify(struct notifier_block *self,
> + unsigned long action, void *hcpu)
> +{
> + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
> +
> + evt->irq = nps_timer_irq;
> + evt->cpumask = cpumask_of(smp_processor_id());
> +
> + /*
> + * Grab cpu pointer in each case to avoid spurious
> + * preemptible warnings
> + */
> + switch (action & ~CPU_TASKS_FROZEN) {
> + case CPU_STARTING:
> + enable_percpu_irq(nps_timer_irq, 0);
> + clockevents_config_and_register(evt, nps_timer_rate,
> + 0, ULONG_MAX);
> + break;
> + case CPU_DYING:
> + disable_percpu_irq(nps_timer_irq);
> + break;
> + }
> +
> + return NOTIFY_OK;
> +}
> +
> +static struct notifier_block nps_timer_cpu_nb = {
> + .notifier_call = nps_timer_cpu_notify,
> +};
> +
> +static irqreturn_t nps_timer_irq_handler(int irq, void *dev_id)
> +{
> + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
> + int irq_reenable = clockevent_state_periodic(evt);
> +
> + /*
> + * Any write to CTRL reg ACks the interrupt, we rewrite the
> + * Count when [N]ot [H]alted bit.
> + * And re-arm it if perioid by [I]nterrupt [E]nable bit
> + */
> + write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
> +
> + evt->event_handler(evt);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void __init nps_setup_clocksource(struct device_node *node,
> + struct clk *clk, int irq)
> +{
> + struct clocksource *clksrc = &nps_counter;
> + int ret, cluster;
> +
> + for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
> + nps_msu_reg_low_addr[cluster] =
> + nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
> + NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
> +
> + ret = clk_prepare_enable(clk);
> + if (ret)
> + pr_err("Couldn't enable parent clock\n");
> +
> + nps_timer_rate = clk_get_rate(clk);
> +
> + ret = clocksource_register_hz(clksrc, nps_timer_rate);
> + if (ret)
> + pr_err("Couldn't register clock source.\n");
> +}
> +
> +static void __init nps_setup_clockevents(struct device_node *node,
> + struct clk *clk, int irq)
> +{
> + struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
> + int ret;
> +
> + register_cpu_notifier(&nps_timer_cpu_nb);
> +
> + evt->irq = irq;
> + evt->cpumask = cpumask_of(smp_processor_id());
> +
> + clockevents_config_and_register(evt, nps_timer_rate, 0, ULONG_MAX);
> +
> + enable_percpu_irq(irq, 0);
> +
> + ret = request_percpu_irq(irq, nps_timer_irq_handler,
> + "timer", evt);
> + if (ret)
> + pr_err("Unable to register interrupt\n");
> +}
> +
> +static void __init nps_timer_init(struct device_node *node)
> +{
> + struct clk *clk;
> +
> + nps_timer_irq = irq_of_parse_and_map(node, 0);
> + if (nps_timer_irq <= 0)
> + panic("Can't parse IRQ");
> +
> + clk = of_clk_get(node, 0);
> + if (IS_ERR(clk))
> + panic("Can't get timer clock");
> +
> + nps_setup_clocksource(node, clk, nps_timer_irq);
> + nps_setup_clockevents(node, clk, nps_timer_irq);
> +}
> +
> +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
> + nps_timer_init);
>
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