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[PATCH V16 00/11] x86: Intel Cache Allocation Technology Support

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  [PATCH V16 00/11] x86: Intel Cache Allocation Technology Support "Fenghua Yu" <fenghua.yu@intel.com> - 2015-12-17 21:10 +0100
    [PATCH V16 01/11] x86/intel_cqm: Modify hot cpu notification handling "Fenghua Yu" <fenghua.yu@intel.com> - 2015-12-17 21:10 +0100
      [tip:x86/cache] x86/intel_cqm:   Modify hot cpu notification handling tip-bot for Fenghua Yu <tipbot@zytor.com> - 2015-12-18 22:40 +0100
    [PATCH V16 03/11] x86/intel_rdt: Cache Allocation documentation "Fenghua Yu" <fenghua.yu@intel.com> - 2015-12-17 21:10 +0100
      [tip:x86/cache] x86/intel_rdt: Cache Allocation documentation tip-bot for Fenghua Yu <tipbot@zytor.com> - 2015-12-18 22:40 +0100
    [PATCH V16 07/11] x86/intel_rdt: Implement scheduling support for Intel RDT "Fenghua Yu" <fenghua.yu@intel.com> - 2015-12-17 21:10 +0100
      [tip:x86/cache] x86/intel_rdt:   Implement scheduling support for Intel RDT tip-bot for Fenghua Yu <tipbot@zytor.com> - 2015-12-18 22:40 +0100
    [PATCH V16 04/11] x86/intel_rdt: Add support for Cache Allocation detection "Fenghua Yu" <fenghua.yu@intel.com> - 2015-12-17 21:10 +0100
      [tip:x86/cache] x86/intel_rdt:   Add support for Cache Allocation detection tip-bot for Fenghua Yu <tipbot@zytor.com> - 2015-12-18 22:40 +0100
    [PATCH V16 09/11] x86/intel_rdt: Intel haswell Cache Allocation enumeration "Fenghua Yu" <fenghua.yu@intel.com> - 2015-12-17 21:10 +0100
      [tip:x86/cache] x86/intel_rdt:   Intel haswell Cache Allocation enumeration tip-bot for Fenghua Yu <tipbot@zytor.com> - 2015-12-18 22:40 +0100
    [PATCH V16 08/11] x86/intel_rdt: Hot cpu support for Cache Allocation "Fenghua Yu" <fenghua.yu@intel.com> - 2015-12-17 21:10 +0100
      [tip:x86/cache] x86/intel_rdt:   Hot cpu support for Cache Allocation tip-bot for Fenghua Yu <tipbot@zytor.com> - 2015-12-18 22:40 +0100
    [PATCH V16 06/11] x86/intel_rdt: Add L3 cache capacity bitmask management "Fenghua Yu" <fenghua.yu@intel.com> - 2015-12-17 21:10 +0100
      [tip:x86/cache] x86/intel_rdt:   Add L3 cache capacity bitmask management tip-bot for Fenghua Yu <tipbot@zytor.com> - 2015-12-18 22:40 +0100
    [PATCH V16 11/11] x86,cgroup/intel_rdt : Add a cgroup interface to manage Intel cache allocation "Fenghua Yu" <fenghua.yu@intel.com> - 2015-12-17 21:10 +0100
      [tip:x86/cache] x86,cgroup/intel_rdt :   Add a cgroup interface to manage Intel cache allocation tip-bot for Fenghua Yu <tipbot@zytor.com> - 2015-12-18 22:40 +0100
      Re: [PATCH V16 11/11] x86,cgroup/intel_rdt : Add a cgroup interface  to manage Intel cache allocation Thomas Gleixner <tglx@linutronix.de> - 2015-12-19 11:50 +0100
        Re: [PATCH V16 11/11] x86,cgroup/intel_rdt : Add a cgroup interface  to manage Intel cache allocation Marcelo Tosatti <mtosatti@redhat.com> - 2015-12-21 13:00 +0100
          Re: [PATCH V16 11/11] x86,cgroup/intel_rdt : Add a cgroup interface  to manage Intel cache allocation Thomas Gleixner <tglx@linutronix.de> - 2015-12-21 14:50 +0100
          Re: [PATCH V16 11/11] x86,cgroup/intel_rdt : Add a cgroup interface  to manage Intel cache allocation Luiz Capitulino <lcapitulino@redhat.com> - 2015-12-21 16:50 +0100
            Re: [PATCH V16 11/11] x86,cgroup/intel_rdt : Add a cgroup interface  to manage Intel cache allocation Marcelo Tosatti <mtosatti@redhat.com> - 2015-12-22 00:10 +0100
    Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology  Support Christoph Lameter <cl@linux.com> - 2015-12-18 18:50 +0100
      Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology Support Marcelo Tosatti <mtosatti@redhat.com> - 2015-12-21 13:00 +0100
        Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology  Support Christoph Lameter <cl@linux.com> - 2015-12-21 14:00 +0100
    Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology  Support Luiz Capitulino <lcapitulino@redhat.com> - 2015-12-21 17:00 +0100
    Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology Support Tejun Heo <tj@kernel.org> - 2015-12-23 17:00 +0100

Page 2 of 2 — ← Prev page 1 [2]

#1296040 — Re: [PATCH V16 11/11] x86,cgroup/intel_rdt : Add a cgroup interface to manage Intel cache allocation

On Sat, 19 Dec 2015 22:57:30 -0200
Marcelo Tosatti <mtosatti@redhat.com> wrote:

> On Sat, Dec 19, 2015 at 11:42:57AM +0100, Thomas Gleixner wrote:
> > On Thu, 17 Dec 2015, Fenghua Yu wrote:
> > 
> > > From: Fenghua Yu <fenghua.yu@intel.com>
> > > 
> > > From: Vikas Shivappa <vikas.shivappa@linux.intel.com>
> > > 
> > > Add a new cgroup 'intel_rdt' to manage cache allocation. Each cgroup
> > > directory is associated with a class of service id(closid). To map a
> > > task with closid during scheduling, this patch removes the closid field
> > > from task_struct and uses the already existing 'cgroups' field in
> > > task_struct.
> > > 
> > > The cgroup has a file 'l3_cbm' which represents the L3 cache capacity
> > > bitmask(CBM). The CBM is global for the whole system currently. The
> > > capacity bitmask needs to have only contiguous bits set and number of
> > > bits that can be set is less than the max bits that can be set. The
> > > tasks belonging to a cgroup get to fill in the L3 cache represented by
> > > the capacity bitmask of the cgroup. For ex: if the max bits in the CBM
> > > is 10 and the cache size is 10MB, each bit represents 1MB of cache
> > > capacity.
> > > 
> > > Root cgroup always has all the bits set in the l3_cbm. User can create
> > > more cgroups with mkdir syscall. By default the child cgroups inherit
> > > the capacity bitmask(CBM) from parent. User can change the CBM specified
> > > in hex for each cgroup. Each unique bitmask is associated with a class
> > > of service ID and an -ENOSPC is returned once we run out of
> > > closids.
> > 
> > This is still the original crap. No, we are not introducing this
> > interface now just because we can. I explained in great length why
> > this is completely useless and what we really need.
> > 
> > Thanks,
> > 
> > 	tglx
> 
> Can you make a summary of the points, and enumerate them, please.
> (what are the problems of the current interface, and why such problems
> are fixed in the new interface?).

Marcelo, you participated on the discussions. We discussed why this
is a bad interface a *lot* in the v15 posting. There are two writeups
that summarize all the problems:

 - https://lkml.org/lkml/2015/11/18/637

 - http://lkml.iu.edu/hypermail/linux/kernel/1511.0/02375.html
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#1296279 — Re: [PATCH V16 11/11] x86,cgroup/intel_rdt : Add a cgroup interface to manage Intel cache allocation

On Mon, Dec 21, 2015 at 10:48:22AM -0500, Luiz Capitulino wrote:
> On Sat, 19 Dec 2015 22:57:30 -0200
> Marcelo Tosatti <mtosatti@redhat.com> wrote:
> 
> > On Sat, Dec 19, 2015 at 11:42:57AM +0100, Thomas Gleixner wrote:
> > > On Thu, 17 Dec 2015, Fenghua Yu wrote:
> > > 
> > > > From: Fenghua Yu <fenghua.yu@intel.com>
> > > > 
> > > > From: Vikas Shivappa <vikas.shivappa@linux.intel.com>
> > > > 
> > > > Add a new cgroup 'intel_rdt' to manage cache allocation. Each cgroup
> > > > directory is associated with a class of service id(closid). To map a
> > > > task with closid during scheduling, this patch removes the closid field
> > > > from task_struct and uses the already existing 'cgroups' field in
> > > > task_struct.
> > > > 
> > > > The cgroup has a file 'l3_cbm' which represents the L3 cache capacity
> > > > bitmask(CBM). The CBM is global for the whole system currently. The
> > > > capacity bitmask needs to have only contiguous bits set and number of
> > > > bits that can be set is less than the max bits that can be set. The
> > > > tasks belonging to a cgroup get to fill in the L3 cache represented by
> > > > the capacity bitmask of the cgroup. For ex: if the max bits in the CBM
> > > > is 10 and the cache size is 10MB, each bit represents 1MB of cache
> > > > capacity.
> > > > 
> > > > Root cgroup always has all the bits set in the l3_cbm. User can create
> > > > more cgroups with mkdir syscall. By default the child cgroups inherit
> > > > the capacity bitmask(CBM) from parent. User can change the CBM specified
> > > > in hex for each cgroup. Each unique bitmask is associated with a class
> > > > of service ID and an -ENOSPC is returned once we run out of
> > > > closids.
> > > 
> > > This is still the original crap. No, we are not introducing this
> > > interface now just because we can. I explained in great length why
> > > this is completely useless and what we really need.
> > > 
> > > Thanks,
> > > 
> > > 	tglx
> > 
> > Can you make a summary of the points, and enumerate them, please.
> > (what are the problems of the current interface, and why such problems
> > are fixed in the new interface?).
> 
> Marcelo, you participated on the discussions. We discussed why this
> is a bad interface a *lot* in the v15 posting. There are two writeups
> that summarize all the problems:
> 
>  - https://lkml.org/lkml/2015/11/18/637

OK cool hopefully that makes it clear to Fenghua Yu what must
be changed in the patchset.

>  - http://lkml.iu.edu/hypermail/linux/kernel/1511.0/02375.html

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#1295073 — Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology Support

On Thu, 17 Dec 2015, Fenghua Yu wrote:

> 	Intel Cache allocation support:
>
> 	Cache allocation patches adds a cgroup subsystem to support the new
> Cache Allocation feature found in future Intel Xeon Intel processors.
> Cache Allocation is a sub-feature with in Resource Director
> Technology(RDT) feature. Current patches support only L3 cache
> allocation.
>
> Cache Allocation provides a way for the Software (OS/VMM) to restrict
> cache allocation to a defined 'subset' of cache which may be overlapping
> with other 'subsets'.  This feature is used when a thread is allocating
> a cache line ie when pulling new data into the cache.
>
> Threads are associated with a CLOS(Class of service). OS specifies the
> CLOS of a thread by writing the IA32_PQR_ASSOC MSR during context
> switch. The cache capacity associated with CLOS 'n' is specified by
> writing to the IA32_L3_MASK_n MSR.

Could you also support another low level interface where a task (or
process) can set the CLOS id itself if it has CAP_SYS_NICE. Plus some way
for the supervisor to directly control the IA32_L3_MASK_n MSR?

Is there a way to see these values for debugging purposes?

We tightly control processes and bind them to processors. cpusets are
often a too high level instrument at that level.

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#1295936

On Fri, Dec 18, 2015 at 11:45:29AM -0600, Christoph Lameter wrote:
> On Thu, 17 Dec 2015, Fenghua Yu wrote:
> 
> > 	Intel Cache allocation support:
> >
> > 	Cache allocation patches adds a cgroup subsystem to support the new
> > Cache Allocation feature found in future Intel Xeon Intel processors.
> > Cache Allocation is a sub-feature with in Resource Director
> > Technology(RDT) feature. Current patches support only L3 cache
> > allocation.
> >
> > Cache Allocation provides a way for the Software (OS/VMM) to restrict
> > cache allocation to a defined 'subset' of cache which may be overlapping
> > with other 'subsets'.  This feature is used when a thread is allocating
> > a cache line ie when pulling new data into the cache.
> >
> > Threads are associated with a CLOS(Class of service). OS specifies the
> > CLOS of a thread by writing the IA32_PQR_ASSOC MSR during context
> > switch. The cache capacity associated with CLOS 'n' is specified by
> > writing to the IA32_L3_MASK_n MSR.
> 
> Could you also support another low level interface where a task (or
> process) can set the CLOS id itself if it has CAP_SYS_NICE.

Hi Christoph,

Do you have a proposal for an interface?

>  Plus some way
> for the supervisor to directly control the IA32_L3_MASK_n MSR?

What you mean supervisor? Hypervisor or root user?

> Is there a way to see these values for debugging purposes?

Yes, from userspace, wrmsr and rdmsr.

> We tightly control processes and bind them to processors. cpusets are
> often a too high level instrument at that level.


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#1295964 — Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology Support

On Fri, 18 Dec 2015, Marcelo Tosatti wrote:

> > Could you also support another low level interface where a task (or
> > process) can set the CLOS id itself if it has CAP_SYS_NICE.
>
> Hi Christoph,
>
> Do you have a proposal for an interface?

Syscall set_closid(int closid) for an app. The CLOS id should be
listed in /proc/<pid>/status

And then /proc/clos listing the possible configs with their current
setups.

Or /proc/clos/<closid>/<value>. Then have the ability to modify
those for the root user.

> >  Plus some way
> > for the supervisor to directly control the IA32_L3_MASK_n MSR?
>
> What you mean supervisor? Hypervisor or root user?

Root user.
>
> > Is there a way to see these values for debugging purposes?
>
> Yes, from userspace, wrmsr and rdmsr.

Maybe have a nicer way to interact with these configurations via /proc?
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#1296050 — Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology Support

On Thu, 17 Dec 2015 14:46:05 -0800
"Fenghua Yu" <fenghua.yu@intel.com> wrote:

> Changes in V16:
>  - Port to latest upstream kernel
>  - Add a spin lock to handle contention when writing closid to MSR and
>    creating closid by a user.

Fenghua, Peter, what about all the discussion v15 got
about this interface being just wrong? Where's that
addressed?

 - https://lkml.org/lkml/2015/11/18/637

 - http://lkml.iu.edu/hypermail/linux/kernel/1511.0/02375.html
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#1297515

Hello, Fenghua, Ingo.

So, I'm seeing this patchset in -next and it looks like it came
through -tip.  What's going on?

Thanks.

-- 
tejun
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