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[PATCH v2] spi-fsl-dspi: Fix CTAR Register access

Started byBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
First post2015-12-10 07:00 +0100
Last post2015-12-10 17:50 +0100
Articles 6 — 3 participants

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  [PATCH v2] spi-fsl-dspi: Fix CTAR Register access Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> - 2015-12-10 07:00 +0100
    Re: [PATCH v2] spi-fsl-dspi: Fix CTAR Register access Alexander Stein <alexander.stein@systec-electronic.com> - 2015-12-10 08:20 +0100
      Re: [PATCH v2] spi-fsl-dspi: Fix CTAR Register access Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> - 2015-12-10 09:50 +0100
        Re: [PATCH v2] spi-fsl-dspi: Fix CTAR Register access Alexander Stein <alexander.stein@systec-electronic.com> - 2015-12-10 10:10 +0100
          Re: [PATCH v2] spi-fsl-dspi: Fix CTAR Register access Stefan Agner <stefan@agner.ch> - 2015-12-10 17:40 +0100
    Re: [PATCH v2] spi-fsl-dspi: Fix CTAR Register access Stefan Agner <stefan@agner.ch> - 2015-12-10 17:50 +0100

#1288217 — [PATCH v2] spi-fsl-dspi: Fix CTAR Register access

FromBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Date2015-12-10 07:00 +0100
Subject[PATCH v2] spi-fsl-dspi: Fix CTAR Register access
Message-ID<qE2qL-1W9-9@gated-at.bofh.it>
DSPI instances in Vybrid have a different amount of chip selects
and CTARs (Clock and transfer Attributes Register). In case of
DSPI1 we only have 2 CTAR registers and 4 CS. In present driver
implementation CTAR offset is derived from CS instance which will
lead to out of bound access if chip select instance is greater than
CTAR register instance, hence use single CTAR0 register for all CS
instances. Since we write the CTAR register anyway before each access,
there is no value in using the additional CTAR registers. Also one
should not program a value in CTAS for a CTAR register that is not
present, hence configure CTAS to use CTAR0.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
---
 drivers/spi/spi-fsl-dspi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
index 59a1143..39412c9 100644
--- a/drivers/spi/spi-fsl-dspi.c
+++ b/drivers/spi/spi-fsl-dspi.c
@@ -167,7 +167,7 @@ static inline int is_double_byte_mode(struct fsl_dspi *dspi)
 {
 	unsigned int val;
 
-	regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
+	regmap_read(dspi->regmap, SPI_CTAR(0), &val);
 
 	return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
 }
@@ -257,7 +257,7 @@ static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word)
 
 	return	SPI_PUSHR_TXDATA(d16) |
 		SPI_PUSHR_PCS(dspi->cs) |
-		SPI_PUSHR_CTAS(dspi->cs) |
+		SPI_PUSHR_CTAS(0) |
 		SPI_PUSHR_CONT;
 }
 
@@ -290,7 +290,7 @@ static int dspi_eoq_write(struct fsl_dspi *dspi)
 		 */
 		if (tx_word && (dspi->len == 1)) {
 			dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
-			regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
+			regmap_update_bits(dspi->regmap, SPI_CTAR(0),
 					SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
 			tx_word = 0;
 		}
@@ -339,7 +339,7 @@ static int dspi_tcfq_write(struct fsl_dspi *dspi)
 
 	if (tx_word && (dspi->len == 1)) {
 		dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
-		regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
+		regmap_update_bits(dspi->regmap, SPI_CTAR(0),
 				SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
 		tx_word = 0;
 	}
@@ -407,7 +407,7 @@ static int dspi_transfer_one_message(struct spi_master *master,
 		regmap_update_bits(dspi->regmap, SPI_MCR,
 				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
 				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
-		regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
+		regmap_write(dspi->regmap, SPI_CTAR(0),
 				dspi->cur_chip->ctar_val);
 
 		trans_mode = dspi->devtype_data->trans_mode;
@@ -566,7 +566,7 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
 		if (!dspi->len) {
 			if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) {
 				regmap_update_bits(dspi->regmap,
-						   SPI_CTAR(dspi->cs),
+						   SPI_CTAR(0),
 						   SPI_FRAME_BITS_MASK,
 						   SPI_FRAME_BITS(16));
 				dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM;
-- 
2.6.2

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#1288244

FromAlexander Stein <alexander.stein@systec-electronic.com>
Date2015-12-10 08:20 +0100
Message-ID<qE3G9-2Ub-1@gated-at.bofh.it>
In reply to#1288217
On Thursday 10 December 2015 11:25:30, Bhuvanchandra DV wrote:
> DSPI instances in Vybrid have a different amount of chip selects
> and CTARs (Clock and transfer Attributes Register). In case of
> DSPI1 we only have 2 CTAR registers and 4 CS. In present driver
> implementation CTAR offset is derived from CS instance which will
> lead to out of bound access if chip select instance is greater than
> CTAR register instance, hence use single CTAR0 register for all CS
> instances. Since we write the CTAR register anyway before each access,
> there is no value in using the additional CTAR registers. Also one
> should not program a value in CTAS for a CTAR register that is not
> present, hence configure CTAS to use CTAR0.

Shouldn't the information put into struct fsl_dspi_devtype_data how much CTAR and CS the actual implementation has available? E.g. LS1021A has 6 CS and 4 CTAR

Best regards,
Alexander
-- 
-----
Please note our closure period for Christmas vacation and turn of the year
We are closed from 21st December 2015 to 3rd January 2016
-----
Dipl.-Inf. Alexander Stein
SYS TEC electronic GmbH
alexander.stein@systec-electronic.com

Legal and Commercial Address:
Am Windrad 2
08468 Heinsdorfergrund
Germany

Office: +49 (0) 3765 38600-0
Fax:    +49 (0) 3765 38600-4100
 
Managing Directors:
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	Director Commercial Affairs/COO: Dipl. Ing. (FH) Armin von Collrepp
Commercial Registry:
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#1288365

FromBhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Date2015-12-10 09:50 +0100
Message-ID<qE55f-3L0-13@gated-at.bofh.it>
In reply to#1288244
On 12/10/2015 12:45 PM, Alexander Stein wrote:
> On Thursday 10 December 2015 11:25:30, Bhuvanchandra DV wrote:
>> DSPI instances in Vybrid have a different amount of chip selects
>> and CTARs (Clock and transfer Attributes Register). In case of
>> DSPI1 we only have 2 CTAR registers and 4 CS. In present driver
>> implementation CTAR offset is derived from CS instance which will
>> lead to out of bound access if chip select instance is greater than
>> CTAR register instance, hence use single CTAR0 register for all CS
>> instances. Since we write the CTAR register anyway before each access,
>> there is no value in using the additional CTAR registers. Also one
>> should not program a value in CTAS for a CTAR register that is not
>> present, hence configure CTAS to use CTAR0.
>
> Shouldn't the information put into struct fsl_dspi_devtype_data how much CTAR and CS the actual implementation has available? E.g. LS1021A has 6 CS and 4 CTAR

I guess still this will not help us when CS instance greater than CTAR 
instance is selected. Other point to consider here is we are writing the 
CTAR register before every access, so for us there is no additional 
advantage of using multiple CTAR registers.

>
> Best regards,
> Alexander
>

-- 
Best regards,
Bhuvan
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#1288371

FromAlexander Stein <alexander.stein@systec-electronic.com>
Date2015-12-10 10:10 +0100
Message-ID<qE5oC-47J-1@gated-at.bofh.it>
In reply to#1288365
On Thursday 10 December 2015 14:14:11, Bhuvanchandra DV wrote:
> On 12/10/2015 12:45 PM, Alexander Stein wrote:
> > On Thursday 10 December 2015 11:25:30, Bhuvanchandra DV wrote:
> >> DSPI instances in Vybrid have a different amount of chip selects
> >> and CTARs (Clock and transfer Attributes Register). In case of
> >> DSPI1 we only have 2 CTAR registers and 4 CS. In present driver
> >> implementation CTAR offset is derived from CS instance which will
> >> lead to out of bound access if chip select instance is greater than
> >> CTAR register instance, hence use single CTAR0 register for all CS
> >> instances. Since we write the CTAR register anyway before each access,
> >> there is no value in using the additional CTAR registers. Also one
> >> should not program a value in CTAS for a CTAR register that is not
> >> present, hence configure CTAS to use CTAR0.
> >
> > Shouldn't the information put into struct fsl_dspi_devtype_data how much CTAR and CS the actual implementation has available? E.g. LS1021A has 6 CS and 4 CTAR
> 
> I guess still this will not help us when CS instance greater than CTAR 
> instance is selected. Other point to consider here is we are writing the 
> CTAR register before every access, so for us there is no additional 
> advantage of using multiple CTAR registers.

Please have a look at 5cc7b04740effa5cc0af53f434134b5859d58b73 which addresses this problem for the 4 CTAR and 6 CS case.
I'm unsure how multiple CTAR will help at all. But at the end the amount of CS seems to be different for different implementations. So this still needs to be added to fsl_dspi_devtype_data.

Best regards,
Alexander
-- 
-----
Please note our closure period for Christmas vacation and turn of the year
We are closed from 21st December 2015 to 3rd January 2016
-----
Dipl.-Inf. Alexander Stein
SYS TEC electronic GmbH
alexander.stein@systec-electronic.com

Legal and Commercial Address:
Am Windrad 2
08468 Heinsdorfergrund
Germany

Office: +49 (0) 3765 38600-0
Fax:    +49 (0) 3765 38600-4100
 
Managing Directors:
	Director Technology/CEO: Dipl.-Phys. Siegmar Schmidt;
	Director Commercial Affairs/COO: Dipl. Ing. (FH) Armin von Collrepp
Commercial Registry:
	Amtsgericht Chemnitz, HRB 28082; USt.-Id Nr. DE150534010

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#1288653

FromStefan Agner <stefan@agner.ch>
Date2015-12-10 17:40 +0100
Message-ID<qEcq6-cf-1@gated-at.bofh.it>
In reply to#1288371
On 2015-12-10 01:06, Alexander Stein wrote:
> On Thursday 10 December 2015 14:14:11, Bhuvanchandra DV wrote:
>> On 12/10/2015 12:45 PM, Alexander Stein wrote:
>> > On Thursday 10 December 2015 11:25:30, Bhuvanchandra DV wrote:
>> >> DSPI instances in Vybrid have a different amount of chip selects
>> >> and CTARs (Clock and transfer Attributes Register). In case of
>> >> DSPI1 we only have 2 CTAR registers and 4 CS. In present driver
>> >> implementation CTAR offset is derived from CS instance which will
>> >> lead to out of bound access if chip select instance is greater than
>> >> CTAR register instance, hence use single CTAR0 register for all CS
>> >> instances. Since we write the CTAR register anyway before each access,
>> >> there is no value in using the additional CTAR registers. Also one
>> >> should not program a value in CTAS for a CTAR register that is not
>> >> present, hence configure CTAS to use CTAR0.
>> >
>> > Shouldn't the information put into struct fsl_dspi_devtype_data how much CTAR and CS the actual implementation has available? E.g. LS1021A has 6 CS and 4 CTAR
>>
>> I guess still this will not help us when CS instance greater than CTAR
>> instance is selected. Other point to consider here is we are writing the
>> CTAR register before every access, so for us there is no additional
>> advantage of using multiple CTAR registers.
> 
> Please have a look at 5cc7b04740effa5cc0af53f434134b5859d58b73 which
> addresses this problem for the 4 CTAR and 6 CS case.
> I'm unsure how multiple CTAR will help at all. But at the end the
> amount of CS seems to be different for different implementations. So
> this still needs to be added to fsl_dspi_devtype_data.

IMO the multiple CTAR registers are only really helpful for
bare-metal/microcontroller kind of application where you want to safe
every register write. The Kernel anyway writes the register before each
transfer, so there is no value making use of the multiple registers...

By just using the first CTAR, it is not required to have the amount of
CS around, the SPI frameowork takes care of assigning the CS, and that
is all what is needed...

--
Stefan
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#1288667

FromStefan Agner <stefan@agner.ch>
Date2015-12-10 17:50 +0100
Message-ID<qEczN-gM-43@gated-at.bofh.it>
In reply to#1288217
On 2015-12-09 21:55, Bhuvanchandra DV wrote:
> DSPI instances in Vybrid have a different amount of chip selects
> and CTARs (Clock and transfer Attributes Register). In case of
> DSPI1 we only have 2 CTAR registers and 4 CS. In present driver
> implementation CTAR offset is derived from CS instance which will
> lead to out of bound access if chip select instance is greater than
> CTAR register instance, hence use single CTAR0 register for all CS
> instances. Since we write the CTAR register anyway before each access,
> there is no value in using the additional CTAR registers. Also one
> should not program a value in CTAS for a CTAR register that is not
> present, hence configure CTAS to use CTAR0.

This looks to me to be the easiest way to solve the issue for all DSPI
instances.

Acked-by: Stefan Agner <stefan@agner.ch>

> 
> Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> ---
>  drivers/spi/spi-fsl-dspi.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c
> index 59a1143..39412c9 100644
> --- a/drivers/spi/spi-fsl-dspi.c
> +++ b/drivers/spi/spi-fsl-dspi.c
> @@ -167,7 +167,7 @@ static inline int is_double_byte_mode(struct fsl_dspi *dspi)
>  {
>  	unsigned int val;
>  
> -	regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
> +	regmap_read(dspi->regmap, SPI_CTAR(0), &val);
>  
>  	return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
>  }
> @@ -257,7 +257,7 @@ static u32 dspi_data_to_pushr(struct fsl_dspi
> *dspi, int tx_word)
>  
>  	return	SPI_PUSHR_TXDATA(d16) |
>  		SPI_PUSHR_PCS(dspi->cs) |
> -		SPI_PUSHR_CTAS(dspi->cs) |
> +		SPI_PUSHR_CTAS(0) |
>  		SPI_PUSHR_CONT;
>  }
>  
> @@ -290,7 +290,7 @@ static int dspi_eoq_write(struct fsl_dspi *dspi)
>  		 */
>  		if (tx_word && (dspi->len == 1)) {
>  			dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
> -			regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
> +			regmap_update_bits(dspi->regmap, SPI_CTAR(0),
>  					SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
>  			tx_word = 0;
>  		}
> @@ -339,7 +339,7 @@ static int dspi_tcfq_write(struct fsl_dspi *dspi)
>  
>  	if (tx_word && (dspi->len == 1)) {
>  		dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
> -		regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
> +		regmap_update_bits(dspi->regmap, SPI_CTAR(0),
>  				SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
>  		tx_word = 0;
>  	}
> @@ -407,7 +407,7 @@ static int dspi_transfer_one_message(struct
> spi_master *master,
>  		regmap_update_bits(dspi->regmap, SPI_MCR,
>  				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
>  				SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
> -		regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
> +		regmap_write(dspi->regmap, SPI_CTAR(0),
>  				dspi->cur_chip->ctar_val);
>  
>  		trans_mode = dspi->devtype_data->trans_mode;
> @@ -566,7 +566,7 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id)
>  		if (!dspi->len) {
>  			if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) {
>  				regmap_update_bits(dspi->regmap,
> -						   SPI_CTAR(dspi->cs),
> +						   SPI_CTAR(0),
>  						   SPI_FRAME_BITS_MASK,
>  						   SPI_FRAME_BITS(16));
>  				dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM;
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