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| Started by | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| First post | 2015-12-09 05:20 +0100 |
| Last post | 2015-12-10 05:30 +0100 |
| Articles | 3 — 2 participants |
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[PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 Chanwoo Choi <cw00.choi@samsung.com> - 2015-12-09 05:20 +0100
Re: [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-10 04:20 +0100
Re: [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 Chanwoo Choi <cw00.choi@samsung.com> - 2015-12-10 05:30 +0100
| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2015-12-09 05:20 +0100 |
| Subject | [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 |
| Message-ID | <qDEop-3mU-7@gated-at.bofh.it> |
This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
Exynos4x12 has the following AXI buses to translate data
between DRAM and DMC/ACP/C2C.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index b77dac61ffb5..3bcf0939755e 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -282,6 +282,78 @@
clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
#iommu-cells = <0>;
};
+
+ bus_dmc: bus_dmc {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_DMC>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_acp: bus_acp {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_ACP>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_acp_opp_table>;
+ status = "disabled";
+ };
+
+ bus_c2c: bus_c2c {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DIV_C2C>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_dmc_opp_table>;
+ status = "disabled";
+ };
+
+ bus_dmc_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <900000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <900000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <900000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+
+ bus_acp_opp_table: opp_table2 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <900000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <134000000>;
+ opp-microvolt = <900000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <900000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <950000>;
+ };
+ };
};
&combiner {
--
1.9.1
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| From | Krzysztof Kozlowski <k.kozlowski@samsung.com> |
|---|---|
| Date | 2015-12-10 04:20 +0100 |
| Subject | Re: [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 |
| Message-ID | <qDZVU-u1-7@gated-at.bofh.it> |
| In reply to | #1287081 |
On 09.12.2015 13:08, Chanwoo Choi wrote:
> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
s/noes/nodes/
> Exynos4x12 has the following AXI buses to translate data
> between DRAM and DMC/ACP/C2C.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
> index b77dac61ffb5..3bcf0939755e 100644
> --- a/arch/arm/boot/dts/exynos4x12.dtsi
> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
> @@ -282,6 +282,78 @@
> clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
> #iommu-cells = <0>;
> };
> +
> + bus_dmc: bus_dmc {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_DIV_DMC>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_dmc_opp_table>;
> + status = "disabled";
> + };
> +
> + bus_acp: bus_acp {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_DIV_ACP>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_acp_opp_table>;
> + status = "disabled";
> + };
> +
> + bus_c2c: bus_c2c {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_DIV_C2C>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_dmc_opp_table>;
> + status = "disabled";
> + };
> +
> + bus_dmc_opp_table: opp_table1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp00 {
> + opp-hz = /bits/ 64 <100000000>;
> + opp-microvolt = <900000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <134000000>;
> + opp-microvolt = <900000>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <160000000>;
> + opp-microvolt = <900000>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-microvolt = <950000>;
The exyno4_bus.c (from mainline) uses 267 MHz here. Why choosing 200 MHz?
Best regards,
Krzysztof
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| From | Chanwoo Choi <cw00.choi@samsung.com> |
|---|---|
| Date | 2015-12-10 05:30 +0100 |
| Subject | Re: [PATCH v2 13/19] ARM: dts: Add bus nodes using VDD_MIF for Exynos4x12 |
| Message-ID | <qE11E-17Q-19@gated-at.bofh.it> |
| In reply to | #1288168 |
On 2015년 12월 10일 12:17, Krzysztof Kozlowski wrote:
> On 09.12.2015 13:08, Chanwoo Choi wrote:
>> This patch adds the bus noes using VDD_MIF for Exynos4x12 SoC.
>
> s/noes/nodes/
OK.
>
>> Exynos4x12 has the following AXI buses to translate data
>> between DRAM and DMC/ACP/C2C.
>>
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
>> arch/arm/boot/dts/exynos4x12.dtsi | 72 +++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 72 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
>> index b77dac61ffb5..3bcf0939755e 100644
>> --- a/arch/arm/boot/dts/exynos4x12.dtsi
>> +++ b/arch/arm/boot/dts/exynos4x12.dtsi
>> @@ -282,6 +282,78 @@
>> clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
>> #iommu-cells = <0>;
>> };
>> +
>> + bus_dmc: bus_dmc {
>> + compatible = "samsung,exynos-bus";
>> + clocks = <&clock CLK_DIV_DMC>;
>> + clock-names = "bus";
>> + operating-points-v2 = <&bus_dmc_opp_table>;
>> + status = "disabled";
>> + };
>> +
>> + bus_acp: bus_acp {
>> + compatible = "samsung,exynos-bus";
>> + clocks = <&clock CLK_DIV_ACP>;
>> + clock-names = "bus";
>> + operating-points-v2 = <&bus_acp_opp_table>;
>> + status = "disabled";
>> + };
>> +
>> + bus_c2c: bus_c2c {
>> + compatible = "samsung,exynos-bus";
>> + clocks = <&clock CLK_DIV_C2C>;
>> + clock-names = "bus";
>> + operating-points-v2 = <&bus_dmc_opp_table>;
>> + status = "disabled";
>> + };
>> +
>> + bus_dmc_opp_table: opp_table1 {
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> +
>> + opp00 {
>> + opp-hz = /bits/ 64 <100000000>;
>> + opp-microvolt = <900000>;
>> + };
>> + opp01 {
>> + opp-hz = /bits/ 64 <134000000>;
>> + opp-microvolt = <900000>;
>> + };
>> + opp02 {
>> + opp-hz = /bits/ 64 <160000000>;
>> + opp-microvolt = <900000>;
>> + };
>> + opp03 {
>> + opp-hz = /bits/ 64 <200000000>;
>> + opp-microvolt = <950000>;
>
> The exyno4_bus.c (from mainline) uses 267 MHz here. Why choosing 200 MHz?
There is no special reason.
I'll change it (200MHz -> 267MHz).
Best Regards,
Chanwoo Choi
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