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[PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks

Started byMarek Szyprowski <m.szyprowski@samsung.com>
First post2015-12-08 14:50 +0100
Last post2015-12-09 14:40 +0100
Articles 8 — 3 participants

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  [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block  clocks Marek Szyprowski <m.szyprowski@samsung.com> - 2015-12-08 14:50 +0100
    [PATCH 2/2] ARM: dts: exynos542x: add GSCL block parent clock  management to pm domain Marek Szyprowski <m.szyprowski@samsung.com> - 2015-12-08 14:50 +0100
      Re: [PATCH 2/2] ARM: dts: exynos542x: add GSCL block parent clock  management to pm domain Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-09 06:00 +0100
        [PATCH v2 2/2] ARM: dts: exynos542x: add GSCL block parent clock  management to pm domain Marek Szyprowski <m.szyprowski@samsung.com> - 2015-12-09 09:10 +0100
          Re: [PATCH v2 2/2] ARM: dts: exynos542x: add GSCL block parent clock  management to pm domain Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-09 14:40 +0100
    Re: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL  block clocks Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-09 06:00 +0100
      Re: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL  block clocks Sylwester Nawrocki <s.nawrocki@samsung.com> - 2015-12-09 11:20 +0100
        Re: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL  block clocks Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2015-12-09 14:40 +0100

#1286490 — [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks

FromMarek Szyprowski <m.szyprowski@samsung.com>
Date2015-12-08 14:50 +0100
Subject[PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks
Message-ID<qDqOu-30G-15@gated-at.bofh.it>
This patch adds clocks, which are required for preserving parent clock
configuration on GSCL power domain on/off.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c   | 8 ++++----
 include/dt-bindings/clock/exynos5420.h | 2 ++
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 389af3c..4bae2e3 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -677,8 +677,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 			SRC_TOP5, 20, 1),
 	MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
 			mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
-	MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
-			SRC_TOP5, 28, 1),
+	MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
+			mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
 
 	MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
 	MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
@@ -729,8 +729,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 			SRC_TOP12, 20, 1),
 	MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
 			mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
-	MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
-			SRC_TOP12, 28, 1),
+	MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
+			mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
 
 	/* DISP1 Block */
 	MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 99da0d1..b5af23a 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -210,6 +210,8 @@
 #define CLK_MOUT_SW_ACLK300     649
 #define CLK_MOUT_USER_ACLK400_DISP1     650
 #define CLK_MOUT_SW_ACLK400     651
+#define CLK_MOUT_USER_ACLK300_GSCL	652
+#define CLK_MOUT_SW_ACLK300_GSCL	653
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
-- 
1.9.2

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#1286493 — [PATCH 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain

FromMarek Szyprowski <m.szyprowski@samsung.com>
Date2015-12-08 14:50 +0100
Subject[PATCH 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain
Message-ID<qDqOu-30G-27@gated-at.bofh.it>
In reply to#1286490
Add support for restoring GScaler parent clocks configuration when GSCL
power domain is turned on.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 48a0a55..912143e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -252,8 +252,10 @@
 		compatible = "samsung,exynos4210-pd";
 		reg = <0x10044000 0x20>;
 		#power-domain-cells = <0>;
-		clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
-		clock-names = "asb0", "asb1";
+		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK300_GSCL>,
+			<&clock CLK_MOUT_USER_ACLK300_GSCL>, <&clock CLK_GSCL0>,
+			<&clock CLK_GSCL1>;
+		clock-names = "oscclk", "pclk0", "clk0", "asb0", "asb1";
 	};
 
 	isp_pd: power-domain@10044020 {
-- 
1.9.2

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#1287108 — Re: [PATCH 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2015-12-09 06:00 +0100
SubjectRe: [PATCH 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain
Message-ID<qDF18-3C2-9@gated-at.bofh.it>
In reply to#1286493
On 08.12.2015 22:46, Marek Szyprowski wrote:
> Add support for restoring GScaler parent clocks configuration when GSCL
> power domain is turned on.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420.dtsi | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index 48a0a55..912143e 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -252,8 +252,10 @@
>  		compatible = "samsung,exynos4210-pd";
>  		reg = <0x10044000 0x20>;
>  		#power-domain-cells = <0>;
> -		clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
> -		clock-names = "asb0", "asb1";
> +		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK300_GSCL>,
> +			<&clock CLK_MOUT_USER_ACLK300_GSCL>, <&clock CLK_GSCL0>,
> +			<&clock CLK_GSCL1>;
> +		clock-names = "oscclk", "pclk0", "clk0", "asb0", "asb1";

The pclkN name is not used.

Best regards,
Krzysztof

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#1287174 — [PATCH v2 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain

FromMarek Szyprowski <m.szyprowski@samsung.com>
Date2015-12-09 09:10 +0100
Subject[PATCH v2 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain
Message-ID<qDHYZ-5KQ-11@gated-at.bofh.it>
In reply to#1287108
Add support for restoring GScaler parent clocks configuration when GSCL
power domain is turned on.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm/boot/dts/exynos5420.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 1b3d6c7..5d00c18 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -252,8 +252,10 @@
 		compatible = "samsung,exynos4210-pd";
 		reg = <0x10044000 0x20>;
 		#power-domain-cells = <0>;
-		clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
-		clock-names = "asb0", "asb1";
+		clocks = <&clock CLK_FIN_PLL>,
+			 <&clock CLK_MOUT_USER_ACLK300_GSCL>,
+			 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
+		clock-names = "oscclk", "clk0", "asb0", "asb1";
 	};
 
 	isp_pd: power-domain@10044020 {
-- 
1.9.2

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#1287503 — Re: [PATCH v2 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2015-12-09 14:40 +0100
SubjectRe: [PATCH v2 2/2] ARM: dts: exynos542x: add GSCL block parent clock management to pm domain
Message-ID<qDN8n-xe-41@gated-at.bofh.it>
In reply to#1287174
W dniu 09.12.2015 o 17:07, Marek Szyprowski pisze:
> Add support for restoring GScaler parent clocks configuration when GSCL
> power domain is turned on.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5420.dtsi | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)

Changelog is always nice, even though the traffic on samsung-soc is not
huge now.

Anyway, thanks for update:

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof
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#1287107 — Re: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2015-12-09 06:00 +0100
SubjectRe: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks
Message-ID<qDF18-3C2-7@gated-at.bofh.it>
In reply to#1286490
On 08.12.2015 22:46, Marek Szyprowski wrote:
> This patch adds clocks, which are required for preserving parent clock
> configuration on GSCL power domain on/off.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c   | 8 ++++----
>  include/dt-bindings/clock/exynos5420.h | 2 ++
>  2 files changed, 6 insertions(+), 4 deletions(-)

I suppose that, with ack from clock folks, this can go through samsung-soc?

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Best regards,
Krzysztof
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#1287336 — Re: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks

FromSylwester Nawrocki <s.nawrocki@samsung.com>
Date2015-12-09 11:20 +0100
SubjectRe: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks
Message-ID<qDK0N-71Y-3@gated-at.bofh.it>
In reply to#1287107
Adding Stephen and linux-clk at Cc.

On 09/12/15 05:49, Krzysztof Kozlowski wrote:
> On 08.12.2015 22:46, Marek Szyprowski wrote:
>> > This patch adds clocks, which are required for preserving parent clock
>> > configuration on GSCL power domain on/off.
>> > 
>> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> > ---
>> >  drivers/clk/samsung/clk-exynos5420.c   | 8 ++++----
>> >  include/dt-bindings/clock/exynos5420.h | 2 ++
>> >  2 files changed, 6 insertions(+), 4 deletions(-)
>
> I suppose that, with ack from clock folks, this can go through samsung-soc?

I guess it makes more sense that making a stable branch with just
this patch to be pulled into arm-soc and clk tree. I'm fine with
applying this patch through arm-soc, but I think we also need
Mike's or Stephen ack for this.

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

-- 
Thanks,
Sylwester
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#1287499 — Re: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks

FromKrzysztof Kozlowski <k.kozlowski@samsung.com>
Date2015-12-09 14:40 +0100
SubjectRe: [PATCH 1/2] clk: samsung: exynos5422: add missing parent GSCL block clocks
Message-ID<qDN8m-xe-19@gated-at.bofh.it>
In reply to#1287336
W dniu 09.12.2015 o 19:14, Sylwester Nawrocki pisze:
> Adding Stephen and linux-clk at Cc.
> 
> On 09/12/15 05:49, Krzysztof Kozlowski wrote:
>> On 08.12.2015 22:46, Marek Szyprowski wrote:
>>>> This patch adds clocks, which are required for preserving parent clock
>>>> configuration on GSCL power domain on/off.
>>>>
>>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>>> ---
>>>>  drivers/clk/samsung/clk-exynos5420.c   | 8 ++++----
>>>>  include/dt-bindings/clock/exynos5420.h | 2 ++
>>>>  2 files changed, 6 insertions(+), 4 deletions(-)
>>
>> I suppose that, with ack from clock folks, this can go through samsung-soc?
> 
> I guess it makes more sense that making a stable branch with just
> this patch to be pulled into arm-soc and clk tree. I'm fine with
> applying this patch through arm-soc, but I think we also need
> Mike's or Stephen ack for this.
> 
> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

I am fine with the branch approach (actually in such cases I make them
anyway just in case).

As you suggested I'll wait for Mike's or Stepen's acks.

BR,
Krzysztof

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