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| Started by | yankejian <yankejian@huawei.com> |
|---|---|
| First post | 2015-12-05 08:50 +0100 |
| Last post | 2015-12-05 09:00 +0100 |
| Articles | 7 — 4 participants |
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[PATCH RESEND net-next 0/3] dts: hisi: fixes can't find eth for hip05-D02 yankejian <yankejian@huawei.com> - 2015-12-05 08:50 +0100
[PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio yankejian <yankejian@huawei.com> - 2015-12-05 08:50 +0100
[PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board yankejian <yankejian@huawei.com> - 2015-12-05 08:50 +0100
Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board Rob Herring <robh@kernel.org> - 2015-12-07 14:20 +0100
Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board Bintian <bintian.wang@huawei.com> - 2015-12-07 14:50 +0100
Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board "Yankejian (Hackim Yim)" <yankejian@huawei.com> - 2015-12-08 02:50 +0100
Re: [PATCH RESEND net-next 0/3] dts: hisi: fixes can't find eth for hip05-D02 "Yankejian (Hackim Yim)" <yankejian@huawei.com> - 2015-12-05 09:00 +0100
| From | yankejian <yankejian@huawei.com> |
|---|---|
| Date | 2015-12-05 08:50 +0100 |
| Subject | [PATCH RESEND net-next 0/3] dts: hisi: fixes can't find eth for hip05-D02 |
| Message-ID | <qCfBM-5YV-3@gated-at.bofh.it> |
this patchset fixes the bug that eth can't initial successful on hip05-D02 because the dts files doesn't match the source code. yankejian (3): dts: hisi: enables the ethX for D02 board dts: hisi: fixes no syscon error when init mdio arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++ arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++-- 4 files changed, 38 insertions(+), 2 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | yankejian <yankejian@huawei.com> |
|---|---|
| Date | 2015-12-05 08:50 +0100 |
| Subject | [PATCH RESEND net-next 2/3] dts: hisi: fixes no syscon error when init mdio |
| Message-ID | <qCfLr-66U-9@gated-at.bofh.it> |
| In reply to | #1284477 |
when linux start up, we get the log below:
"Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl
mdio_bus mdio@803c0000: mdio sys ctl reg has not maped "
the source code about the subctrl is dealled with syscon, but dts doesn't.
it cause such fault. so this patch adds the syscon info on dts files to
fixes it.
Signed-off-by: yankejian <yankejian@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++
arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index 4ff16d0..daaca63 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -246,6 +246,10 @@
clock-frequency = <200000000>;
};
+ peri_c_subctrl: sub_ctrl_c@80000000 {
+ compatible = "hisilicon,peri-c-subctrl", "syscon";
+ reg = < 0x0 0x80000000 0x0 0x10000>;
+ };
uart0: uart@80300000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x80300000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
index 606dd5a..4d4815e 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
@@ -10,8 +10,8 @@ soc0: soc@000000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "hisilicon,hns-mdio";
- reg = <0x0 0x803c0000 0x0 0x10000
- 0x0 0x80000000 0x0 0x10000>;
+ reg = <0x0 0x803c0000 0x0 0x10000>;
+ subctrl_vbase = <&peri_c_subctrl>;
soc0_phy0: ethernet-phy@0 {
reg = <0x0>;
--
1.9.1
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| From | yankejian <yankejian@huawei.com> |
|---|---|
| Date | 2015-12-05 08:50 +0100 |
| Subject | [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board |
| Message-ID | <qCfLs-66U-13@gated-at.bofh.it> |
| In reply to | #1284477 |
This patch adds documentation for the devicetree bindings used by the
DT files of Hisilicon Hip05-D02 development board.
Signed-off-by: yankejian <yankejian@huawei.com>
---
.../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 6ac7c00..5318d78 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -187,6 +187,22 @@ Example:
reg = <0xb0000000 0x10000>;
};
+Hisilicon HiP05 PERISUB system controller
+
+Required properties:
+- compatible : "hisilicon,peri-c-subctrl", "syscon";
+- reg : Register address and size
+
+The HiP05 PERISUB system controller is shared by peripheral controllers in
+HiP05 Soc to implement some basic configurations. the peripheral
+ controllers include mdio, ddr, iic, uart, timer and so on.
+
+Example:
+ /* for HiP05 PCIe-SAS system */
+ pcie_sas: system_controller@0xb0000000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+ reg = <0xb0000000 0x10000>;
+ };
-----------------------------------------------------------------------
Hisilicon CPU controller
--
1.9.1
--
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| From | Rob Herring <robh@kernel.org> |
|---|---|
| Date | 2015-12-07 14:20 +0100 |
| Subject | Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board |
| Message-ID | <qD3RU-4Wd-15@gated-at.bofh.it> |
| In reply to | #1284480 |
On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
> This patch adds documentation for the devicetree bindings used by the
> DT files of Hisilicon Hip05-D02 development board.
>
> Signed-off-by: yankejian <yankejian@huawei.com>
> ---
> .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> index 6ac7c00..5318d78 100644
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> @@ -187,6 +187,22 @@ Example:
> reg = <0xb0000000 0x10000>;
> };
>
> +Hisilicon HiP05 PERISUB system controller
> +
> +Required properties:
> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
This should be more specific and have the SOC name in it.
> +- reg : Register address and size
> +
> +The HiP05 PERISUB system controller is shared by peripheral controllers in
> +HiP05 Soc to implement some basic configurations. the peripheral
> + controllers include mdio, ddr, iic, uart, timer and so on.
> +
> +Example:
> + /* for HiP05 PCIe-SAS system */
> + pcie_sas: system_controller@0xb0000000 {
> + compatible = "hisilicon,pcie-sas-subctrl", "syscon";
The example doesn't match.
> + reg = <0xb0000000 0x10000>;
> + };
> -----------------------------------------------------------------------
> Hisilicon CPU controller
>
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
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| From | Bintian <bintian.wang@huawei.com> |
|---|---|
| Date | 2015-12-07 14:50 +0100 |
| Subject | Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board |
| Message-ID | <qD4kW-56d-7@gated-at.bofh.it> |
| In reply to | #1285292 |
On 2015/12/7 21:16, Rob Herring wrote:
> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>> This patch adds documentation for the devicetree bindings used by the
>> DT files of Hisilicon Hip05-D02 development board.
>>
>> Signed-off-by: yankejian <yankejian@huawei.com>
You may need to configure as "Kejian Yan <yankejian@huawei.com>" :)
BR,
Bintian
>> ---
>> .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> index 6ac7c00..5318d78 100644
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>> @@ -187,6 +187,22 @@ Example:
>> reg = <0xb0000000 0x10000>;
>> };
>>
>> +Hisilicon HiP05 PERISUB system controller
>> +
>> +Required properties:
>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
> This should be more specific and have the SOC name in it.
>
>> +- reg : Register address and size
>> +
>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>> +HiP05 Soc to implement some basic configurations. the peripheral
>> + controllers include mdio, ddr, iic, uart, timer and so on.
>> +
>> +Example:
>> + /* for HiP05 PCIe-SAS system */
>> + pcie_sas: system_controller@0xb0000000 {
>> + compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> The example doesn't match.
>
>> + reg = <0xb0000000 0x10000>;
>> + };
>> -----------------------------------------------------------------------
>> Hisilicon CPU controller
>>
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo@vger.kernel.org
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> --
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> the body of a message to majordomo@vger.kernel.org
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>
> .
>
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| From | "Yankejian (Hackim Yim)" <yankejian@huawei.com> |
|---|---|
| Date | 2015-12-08 02:50 +0100 |
| Subject | Re: [PATCH RESEND net-next 3/3] arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board |
| Message-ID | <qDfzH-4ag-5@gated-at.bofh.it> |
| In reply to | #1285313 |
On 2015/12/7 21:48, Bintian wrote:
> On 2015/12/7 21:16, Rob Herring wrote:
>> On Sat, Dec 05, 2015 at 03:54:48PM +0800, yankejian wrote:
>>> This patch adds documentation for the devicetree bindings used by the
>>> DT files of Hisilicon Hip05-D02 development board.
>>>
>>> Signed-off-by: yankejian <yankejian@huawei.com>
> You may need to configure as "Kejian Yan <yankejian@huawei.com>" :)
>
> BR,
>
> Bintian
agree, thanks
BR,
Kejian Yan
>>> ---
>>> .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++
>>> 1 file changed, 16 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> index 6ac7c00..5318d78 100644
>>> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
>>> @@ -187,6 +187,22 @@ Example:
>>> reg = <0xb0000000 0x10000>;
>>> };
>>> +Hisilicon HiP05 PERISUB system controller
>>> +
>>> +Required properties:
>>> +- compatible : "hisilicon,peri-c-subctrl", "syscon";
>> This should be more specific and have the SOC name in it.
>>
>>> +- reg : Register address and size
>>> +
>>> +The HiP05 PERISUB system controller is shared by peripheral controllers in
>>> +HiP05 Soc to implement some basic configurations. the peripheral
>>> + controllers include mdio, ddr, iic, uart, timer and so on.
>>> +
>>> +Example:
>>> + /* for HiP05 PCIe-SAS system */
>>> + pcie_sas: system_controller@0xb0000000 {
>>> + compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> The example doesn't match.
>>
Thanks for this. I have changed this in PATCH V2 already floated.
BR
Kejian Yan
>>> + reg = <0xb0000000 0x10000>;
>>> + };
>>> -----------------------------------------------------------------------
>>> Hisilicon CPU controller
>>> --
>>> 1.9.1
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>> --
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>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at http://www.tux.org/lkml/
>>
>> .
>>
>
>
>
> .
>
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| From | "Yankejian (Hackim Yim)" <yankejian@huawei.com> |
|---|---|
| Date | 2015-12-05 09:00 +0100 |
| Subject | Re: [PATCH RESEND net-next 0/3] dts: hisi: fixes can't find eth for hip05-D02 |
| Message-ID | <qCfV9-6f3-17@gated-at.bofh.it> |
| In reply to | #1284477 |
sorry, pls ignore this patchset. On 2015/12/5 15:54, yankejian wrote: > this patchset fixes the bug that eth can't initial successful on hip05-D02 > because the dts files doesn't match the source code. > > yankejian (3): > dts: hisi: enables the ethX for D02 board > dts: hisi: fixes no syscon error when init mdio > arm64: hip05-d02: Document devicetree bindings for Hisilicon D02 Board > > .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++ > arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 16 ++++++++++++++++ > arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++ > arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++-- > 4 files changed, 38 insertions(+), 2 deletions(-) > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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