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[PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC

Started byHeikki Krogerus <heikki.krogerus@linux.intel.com>
First post2015-12-01 14:40 +0100
Last post2015-12-02 10:20 +0100
Articles 6 — 3 participants

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  [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC Heikki Krogerus <heikki.krogerus@linux.intel.com> - 2015-12-01 14:40 +0100
    Re: [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC Felipe Balbi <balbi@ti.com> - 2015-12-01 21:40 +0100
      Re: [PATCH 2/2] usb: pci-quirks: register USB mux found on  Cherrytrail SOC Heikki Krogerus <heikki.krogerus@linux.intel.com> - 2015-12-02 10:20 +0100
        Re: [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC Felipe Balbi <balbi@ti.com> - 2015-12-02 15:50 +0100
    Re: [PATCH 2/2] usb: pci-quirks: register USB mux found on  Cherrytrail SOC Lu Baolu <baolu.lu@linux.intel.com> - 2015-12-02 08:10 +0100
      Re: [PATCH 2/2] usb: pci-quirks: register USB mux found on  Cherrytrail SOC Heikki Krogerus <heikki.krogerus@linux.intel.com> - 2015-12-02 10:20 +0100

#1280868 — [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC

FromHeikki Krogerus <heikki.krogerus@linux.intel.com>
Date2015-12-01 14:40 +0100
Subject[PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC
Message-ID<qATjY-1Oq-7@gated-at.bofh.it>
Intel Braswell/Cherrytrail has an internal mux that shares
one USB port between USB Device Controller and xHCI. The
same mux is found on several SOCs from Intel, but only on
a few Cherrytrail based platforms the OS is expected to
configure it. Normally BIOS takes care of it.

The driver for the mux is an "extcon" driver. With this we
only register the mux if it's detected.

Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
---
 drivers/usb/host/pci-quirks.c | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index f940056..4e3016a 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -16,6 +16,7 @@
 #include <linux/export.h>
 #include <linux/acpi.h>
 #include <linux/dmi.h>
+#include <linux/extcon/intel_usb_mux.h>
 #include "pci-quirks.h"
 #include "xhci-ext-caps.h"
 
@@ -1029,9 +1030,36 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
 	writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
 
 hc_init:
-	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
+	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 		usb_enable_intel_xhci_ports(pdev);
 
+		/*
+		 * Initialize the internal mux that shares a port between USB
+		 * Device Controller and xHCI on platforms that have it.
+		 */
+#define XHCI_INTEL_VENDOR_CAPS 192
+#define XHCI_INTEL_USB_MUX_OFFSET 0x80d8
+		ext_cap_offset = xhci_find_next_cap_offset(base,
+							XHCI_HCC_PARAMS_OFFSET);
+		ext_cap_offset = xhci_find_ext_cap_by_id(base, ext_cap_offset,
+							XHCI_INTEL_VENDOR_CAPS);
+		if (ext_cap_offset) {
+			struct intel_usb_mux *mux;
+			struct resource r;
+
+			r.start = pci_resource_start(pdev, 0) +
+					XHCI_INTEL_USB_MUX_OFFSET;
+			r.end   = r.start + 8;
+			r.flags = IORESOURCE_MEM;
+
+			mux = intel_usb_mux_register(&pdev->dev, &r);
+			if (IS_ERR(mux) && PTR_ERR(mux) == -ENOTSUPP)
+				dev_dbg(&pdev->dev, "USB mux not supported\n");
+			else if (IS_ERR(mux))
+				dev_err(&pdev->dev, "failed to register mux\n");
+		}
+	}
+
 	op_reg_base = base + XHCI_HC_LENGTH(readl(base));
 
 	/* Wait for the host controller to be ready before writing any
-- 
2.6.2

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#1281190

FromFelipe Balbi <balbi@ti.com>
Date2015-12-01 21:40 +0100
Message-ID<qAZSq-622-13@gated-at.bofh.it>
In reply to#1280868

[Multipart message — attachments visible in raw view] — view raw

Hi,

Heikki Krogerus <heikki.krogerus@linux.intel.com> writes:
> Intel Braswell/Cherrytrail has an internal mux that shares
> one USB port between USB Device Controller and xHCI. The
> same mux is found on several SOCs from Intel, but only on
> a few Cherrytrail based platforms the OS is expected to
> configure it. Normally BIOS takes care of it.
>
> The driver for the mux is an "extcon" driver. With this we
> only register the mux if it's detected.
>
> Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> ---
>  drivers/usb/host/pci-quirks.c | 30 +++++++++++++++++++++++++++++-
>  1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
> index f940056..4e3016a 100644
> --- a/drivers/usb/host/pci-quirks.c
> +++ b/drivers/usb/host/pci-quirks.c
> @@ -16,6 +16,7 @@
>  #include <linux/export.h>
>  #include <linux/acpi.h>
>  #include <linux/dmi.h>
> +#include <linux/extcon/intel_usb_mux.h>
>  #include "pci-quirks.h"
>  #include "xhci-ext-caps.h"
>  
> @@ -1029,9 +1030,36 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
>  	writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
>  
>  hc_init:
> -	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
> +	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
>  		usb_enable_intel_xhci_ports(pdev);
>  
> +		/*
> +		 * Initialize the internal mux that shares a port between USB
> +		 * Device Controller and xHCI on platforms that have it.
> +		 */
> +#define XHCI_INTEL_VENDOR_CAPS 192
> +#define XHCI_INTEL_USB_MUX_OFFSET 0x80d8
> +		ext_cap_offset = xhci_find_next_cap_offset(base,
> +							XHCI_HCC_PARAMS_OFFSET);
> +		ext_cap_offset = xhci_find_ext_cap_by_id(base, ext_cap_offset,
> +							XHCI_INTEL_VENDOR_CAPS);
> +		if (ext_cap_offset) {
> +			struct intel_usb_mux *mux;
> +			struct resource r;
> +
> +			r.start = pci_resource_start(pdev, 0) +
> +					XHCI_INTEL_USB_MUX_OFFSET;
> +			r.end   = r.start + 8;
> +			r.flags = IORESOURCE_MEM;
> +
> +			mux = intel_usb_mux_register(&pdev->dev, &r);
> +			if (IS_ERR(mux) && PTR_ERR(mux) == -ENOTSUPP)
> +				dev_dbg(&pdev->dev, "USB mux not supported\n");
> +			else if (IS_ERR(mux))
> +				dev_err(&pdev->dev, "failed to register mux\n");

IMHO, this should be creating a child device instead of calling
intel_usb_mux_register() directly. That way, your mux driver could
actually _be_ a driver. Seems like all you need to do from this point is
a register a simple platform_device which is a child of xhci, see
platform_device_register_simple() for how to do this.

Or rather, platform_device_register_rsndata() passing xhci's device
pointer as parent.

-- 
balbi

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#1281540 — Re: [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC

FromHeikki Krogerus <heikki.krogerus@linux.intel.com>
Date2015-12-02 10:20 +0100
SubjectRe: [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC
Message-ID<qBbJU-5dP-15@gated-at.bofh.it>
In reply to#1281190
Hi Felipe,

> IMHO, this should be creating a child device instead of calling
> intel_usb_mux_register() directly. That way, your mux driver could
> actually _be_ a driver. Seems like all you need to do from this point is
> a register a simple platform_device which is a child of xhci, see
> platform_device_register_simple() for how to do this.
> 
> Or rather, platform_device_register_rsndata() passing xhci's device
> pointer as parent.

That was the plan originally, but unfortunately it does not work in
this case. It creates conflict as platform_device_add() call will then
claim part of io memory belonging to xHCI, making xHCI fail to probe.


Thanks,

-- 
heikki
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#1281872

FromFelipe Balbi <balbi@ti.com>
Date2015-12-02 15:50 +0100
Message-ID<qBgTg-8qM-17@gated-at.bofh.it>
In reply to#1281540

[Multipart message — attachments visible in raw view] — view raw

Hi,

Heikki Krogerus <heikki.krogerus@linux.intel.com> writes:
> Hi Felipe,
>
>> IMHO, this should be creating a child device instead of calling
>> intel_usb_mux_register() directly. That way, your mux driver could
>> actually _be_ a driver. Seems like all you need to do from this point is
>> a register a simple platform_device which is a child of xhci, see
>> platform_device_register_simple() for how to do this.
>> 
>> Or rather, platform_device_register_rsndata() passing xhci's device
>> pointer as parent.
>
> That was the plan originally, but unfortunately it does not work in
> this case. It creates conflict as platform_device_add() call will then
> claim part of io memory belonging to xHCI, making xHCI fail to probe.

okay, understood.

-- 
balbi

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#1281492 — Re: [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC

FromLu Baolu <baolu.lu@linux.intel.com>
Date2015-12-02 08:10 +0100
SubjectRe: [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC
Message-ID<qB9I5-3XN-9@gated-at.bofh.it>
In reply to#1280868

On 12/01/2015 09:32 PM, Heikki Krogerus wrote:
> Intel Braswell/Cherrytrail has an internal mux that shares
> one USB port between USB Device Controller and xHCI. The
> same mux is found on several SOCs from Intel, but only on
> a few Cherrytrail based platforms the OS is expected to
> configure it. Normally BIOS takes care of it.
>
> The driver for the mux is an "extcon" driver. With this we
> only register the mux if it's detected.
>
> Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> ---
>  drivers/usb/host/pci-quirks.c | 30 +++++++++++++++++++++++++++++-
>  1 file changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
> index f940056..4e3016a 100644
> --- a/drivers/usb/host/pci-quirks.c
> +++ b/drivers/usb/host/pci-quirks.c
> @@ -16,6 +16,7 @@
>  #include <linux/export.h>
>  #include <linux/acpi.h>
>  #include <linux/dmi.h>
> +#include <linux/extcon/intel_usb_mux.h>
>  #include "pci-quirks.h"
>  #include "xhci-ext-caps.h"
>  
> @@ -1029,9 +1030,36 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
>  	writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
>  
>  hc_init:
> -	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
> +	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
>  		usb_enable_intel_xhci_ports(pdev);
>  
> +		/*
> +		 * Initialize the internal mux that shares a port between USB
> +		 * Device Controller and xHCI on platforms that have it.
> +		 */
> +#define XHCI_INTEL_VENDOR_CAPS 192
> +#define XHCI_INTEL_USB_MUX_OFFSET 0x80d8
> +		ext_cap_offset = xhci_find_next_cap_offset(base,
> +							XHCI_HCC_PARAMS_OFFSET);
> +		ext_cap_offset = xhci_find_ext_cap_by_id(base, ext_cap_offset,
> +							XHCI_INTEL_VENDOR_CAPS);

Hi Heikki,

This helper has been replaced with xhci_find_next_ext_cap() in
commit d5ddcdf(xhci: rework xhci extended capability list parsing functions).

Need to fix this, otherwise it will not pass compile on top of usb-next.

Thanks,
Baolu

> +		if (ext_cap_offset) {
> +			struct intel_usb_mux *mux;
> +			struct resource r;
> +
> +			r.start = pci_resource_start(pdev, 0) +
> +					XHCI_INTEL_USB_MUX_OFFSET;
> +			r.end   = r.start + 8;
> +			r.flags = IORESOURCE_MEM;
> +
> +			mux = intel_usb_mux_register(&pdev->dev, &r);
> +			if (IS_ERR(mux) && PTR_ERR(mux) == -ENOTSUPP)
> +				dev_dbg(&pdev->dev, "USB mux not supported\n");
> +			else if (IS_ERR(mux))
> +				dev_err(&pdev->dev, "failed to register mux\n");
> +		}
> +	}
> +
>  	op_reg_base = base + XHCI_HC_LENGTH(readl(base));
>  
>  	/* Wait for the host controller to be ready before writing any

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#1281539 — Re: [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC

FromHeikki Krogerus <heikki.krogerus@linux.intel.com>
Date2015-12-02 10:20 +0100
SubjectRe: [PATCH 2/2] usb: pci-quirks: register USB mux found on Cherrytrail SOC
Message-ID<qBbJT-5dP-7@gated-at.bofh.it>
In reply to#1281492
Hi,

> > @@ -1029,9 +1030,36 @@ static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
> >  	writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
> >  
> >  hc_init:
> > -	if (pdev->vendor == PCI_VENDOR_ID_INTEL)
> > +	if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
> >  		usb_enable_intel_xhci_ports(pdev);
> >  
> > +		/*
> > +		 * Initialize the internal mux that shares a port between USB
> > +		 * Device Controller and xHCI on platforms that have it.
> > +		 */
> > +#define XHCI_INTEL_VENDOR_CAPS 192
> > +#define XHCI_INTEL_USB_MUX_OFFSET 0x80d8
> > +		ext_cap_offset = xhci_find_next_cap_offset(base,
> > +							XHCI_HCC_PARAMS_OFFSET);
> > +		ext_cap_offset = xhci_find_ext_cap_by_id(base, ext_cap_offset,
> > +							XHCI_INTEL_VENDOR_CAPS);
> 
> Hi Heikki,
> 
> This helper has been replaced with xhci_find_next_ext_cap() in
> commit d5ddcdf(xhci: rework xhci extended capability list parsing functions).
> 
> Need to fix this, otherwise it will not pass compile on top of usb-next.

Thanks Baolu. I'll fix it.


Cheers,

-- 
heikki
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