Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1222789 > unrolled thread
| Started by | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| First post | 2015-09-11 14:30 +0200 |
| Last post | 2015-09-15 08:50 +0200 |
| Articles | 16 — 3 participants |
Back to article view | Back to linux.kernel
[PATCH v2 00/23] dmaengine/ARM: Merge the edma drivers into one Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:30 +0200
[PATCH v2 09/23] ARM: davinci: Use platform_device_register_full() to create pdev for eDMA Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:30 +0200
[PATCH v2 18/23] dmaengine: edma: Print warning when linking slots from different eDMA Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:30 +0200
[PATCH v2 07/23] ARM/dmaengine: edma: Public API to use private struct pointer Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:40 +0200
[PATCH v2 19/23] dmaengine: edma: Consolidate the comments for functions Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:40 +0200
[PATCH v2 08/23] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:40 +0200
[PATCH v2 10/23] ARM: davinci: Add set dma_mask to eDMA devices Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:40 +0200
[PATCH v2 17/23] dmaengine: edma: Use the edma_write_slot instead open coded memcpy_toio Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:40 +0200
[PATCH v2 04/23] ARM: davinci/common: Convert edma driver to handle one eDMA instance per driver Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:40 +0200
Re: [PATCH v2 04/23] ARM: davinci/common: Convert edma driver to handle one eDMA instance per driver Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-18 13:50 +0200
[PATCH v2 12/23] dmaengine: edma: Allocate memory dynamically for bitmaps and structures Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:40 +0200
[PATCH v2 02/23] ARM: common: edma: Remove unused functions Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:40 +0200
[PATCH v2 06/23] ARM: common: edma: Internal API to use pointer to 'struct edma' Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-11 14:40 +0200
Re: [PATCH v2 00/23] dmaengine/ARM: Merge the edma drivers into one Sekhar Nori <nsekhar@ti.com> - 2015-09-12 13:30 +0200
Re: [PATCH v2 11/23] ARM/dmaengine: edma: Merge the two drivers under drivers/dmaengine Tony Lindgren <tony@atomide.com> - 2015-09-14 18:20 +0200
Re: [PATCH v2 11/23] ARM/dmaengine: edma: Merge the two drivers under drivers/dmaengine Peter Ujfalusi <peter.ujfalusi@ti.com> - 2015-09-15 08:50 +0200
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:30 +0200 |
| Subject | [PATCH v2 00/23] dmaengine/ARM: Merge the edma drivers into one |
| Message-ID | <q7vCN-1rQ-3@gated-at.bofh.it> |
Hi,
Changes since v1:
- Convert edma platform device registration to use platform_device_register_full
- Moved the PM callback also to the dmaengine driver - missed in v1
- Commit message added to:
ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers
- New patch which reads the flag for the channel mapping support in one place
Cover letter:
with this series the edma two driver setup will be changed to have only one
driver to support eDMA3. The legacy edma interface will be removed and eDMA can
only be used via dmaengine API from this point on.
In order to do the merge the following improvements has been done:
- One driver instance per eDMA:
- Any number of eDMA instances are supported (both legacy and DT boot)
- Not relying on global variables, arrays, etc
- Code simplification and optimizations in several places
This change will also help us to do bigger changes in the eDMA driver since,
since now we have only one driver to work with.
The series has been tested on:
da850-evm (OMAP-L138)
- with legacy and DT boot (both eDMA0 and eDMA1 is enabled)
- In code swapping the eDMA instances in legacy mode to make sure the second
instance is handled correctly.
am335x-evmsk
- DT boot
I think this series could go via the dmaengine tree. Changes are trivial under
arch/arm/
Regards,
Peter
---
Peter Ujfalusi (23):
ARM: common: edma: Fix channel parameter for irq callbacks
ARM: common: edma: Remove unused functions
dmaengine: edma: Simplify and optimize the edma_execute path
ARM: davinci/common: Convert edma driver to handle one eDMA instance
per driver
ARM/dmaengine: edma: Move of_dma_controller_register to the dmaengine
driver
ARM: common: edma: Internal API to use pointer to 'struct edma'
ARM/dmaengine: edma: Public API to use private struct pointer
ARM/dmaengine: edma: Remove limitation on the number of eDMA
controllers
ARM: davinci: Use platform_device_register_full() to create pdev for
eDMA
ARM: davinci: Add set dma_mask to eDMA devices
ARM/dmaengine: edma: Merge the two drivers under drivers/dmaengine
dmaengine: edma: Allocate memory dynamically for bitmaps and
structures
dmaengine: edma: Parameter alignment and long line fixes
dmaengine: edma: Use devm_kcalloc when possible
dmaengine: edma: Cleanup regarding the use of dev around the code
dmaengine: edma: Use dev_dbg instead pr_debug
dmaengine: edma: Use the edma_write_slot instead open coded
memcpy_toio
dmaengine: edma: Print warning when linking slots from different eDMA
dmaengine: edma: Consolidate the comments for functions
dmaengine: edma: Simplify the interrupt handling
dmaengine: edma: Move the pending error check into helper function
dmaengine: edma: Simplify and optimize ccerr interrupt handler
dmaengine: edma: Read channel mapping support only once from HW
arch/arm/Kconfig | 1 -
arch/arm/common/Kconfig | 3 -
arch/arm/common/Makefile | 1 -
arch/arm/common/edma.c | 1876 ---------------------------------
arch/arm/mach-davinci/devices-da8xx.c | 122 +--
arch/arm/mach-davinci/dm355.c | 40 +-
arch/arm/mach-davinci/dm365.c | 25 +-
arch/arm/mach-davinci/dm644x.c | 40 +-
arch/arm/mach-davinci/dm646x.c | 44 +-
arch/arm/mach-omap2/Kconfig | 1 -
drivers/dma/Kconfig | 1 -
drivers/dma/edma.c | 1560 ++++++++++++++++++++++++---
include/linux/platform_data/edma.h | 101 --
13 files changed, 1516 insertions(+), 2299 deletions(-)
delete mode 100644 arch/arm/common/edma.c
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:30 +0200 |
| Subject | [PATCH v2 09/23] ARM: davinci: Use platform_device_register_full() to create pdev for eDMA |
| Message-ID | <q7vCO-1rQ-33@gated-at.bofh.it> |
| In reply to | #1222789 |
Convert the eDMA platform device creation to use
struct platform_device_info XXXXXX __initconst and
platform_device_register_full()
This will allow us to cleanly specify the dma_mask for the devices in an
upcoming patch.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/mach-davinci/devices-da8xx.c | 38 ++++++++++++++++++-----------------
arch/arm/mach-davinci/dm355.c | 20 +++++++++++-------
arch/arm/mach-davinci/dm644x.c | 20 +++++++++++-------
arch/arm/mach-davinci/dm646x.c | 18 ++++++++++-------
4 files changed, 57 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 9ae049ae816a..9f7d266faa0c 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -213,48 +213,50 @@ static struct resource da850_edma1_resources[] = {
},
};
-static struct platform_device da8xx_edma0_device = {
+static const struct platform_device_info da8xx_edma0_device __initconst = {
.name = "edma",
.id = 0,
- .dev = {
- .platform_data = &da8xx_edma0_pdata,
- },
- .num_resources = ARRAY_SIZE(da8xx_edma0_resources),
- .resource = da8xx_edma0_resources,
+ .res = da8xx_edma0_resources,
+ .num_res = ARRAY_SIZE(da8xx_edma0_resources),
+ .data = &da8xx_edma0_pdata,
+ .size_data = sizeof(da8xx_edma0_pdata),
};
-static struct platform_device da850_edma1_device = {
+static const struct platform_device_info da850_edma1_device __initconst = {
.name = "edma",
.id = 1,
- .dev = {
- .platform_data = &da850_edma1_pdata,
- },
- .num_resources = ARRAY_SIZE(da850_edma1_resources),
- .resource = da850_edma1_resources,
+ .res = da850_edma1_resources,
+ .num_res = ARRAY_SIZE(da850_edma1_resources),
+ .data = &da850_edma1_pdata,
+ .size_data = sizeof(da850_edma1_pdata),
};
int __init da830_register_edma(struct edma_rsv_info *rsv)
{
+ struct platform_device *edma_pdev;
+
da8xx_edma0_pdata.rsv = rsv;
- return platform_device_register(&da8xx_edma0_device);
+ edma_pdev = platform_device_register_full(&da8xx_edma0_device);
+ return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
}
int __init da850_register_edma(struct edma_rsv_info *rsv[2])
{
- int ret;
+ struct platform_device *edma_pdev;
if (rsv) {
da8xx_edma0_pdata.rsv = rsv[0];
da850_edma1_pdata.rsv = rsv[1];
}
- ret = platform_device_register(&da8xx_edma0_device);
- if (ret) {
+ edma_pdev = platform_device_register_full(&da8xx_edma0_device);
+ if (IS_ERR(edma_pdev)) {
pr_warn("%s: Failed to register eDMA0\n", __func__);
- return ret;
+ return PTR_ERR(edma_pdev);
}
- return platform_device_register(&da850_edma1_device);
+ edma_pdev = platform_device_register_full(&da850_edma1_device);
+ return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
}
static struct resource da8xx_i2c_resources0[] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a50bb9c66952..5f10c6695e31 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -613,12 +613,13 @@ static struct resource edma_resources[] = {
/* not using (or muxing) TC*_ERR */
};
-static struct platform_device dm355_edma_device = {
- .name = "edma",
- .id = 0,
- .dev.platform_data = &dm355_edma_pdata,
- .num_resources = ARRAY_SIZE(edma_resources),
- .resource = edma_resources,
+static const struct platform_device_info dm355_edma_device __initconst = {
+ .name = "edma",
+ .id = 0,
+ .res = edma_resources,
+ .num_res = ARRAY_SIZE(edma_resources),
+ .data = &dm355_edma_pdata,
+ .size_data = sizeof(dm355_edma_pdata),
};
static struct resource dm355_asp1_resources[] = {
@@ -1057,13 +1058,18 @@ int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
static int __init dm355_init_devices(void)
{
+ struct platform_device *edma_pdev;
int ret = 0;
if (!cpu_is_davinci_dm355())
return 0;
davinci_cfg_reg(DM355_INT_EDMA_CC);
- platform_device_register(&dm355_edma_device);
+ edma_pdev = platform_device_register_full(&dm355_edma_device);
+ if (IS_ERR(edma_pdev)) {
+ pr_warn("%s: Failed to register eDMA\n", __func__);
+ return PTR_ERR(edma_pdev);
+ }
ret = davinci_init_wdt();
if (ret)
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index d759ca8e58e8..aa3453b40d5f 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -542,12 +542,13 @@ static struct resource edma_resources[] = {
/* not using TC*_ERR */
};
-static struct platform_device dm644x_edma_device = {
- .name = "edma",
- .id = 0,
- .dev.platform_data = &dm644x_edma_pdata,
- .num_resources = ARRAY_SIZE(edma_resources),
- .resource = edma_resources,
+static const struct platform_device_info dm644x_edma_device __initconst = {
+ .name = "edma",
+ .id = 0,
+ .res = edma_resources,
+ .num_res = ARRAY_SIZE(edma_resources),
+ .data = &dm644x_edma_pdata,
+ .size_data = sizeof(dm644x_edma_pdata),
};
/* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
@@ -945,12 +946,17 @@ int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
static int __init dm644x_init_devices(void)
{
+ struct platform_device *edma_pdev;
int ret = 0;
if (!cpu_is_davinci_dm644x())
return 0;
- platform_device_register(&dm644x_edma_device);
+ edma_pdev = platform_device_register_full(&dm644x_edma_device);
+ if (IS_ERR(edma_pdev)) {
+ pr_warn("%s: Failed to register eDMA\n", __func__);
+ return PTR_ERR(edma_pdev);
+ }
platform_device_register(&dm644x_mdio_device);
platform_device_register(&dm644x_emac_device);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 219ebc8f674a..79c1d8917dd3 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -589,12 +589,13 @@ static struct resource edma_resources[] = {
/* not using TC*_ERR */
};
-static struct platform_device dm646x_edma_device = {
- .name = "edma",
- .id = 0,
- .dev.platform_data = &dm646x_edma_pdata,
- .num_resources = ARRAY_SIZE(edma_resources),
- .resource = edma_resources,
+static const struct platform_device_info dm646x_edma_device __initconst = {
+ .name = "edma",
+ .id = 0,
+ .res = edma_resources,
+ .num_res = ARRAY_SIZE(edma_resources),
+ .data = &dm646x_edma_pdata,
+ .size_data = sizeof(dm646x_edma_pdata),
};
static struct resource dm646x_mcasp0_resources[] = {
@@ -931,9 +932,12 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
int __init dm646x_init_edma(struct edma_rsv_info *rsv)
{
+ struct platform_device *edma_pdev;
+
dm646x_edma_pdata.rsv = rsv;
- return platform_device_register(&dm646x_edma_device);
+ edma_pdev = platform_device_register_full(&dm646x_edma_device);
+ return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
}
void __init dm646x_init(void)
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:30 +0200 |
| Subject | [PATCH v2 18/23] dmaengine: edma: Print warning when linking slots from different eDMA |
| Message-ID | <q7vCP-1rQ-43@gated-at.bofh.it> |
| In reply to | #1222789 |
Warning message in case of linking between paRAM slots in different eDMA
controllers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index fcd612fbf00d..5dd0cd478523 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -598,6 +598,9 @@ static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
*/
static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
{
+ if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
+ dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
+
from = EDMA_CHAN_SLOT(from);
to = EDMA_CHAN_SLOT(to);
if (from >= ecc->num_slots || to >= ecc->num_slots)
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:40 +0200 |
| Subject | [PATCH v2 07/23] ARM/dmaengine: edma: Public API to use private struct pointer |
| Message-ID | <q7vMu-1Di-11@gated-at.bofh.it> |
| In reply to | #1222789 |
Instead of relying on indexes pointing to edma private date in the global
pointer array, pass the private data pointer via the public API.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 305 ++++++++++++++++++-------------------
drivers/dma/edma.c | 79 +++++-----
include/linux/platform_data/edma.h | 38 +++--
3 files changed, 214 insertions(+), 208 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 5fd8293a48aa..15b68ce98ec7 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -130,7 +130,7 @@ struct edma {
struct edma_soc_info *info;
int id;
-
+ bool unused_chan_list_done;
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
@@ -264,7 +264,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p)
}
/*****************************************************************************/
-static struct edma *edma_cc[EDMA_MAX_CC];
static int arch_num_cc;
/* dummy param set used to (re)initialize parameter RAM slots */
@@ -490,14 +489,18 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
- int i, count, ctlr;
+ struct edma *cc = data;
+ int i, count;
struct of_phandle_args dma_spec;
if (dev->of_node) {
+ struct platform_device *dma_pdev;
+
count = of_property_count_strings(dev->of_node, "dma-names");
if (count < 0)
return 0;
for (i = 0; i < count; i++) {
+
if (of_parse_phandle_with_args(dev->of_node, "dmas",
"#dma-cells", i,
&dma_spec))
@@ -508,8 +511,12 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
continue;
}
+ dma_pdev = of_find_device_by_node(dma_spec.np);
+ if (&dma_pdev->dev != cc->dev)
+ continue;
+
clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
- edma_cc[0]->edma_unused);
+ cc->edma_unused);
of_node_put(dma_spec.np);
}
return 0;
@@ -517,11 +524,11 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
/* For non-OF case */
for (i = 0; i < pdev->num_resources; i++) {
- if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
- (int)pdev->resource[i].start >= 0) {
- ctlr = EDMA_CTLR(pdev->resource[i].start);
+ struct resource *res = &pdev->resource[i];
+
+ if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) {
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
- edma_cc[ctlr]->edma_unused);
+ cc->edma_unused);
}
}
@@ -530,8 +537,6 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
/*-----------------------------------------------------------------------*/
-static bool unused_chan_list_done;
-
/* Resource alloc/free: dma channels, parameter RAM slots */
/**
@@ -564,77 +569,73 @@ static bool unused_chan_list_done;
*
* Returns the number of the channel, else negative errno.
*/
-int edma_alloc_channel(int channel,
+int edma_alloc_channel(struct edma *cc, int channel,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data,
enum dma_event_q eventq_no)
{
- unsigned i, done = 0, ctlr = 0;
+ unsigned done = 0;
int ret = 0;
- if (!unused_chan_list_done) {
+ if (!cc->unused_chan_list_done) {
/*
* Scan all the platform devices to find out the EDMA channels
* used and clear them in the unused list, making the rest
* available for ARM usage.
*/
- ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
- prepare_unused_channel_list);
+ ret = bus_for_each_dev(&platform_bus_type, NULL, cc,
+ prepare_unused_channel_list);
if (ret < 0)
return ret;
- unused_chan_list_done = true;
+ cc->unused_chan_list_done = true;
}
if (channel >= 0) {
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n",
+ __func__, cc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
channel = EDMA_CHAN_SLOT(channel);
}
if (channel < 0) {
- for (i = 0; i < arch_num_cc; i++) {
- channel = 0;
- for (;;) {
- channel = find_next_bit(edma_cc[i]->edma_unused,
- edma_cc[i]->num_channels,
- channel);
- if (channel == edma_cc[i]->num_channels)
- break;
- if (!test_and_set_bit(channel,
- edma_cc[i]->edma_inuse)) {
- done = 1;
- ctlr = i;
- break;
- }
- channel++;
- }
- if (done)
+ channel = 0;
+ for (;;) {
+ channel = find_next_bit(cc->edma_unused,
+ cc->num_channels, channel);
+ if (channel == cc->num_channels)
+ break;
+ if (!test_and_set_bit(channel, cc->edma_inuse)) {
+ done = 1;
break;
+ }
+ channel++;
}
if (!done)
return -ENOMEM;
- } else if (channel >= edma_cc[ctlr]->num_channels) {
+ } else if (channel >= cc->num_channels) {
return -EINVAL;
- } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
+ } else if (test_and_set_bit(channel, cc->edma_inuse)) {
return -EBUSY;
}
/* ensure access through shadow region 0 */
- edma_or_array2(edma_cc[ctlr], EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+ edma_or_array2(cc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
/* ensure no events are pending */
- edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ edma_stop(cc, EDMA_CTLR_CHAN(cc->id, channel));
+ memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset,
PARM_SIZE);
if (callback)
- setup_dma_interrupt(edma_cc[ctlr],
- EDMA_CTLR_CHAN(ctlr, channel), callback,
- data);
+ setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, channel),
+ callback, data);
- map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
+ map_dmach_queue(cc, channel, eventq_no);
- return EDMA_CTLR_CHAN(ctlr, channel);
+ return EDMA_CTLR_CHAN(cc->id, channel);
}
EXPORT_SYMBOL(edma_alloc_channel);
@@ -650,22 +651,25 @@ EXPORT_SYMBOL(edma_alloc_channel);
* will not be reactivated by linking, chaining, or software calls to
* edma_start().
*/
-void edma_free_channel(unsigned channel)
+void edma_free_channel(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel >= edma_cc[ctlr]->num_channels)
+ if (channel >= cc->num_channels)
return;
- setup_dma_interrupt(edma_cc[ctlr], channel, NULL, NULL);
+ setup_dma_interrupt(cc, channel, NULL, NULL);
/* REVISIT should probably take out of shadow region 0 */
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ memcpy_toio(cc->base + PARM_OFFSET(channel), &dummy_paramset,
PARM_SIZE);
- clear_bit(channel, edma_cc[ctlr]->edma_inuse);
+ clear_bit(channel, cc->edma_inuse);
}
EXPORT_SYMBOL(edma_free_channel);
@@ -683,35 +687,29 @@ EXPORT_SYMBOL(edma_free_channel);
*
* Returns the number of the slot, else negative errno.
*/
-int edma_alloc_slot(unsigned ctlr, int slot)
+int edma_alloc_slot(struct edma *cc, int slot)
{
- if (!edma_cc[ctlr])
- return -EINVAL;
-
- if (slot >= 0)
+ if (slot > 0)
slot = EDMA_CHAN_SLOT(slot);
-
if (slot < 0) {
- slot = edma_cc[ctlr]->num_channels;
+ slot = cc->num_channels;
for (;;) {
- slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
- edma_cc[ctlr]->num_slots, slot);
- if (slot == edma_cc[ctlr]->num_slots)
+ slot = find_next_zero_bit(cc->edma_inuse, cc->num_slots,
+ slot);
+ if (slot == cc->num_slots)
return -ENOMEM;
- if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
+ if (!test_and_set_bit(slot, cc->edma_inuse))
break;
}
- } else if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots) {
+ } else if (slot < cc->num_channels || slot >= cc->num_slots) {
return -EINVAL;
- } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
+ } else if (test_and_set_bit(slot, cc->edma_inuse)) {
return -EBUSY;
}
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
- PARM_SIZE);
+ memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE);
- return EDMA_CTLR_CHAN(ctlr, slot);
+ return slot;
}
EXPORT_SYMBOL(edma_alloc_slot);
@@ -723,20 +721,15 @@ EXPORT_SYMBOL(edma_alloc_slot);
* Callers are responsible for ensuring the slot is inactive, and will
* not be activated.
*/
-void edma_free_slot(unsigned slot)
+void edma_free_slot(struct edma *cc, unsigned slot)
{
- unsigned ctlr;
- ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots)
+ if (slot < cc->num_channels || slot >= cc->num_slots)
return;
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
- PARM_SIZE);
- clear_bit(slot, edma_cc[ctlr]->edma_inuse);
+ memcpy_toio(cc->base + PARM_OFFSET(slot), &dummy_paramset, PARM_SIZE);
+ clear_bit(slot, cc->edma_inuse);
}
EXPORT_SYMBOL(edma_free_slot);
@@ -751,16 +744,15 @@ EXPORT_SYMBOL(edma_free_slot);
*
* Returns the position of the current active slot
*/
-dma_addr_t edma_get_position(unsigned slot, bool dst)
+dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst)
{
- u32 offs, ctlr = EDMA_CTLR(slot);
+ u32 offs;
slot = EDMA_CHAN_SLOT(slot);
-
offs = PARM_OFFSET(slot);
offs += dst ? PARM_DST : PARM_SRC;
- return edma_read(edma_cc[ctlr], offs);
+ return edma_read(cc, offs);
}
/**
@@ -770,21 +762,15 @@ dma_addr_t edma_get_position(unsigned slot, bool dst)
*
* The originating slot should not be part of any active DMA transfer.
*/
-void edma_link(unsigned from, unsigned to)
+void edma_link(struct edma *cc, unsigned from, unsigned to)
{
- unsigned ctlr_from, ctlr_to;
-
- ctlr_from = EDMA_CTLR(from);
from = EDMA_CHAN_SLOT(from);
- ctlr_to = EDMA_CTLR(to);
to = EDMA_CHAN_SLOT(to);
-
- if (from >= edma_cc[ctlr_from]->num_slots)
+ if (from >= cc->num_slots || to >= cc->num_slots)
return;
- if (to >= edma_cc[ctlr_to]->num_slots)
- return;
- edma_parm_modify(edma_cc[ctlr_from], PARM_LINK_BCNTRLD, from, 0xffff0000,
- PARM_OFFSET(to));
+
+ edma_parm_modify(cc, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ PARM_OFFSET(to));
}
EXPORT_SYMBOL(edma_link);
@@ -802,16 +788,13 @@ EXPORT_SYMBOL(edma_link);
* calls to set up those parameters in small pieces, and provides
* complete control over all transfer options.
*/
-void edma_write_slot(unsigned slot, const struct edmacc_param *param)
+void edma_write_slot(struct edma *cc, unsigned slot,
+ const struct edmacc_param *param)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
-
- if (slot >= edma_cc[ctlr]->num_slots)
+ if (slot >= cc->num_slots)
return;
- memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), param, PARM_SIZE);
+ memcpy_toio(cc->base + PARM_OFFSET(slot), param, PARM_SIZE);
}
EXPORT_SYMBOL(edma_write_slot);
@@ -823,17 +806,12 @@ EXPORT_SYMBOL(edma_write_slot);
* Use this to read data from a parameter RAM slot, perhaps to
* save them as a template for later reuse.
*/
-void edma_read_slot(unsigned slot, struct edmacc_param *param)
+void edma_read_slot(struct edma *cc, unsigned slot, struct edmacc_param *param)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
slot = EDMA_CHAN_SLOT(slot);
-
- if (slot >= edma_cc[ctlr]->num_slots)
+ if (slot >= cc->num_slots)
return;
- memcpy_fromio(param, edma_cc[ctlr]->base + PARM_OFFSET(slot),
- PARM_SIZE);
+ memcpy_fromio(param, cc->base + PARM_OFFSET(slot), PARM_SIZE);
}
EXPORT_SYMBOL(edma_read_slot);
@@ -848,18 +826,19 @@ EXPORT_SYMBOL(edma_read_slot);
* This temporarily disables EDMA hardware events on the specified channel,
* preventing them from triggering new transfers on its behalf
*/
-void edma_pause(unsigned channel)
+void edma_pause(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
+ if (channel < cc->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(edma_cc[ctlr], SH_EECR, channel >> 5,
- mask);
+ edma_shadow0_write_array(cc, SH_EECR, channel >> 5, mask);
}
}
EXPORT_SYMBOL(edma_pause);
@@ -870,36 +849,39 @@ EXPORT_SYMBOL(edma_pause);
*
* This re-enables EDMA hardware events on the specified channel.
*/
-void edma_resume(unsigned channel)
+void edma_resume(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
+ if (channel < cc->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(edma_cc[ctlr], SH_EESR, channel >> 5,
- mask);
+ edma_shadow0_write_array(cc, SH_EESR, channel >> 5, mask);
}
}
EXPORT_SYMBOL(edma_resume);
-int edma_trigger_channel(unsigned channel)
+int edma_trigger_channel(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
unsigned int mask;
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
channel = EDMA_CHAN_SLOT(channel);
mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(edma_cc[ctlr], SH_ESR, (channel >> 5), mask);
+ edma_shadow0_write_array(cc, SH_ESR, (channel >> 5), mask);
pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
- edma_shadow0_read_array(edma_cc[ctlr], SH_ESR,
- (channel >> 5)));
+ edma_shadow0_read_array(cc, SH_ESR, (channel >> 5)));
return 0;
}
EXPORT_SYMBOL(edma_trigger_channel);
@@ -915,15 +897,16 @@ EXPORT_SYMBOL(edma_trigger_channel);
*
* Returns zero on success, else negative errno.
*/
-int edma_start(unsigned channel)
+int edma_start(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return -EINVAL;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
- struct edma *cc = edma_cc[ctlr];
+ if (channel < cc->num_channels) {
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
@@ -962,15 +945,16 @@ EXPORT_SYMBOL(edma_start);
* may not be resumed, and the channel's Parameter RAM should be
* reinitialized before being reused.
*/
-void edma_stop(unsigned channel)
+void edma_stop(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
- struct edma *cc = edma_cc[ctlr];
+ if (channel < cc->num_channels) {
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
@@ -1005,15 +989,16 @@ EXPORT_SYMBOL(edma_stop);
*
*****************************************************************************/
-void edma_clean_channel(unsigned channel)
+void edma_clean_channel(struct edma *cc, unsigned channel)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel < edma_cc[ctlr]->num_channels) {
- struct edma *cc = edma_cc[ctlr];
+ if (channel < cc->num_channels) {
int j = (channel >> 5);
unsigned int mask = BIT(channel & 0x1f);
@@ -1037,26 +1022,35 @@ EXPORT_SYMBOL(edma_clean_channel);
*
* Can be used to move a channel to a selected event queue.
*/
-void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
+void edma_assign_channel_eventq(struct edma *cc, unsigned channel,
+ enum dma_event_q eventq_no)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
+ if (cc->id != EDMA_CTLR(channel)) {
+ dev_err(cc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
+ cc->id, EDMA_CTLR(channel));
+ return;
+ }
channel = EDMA_CHAN_SLOT(channel);
- if (channel >= edma_cc[ctlr]->num_channels)
+ if (channel >= cc->num_channels)
return;
/* default to low priority queue */
if (eventq_no == EVENTQ_DEFAULT)
- eventq_no = edma_cc[ctlr]->default_queue;
- if (eventq_no >= edma_cc[ctlr]->num_tc)
+ eventq_no = cc->default_queue;
+ if (eventq_no >= cc->num_tc)
return;
- map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
+ map_dmach_queue(cc, channel, eventq_no);
}
EXPORT_SYMBOL(edma_assign_channel_eventq);
+struct edma *edma_get_data(struct device *edma_dev)
+{
+ return dev_get_drvdata(edma_dev);
+}
+
+
static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
struct edma *edma_cc, int cc_id)
{
@@ -1278,11 +1272,10 @@ static int edma_probe(struct platform_device *pdev)
}
}
- edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
- if (!edma_cc[dev_id])
+ cc = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
+ if (!cc)
return -ENOMEM;
- cc = edma_cc[dev_id];
cc->dev = dev;
cc->id = dev_id;
dev_set_drvdata(dev, cc);
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index fcb4680efed7..53d48b2a700d 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -119,6 +119,7 @@ struct edma_chan {
};
struct edma_cc {
+ struct edma *cc;
int ctlr;
struct dma_device dma_slave;
struct edma_chan slave_chans[EDMA_CHANS];
@@ -150,6 +151,7 @@ static void edma_desc_free(struct virt_dma_desc *vdesc)
/* Dispatch a queued descriptor to the controller (caller holds lock) */
static void edma_execute(struct edma_chan *echan)
{
+ struct edma *cc = echan->ecc->cc;
struct virt_dma_desc *vdesc;
struct edma_desc *edesc;
struct device *dev = echan->vchan.chan.device->dev;
@@ -174,7 +176,7 @@ static void edma_execute(struct edma_chan *echan)
/* Write descriptor PaRAM set(s) */
for (i = 0; i < nslots; i++) {
j = i + edesc->processed;
- edma_write_slot(echan->slot[i], &edesc->pset[j].param);
+ edma_write_slot(cc, echan->slot[i], &edesc->pset[j].param);
edesc->sg_len += edesc->pset[j].len;
dev_vdbg(echan->vchan.chan.device->dev,
"\n pset[%d]:\n"
@@ -199,7 +201,7 @@ static void edma_execute(struct edma_chan *echan)
edesc->pset[j].param.link_bcntrld);
/* Link to the previous slot if not the last set */
if (i != (nslots - 1))
- edma_link(echan->slot[i], echan->slot[i+1]);
+ edma_link(cc, echan->slot[i], echan->slot[i+1]);
}
edesc->processed += nslots;
@@ -211,9 +213,9 @@ static void edma_execute(struct edma_chan *echan)
*/
if (edesc->processed == edesc->pset_nr) {
if (edesc->cyclic)
- edma_link(echan->slot[nslots-1], echan->slot[1]);
+ edma_link(cc, echan->slot[nslots-1], echan->slot[1]);
else
- edma_link(echan->slot[nslots-1],
+ edma_link(cc, echan->slot[nslots-1],
echan->ecc->dummy_slot);
}
@@ -224,19 +226,19 @@ static void edma_execute(struct edma_chan *echan)
* transfers of MAX_NR_SG
*/
dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
- edma_clean_channel(echan->ch_num);
- edma_stop(echan->ch_num);
- edma_start(echan->ch_num);
- edma_trigger_channel(echan->ch_num);
+ edma_clean_channel(cc, echan->ch_num);
+ edma_stop(cc, echan->ch_num);
+ edma_start(cc, echan->ch_num);
+ edma_trigger_channel(cc, echan->ch_num);
echan->missed = 0;
} else if (edesc->processed <= MAX_NR_SG) {
dev_dbg(dev, "first transfer starting on channel %d\n",
echan->ch_num);
- edma_start(echan->ch_num);
+ edma_start(cc, echan->ch_num);
} else {
dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
echan->ch_num, edesc->processed);
- edma_resume(echan->ch_num);
+ edma_resume(cc, echan->ch_num);
}
}
@@ -254,10 +256,11 @@ static int edma_terminate_all(struct dma_chan *chan)
* echan->edesc is NULL and exit.)
*/
if (echan->edesc) {
- edma_stop(echan->ch_num);
+ edma_stop(echan->ecc->cc, echan->ch_num);
/* Move the cyclic channel back to default queue */
if (echan->edesc->cyclic)
- edma_assign_channel_eventq(echan->ch_num,
+ edma_assign_channel_eventq(echan->ecc->cc,
+ echan->ch_num,
EVENTQ_DEFAULT);
/*
* free the running request descriptor
@@ -295,7 +298,7 @@ static int edma_dma_pause(struct dma_chan *chan)
if (!echan->edesc)
return -EINVAL;
- edma_pause(echan->ch_num);
+ edma_pause(echan->ecc->cc, echan->ch_num);
return 0;
}
@@ -303,7 +306,7 @@ static int edma_dma_resume(struct dma_chan *chan)
{
struct edma_chan *echan = to_edma_chan(chan);
- edma_resume(echan->ch_num);
+ edma_resume(echan->ecc->cc, echan->ch_num);
return 0;
}
@@ -485,8 +488,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
for (i = 0; i < nslots; i++) {
if (echan->slot[i] < 0) {
echan->slot[i] =
- edma_alloc_slot(EDMA_CTLR(echan->ch_num),
- EDMA_SLOT_ANY);
+ edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY);
if (echan->slot[i] < 0) {
kfree(edesc);
dev_err(dev, "%s: Failed to allocate slot\n",
@@ -641,8 +643,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
/* Allocate a PaRAM slot, if needed */
if (echan->slot[i] < 0) {
echan->slot[i] =
- edma_alloc_slot(EDMA_CTLR(echan->ch_num),
- EDMA_SLOT_ANY);
+ edma_alloc_slot(echan->ecc->cc, EDMA_SLOT_ANY);
if (echan->slot[i] < 0) {
kfree(edesc);
dev_err(dev, "%s: Failed to allocate slot\n",
@@ -703,7 +704,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
}
/* Place the cyclic channel to highest priority queue */
- edma_assign_channel_eventq(echan->ch_num, EVENTQ_0);
+ edma_assign_channel_eventq(echan->ecc->cc, echan->ch_num, EVENTQ_0);
return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}
@@ -711,6 +712,7 @@ static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
{
struct edma_chan *echan = data;
+ struct edma *cc = echan->ecc->cc;
struct device *dev = echan->vchan.chan.device->dev;
struct edma_desc *edesc;
struct edmacc_param p;
@@ -727,13 +729,13 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
} else if (edesc->processed == edesc->pset_nr) {
dev_dbg(dev, "Transfer complete, stopping channel %d\n", ch_num);
edesc->residue = 0;
- edma_stop(echan->ch_num);
+ edma_stop(cc, echan->ch_num);
vchan_cookie_complete(&edesc->vdesc);
echan->edesc = NULL;
} else {
dev_dbg(dev, "Intermediate transfer complete on channel %d\n", ch_num);
- edma_pause(echan->ch_num);
+ edma_pause(cc, echan->ch_num);
/* Update statistics for tx_status */
edesc->residue -= edesc->sg_len;
@@ -744,7 +746,7 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
}
break;
case EDMA_DMA_CC_ERROR:
- edma_read_slot(EDMA_CHAN_SLOT(echan->slot[0]), &p);
+ edma_read_slot(cc, echan->slot[0], &p);
/*
* Issue later based on missed flag which will be sure
@@ -767,10 +769,10 @@ static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
* missed, so its safe to issue it here.
*/
dev_dbg(dev, "Error occurred but slot is non-null, TRIGGERING\n");
- edma_clean_channel(echan->ch_num);
- edma_stop(echan->ch_num);
- edma_start(echan->ch_num);
- edma_trigger_channel(echan->ch_num);
+ edma_clean_channel(cc, echan->ch_num);
+ edma_stop(cc, echan->ch_num);
+ edma_start(cc, echan->ch_num);
+ edma_trigger_channel(cc, echan->ch_num);
}
break;
default:
@@ -789,8 +791,8 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
int a_ch_num;
LIST_HEAD(descs);
- a_ch_num = edma_alloc_channel(echan->ch_num, edma_callback,
- echan, EVENTQ_DEFAULT);
+ a_ch_num = edma_alloc_channel(echan->ecc->cc, echan->ch_num,
+ edma_callback, echan, EVENTQ_DEFAULT);
if (a_ch_num < 0) {
ret = -ENODEV;
@@ -814,7 +816,7 @@ static int edma_alloc_chan_resources(struct dma_chan *chan)
return 0;
err_wrong_chan:
- edma_free_channel(a_ch_num);
+ edma_free_channel(echan->ecc->cc, a_ch_num);
err_no_chan:
return ret;
}
@@ -827,21 +829,21 @@ static void edma_free_chan_resources(struct dma_chan *chan)
int i;
/* Terminate transfers */
- edma_stop(echan->ch_num);
+ edma_stop(echan->ecc->cc, echan->ch_num);
vchan_free_chan_resources(&echan->vchan);
/* Free EDMA PaRAM slots */
for (i = 1; i < EDMA_MAX_SLOTS; i++) {
if (echan->slot[i] >= 0) {
- edma_free_slot(echan->slot[i]);
+ edma_free_slot(echan->ecc->cc, echan->slot[i]);
echan->slot[i] = -1;
}
}
/* Free EDMA channel */
if (echan->alloced) {
- edma_free_channel(echan->ch_num);
+ edma_free_channel(echan->ecc->cc, echan->ch_num);
echan->alloced = false;
}
@@ -871,7 +873,8 @@ static u32 edma_residue(struct edma_desc *edesc)
* We always read the dst/src position from the first RamPar
* pset. That's the one which is active now.
*/
- pos = edma_get_position(edesc->echan->slot[0], dst);
+ pos = edma_get_position(edesc->echan->ecc->cc, edesc->echan->slot[0],
+ dst);
/*
* Cyclic is simple. Just subtract pset[0].addr from pos.
@@ -1008,8 +1011,12 @@ static int edma_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ ecc->cc = edma_get_data(pdev->dev.parent);
+ if (!ecc->cc)
+ return -ENODEV;
+
ecc->ctlr = pdev->id;
- ecc->dummy_slot = edma_alloc_slot(ecc->ctlr, EDMA_SLOT_ANY);
+ ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY);
if (ecc->dummy_slot < 0) {
dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
return ecc->dummy_slot;
@@ -1042,7 +1049,7 @@ static int edma_probe(struct platform_device *pdev)
return 0;
err_reg1:
- edma_free_slot(ecc->dummy_slot);
+ edma_free_slot(ecc->cc, ecc->dummy_slot);
return ret;
}
@@ -1055,7 +1062,7 @@ static int edma_remove(struct platform_device *pdev)
if (parent_node)
of_dma_controller_free(parent_node);
dma_async_device_unregister(&ecc->dma_slave);
- edma_free_slot(ecc->dummy_slot);
+ edma_free_slot(ecc->cc, ecc->dummy_slot);
return 0;
}
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index c1862423b356..466021c03169 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -92,32 +92,40 @@ enum dma_event_q {
#define EDMA_MAX_CC 2
+struct edma;
+
+struct edma *edma_get_data(struct device *edma_dev);
+
/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(int channel,
+int edma_alloc_channel(struct edma *cc, int channel,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data, enum dma_event_q);
-void edma_free_channel(unsigned channel);
+void edma_free_channel(struct edma *cc, unsigned channel);
/* alloc/free parameter RAM slots */
-int edma_alloc_slot(unsigned ctlr, int slot);
-void edma_free_slot(unsigned slot);
+int edma_alloc_slot(struct edma *cc, int slot);
+void edma_free_slot(struct edma *cc, unsigned slot);
/* calls that operate on part of a parameter RAM slot */
-dma_addr_t edma_get_position(unsigned slot, bool dst);
-void edma_link(unsigned from, unsigned to);
+dma_addr_t edma_get_position(struct edma *cc, unsigned slot, bool dst);
+void edma_link(struct edma *cc, unsigned from, unsigned to);
/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-void edma_read_slot(unsigned slot, struct edmacc_param *params);
+void edma_write_slot(struct edma *cc, unsigned slot,
+ const struct edmacc_param *params);
+void edma_read_slot(struct edma *cc, unsigned slot,
+ struct edmacc_param *params);
/* channel control operations */
-int edma_start(unsigned channel);
-void edma_stop(unsigned channel);
-void edma_clean_channel(unsigned channel);
-void edma_pause(unsigned channel);
-void edma_resume(unsigned channel);
+int edma_start(struct edma *cc, unsigned channel);
+void edma_stop(struct edma *cc, unsigned channel);
+void edma_clean_channel(struct edma *cc, unsigned channel);
+void edma_pause(struct edma *cc, unsigned channel);
+void edma_resume(struct edma *cc, unsigned channel);
+int edma_trigger_channel(struct edma *cc, unsigned channel);
-void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no);
+void edma_assign_channel_eventq(struct edma *cc, unsigned channel,
+ enum dma_event_q eventq_no);
struct edma_rsv_info {
@@ -141,6 +149,4 @@ struct edma_soc_info {
const s16 (*xbar_chans)[2];
};
-int edma_trigger_channel(unsigned);
-
#endif
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:40 +0200 |
| Subject | [PATCH v2 19/23] dmaengine: edma: Consolidate the comments for functions |
| Message-ID | <q7vMu-1Di-13@gated-at.bofh.it> |
| In reply to | #1222789 |
Remove or rewrite the comments for the internal functions.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 86 +++++++-----------------------------------------------
1 file changed, 11 insertions(+), 75 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 5dd0cd478523..ffbf63a64313 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -486,19 +486,7 @@ static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch,
}
/*
- * paRAM management functions
- */
-
-/**
- * edma_write_slot - write parameter RAM data for slot
- * @ecc: pointer to edma_cc struct
- * @slot: number of parameter RAM slot being modified
- * @param: data to be written into parameter RAM slot
- *
- * Use this to assign all parameters of a transfer at once. This
- * allows more efficient setup of transfers than issuing multiple
- * calls to set up those parameters in small pieces, and provides
- * complete control over all transfer options.
+ * paRAM slot management functions
*/
static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
const struct edmacc_param *param)
@@ -509,15 +497,6 @@ static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
}
-/**
- * edma_read_slot - read parameter RAM data from slot
- * @ecc: pointer to edma_cc struct
- * @slot: number of parameter RAM slot being copied
- * @param: where to store copy of parameter RAM data
- *
- * Use this to read data from a parameter RAM slot, perhaps to
- * save them as a template for later reuse.
- */
static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
struct edmacc_param *param)
{
@@ -568,15 +547,6 @@ static int edma_alloc_slot(struct edma_cc *ecc, int slot)
return EDMA_CTLR_CHAN(ecc->id, slot);
}
-/**
- * edma_free_slot - deallocate DMA parameter RAM
- * @ecc: pointer to edma_cc struct
- * @slot: parameter RAM slot returned from edma_alloc_slot()
- *
- * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
- * Callers are responsible for ensuring the slot is inactive, and will
- * not be activated.
- */
static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
{
@@ -686,10 +656,9 @@ static int edma_start(struct edma_cc *ecc, unsigned channel)
* @ecc: pointer to edma_cc struct
* @channel: channel being deactivated
*
- * When @lch is a channel, any active transfer is paused and
- * all pending hardware events are cleared. The current transfer
- * may not be resumed, and the channel's Parameter RAM should be
- * reinitialized before being reused.
+ * Any active transfer is paused and all pending hardware events are cleared.
+ * The current transfer may not be resumed, and the channel's Parameter RAM
+ * should be reinitialized before being reused.
*/
static void edma_stop(struct edma_cc *ecc, unsigned channel)
{
@@ -721,13 +690,9 @@ static void edma_stop(struct edma_cc *ecc, unsigned channel)
}
}
-/**
- * edma_pause - pause dma on a channel
- * @ecc: pointer to edma_cc struct
- * @channel: on which edma_start() has been called
- *
- * This temporarily disables EDMA hardware events on the specified channel,
- * preventing them from triggering new transfers on its behalf
+/*
+ * Temporarily disable EDMA hardware events on the specified channel,
+ * preventing them from triggering new transfers
*/
static void edma_pause(struct edma_cc *ecc, unsigned channel)
{
@@ -745,13 +710,7 @@ static void edma_pause(struct edma_cc *ecc, unsigned channel)
}
}
-/**
- * edma_resume - resumes dma on a paused channel
- * @ecc: pointer to edma_cc struct
- * @channel: on which edma_pause() has been called
- *
- * This re-enables EDMA hardware events on the specified channel.
- */
+/* Re-enable EDMA hardware events on the specified channel. */
static void edma_resume(struct edma_cc *ecc, unsigned channel)
{
if (ecc->id != EDMA_CTLR(channel)) {
@@ -787,19 +746,6 @@ static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel)
return 0;
}
-/******************************************************************************
- *
- * It cleans ParamEntry qand bring back EDMA to initial state if media has
- * been removed before EDMA has finished.It is usedful for removable media.
- * Arguments:
- * ch_no - channel no
- *
- * Return: zero on success, or corresponding error no on failure
- *
- * FIXME this should not be needed ... edma_stop() should suffice.
- *
- *****************************************************************************/
-
static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
{
if (ecc->id != EDMA_CTLR(channel)) {
@@ -956,14 +902,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
clear_bit(channel, ecc->edma_inuse);
}
-/*
- * edma_assign_channel_eventq - move given channel to desired eventq
- * Arguments:
- * channel - channel number
- * eventq_no - queue to move the channel
- *
- * Can be used to move a channel to a selected event queue.
- */
+/* Move channel to a specific event queue */
static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
enum dma_event_q eventq_no)
{
@@ -986,6 +925,7 @@ static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
edma_map_dmach_to_queue(ecc, channel, eventq_no);
}
+/* eDMA interrupt handler */
static irqreturn_t dma_irq_handler(int irq, void *data)
{
struct edma_cc *ecc = data;
@@ -1037,11 +977,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
return IRQ_HANDLED;
}
-/******************************************************************************
- *
- * DMA error interrupt handler
- *
- *****************************************************************************/
+/* eDMA error interrupt handler */
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
struct edma_cc *ecc = data;
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:40 +0200 |
| Subject | [PATCH v2 08/23] ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers |
| Message-ID | <q7vMu-1Di-15@gated-at.bofh.it> |
| In reply to | #1222789 |
Since the driver stack no longer depends on lookup with id number in a
global array of pointers, the limitation for the number of eDMAs are no
longer needed. We can handle as many eDMAs in legacy and DT boot as we have
memory for them to allocate the needed structures.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 22 +++++-----------------
drivers/dma/edma.c | 17 ++++++++---------
2 files changed, 13 insertions(+), 26 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 15b68ce98ec7..0f29997c62df 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1227,24 +1227,7 @@ static int edma_probe(struct platform_device *pdev)
.parent = &pdev->dev,
};
- /* When booting with DT the pdev->id is -1 */
- if (dev_id < 0)
- dev_id = arch_num_cc;
-
- if (dev_id >= EDMA_MAX_CC) {
- dev_err(dev,
- "eDMA3 with device id 0 and 1 is supported (id: %d)\n",
- dev_id);
- return -EINVAL;
- }
-
if (node) {
- /* Check if this is a second instance registered */
- if (arch_num_cc) {
- dev_err(dev, "only one EDMA instance is supported via DT\n");
- return -ENODEV;
- }
-
info = edma_setup_info_from_dt(dev, node);
if (IS_ERR(info)) {
dev_err(dev, "failed to get DT data\n");
@@ -1278,6 +1261,11 @@ static int edma_probe(struct platform_device *pdev)
cc->dev = dev;
cc->id = dev_id;
+ /* When booting with DT the pdev->id is -1 */
+ if (dev_id < 0) {
+ cc->id = 0;
+ dev_id = arch_num_cc;
+ }
dev_set_drvdata(dev, cc);
cc->base = devm_ioremap_resource(dev, mem);
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 53d48b2a700d..fc91ab9dd1bb 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -991,14 +991,12 @@ static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
INIT_LIST_HEAD(&dma->channels);
}
-static struct of_dma_filter_info edma_filter_info = {
- .filter_fn = edma_filter_fn,
-};
-
static int edma_probe(struct platform_device *pdev)
{
struct edma_cc *ecc;
struct device_node *parent_node = pdev->dev.parent->of_node;
+ struct platform_device *parent_pdev =
+ to_platform_device(pdev->dev.parent);
int ret;
ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
@@ -1015,7 +1013,10 @@ static int edma_probe(struct platform_device *pdev)
if (!ecc->cc)
return -ENODEV;
- ecc->ctlr = pdev->id;
+ ecc->ctlr = parent_pdev->id;
+ if (ecc->ctlr < 0)
+ ecc->ctlr = 0;
+
ecc->dummy_slot = edma_alloc_slot(ecc->cc, EDMA_SLOT_ANY);
if (ecc->dummy_slot < 0) {
dev_err(&pdev->dev, "Can't allocate PaRAM dummy slot\n");
@@ -1038,10 +1039,8 @@ static int edma_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ecc);
if (parent_node) {
- dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
- dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
- of_dma_controller_register(parent_node, of_dma_simple_xlate,
- &edma_filter_info);
+ of_dma_controller_register(parent_node, of_dma_xlate_by_chan_id,
+ &ecc->dma_slave);
}
dev_info(&pdev->dev, "TI EDMA DMA engine driver\n");
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:40 +0200 |
| Subject | [PATCH v2 10/23] ARM: davinci: Add set dma_mask to eDMA devices |
| Message-ID | <q7vMv-1Di-27@gated-at.bofh.it> |
| In reply to | #1222789 |
The upcoming change to merge the arch/arm/common/edma.c into
drivers/dma/edma.c will need this change when booting daVinci devices in
no DT mode.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/mach-davinci/devices-da8xx.c | 2 ++
arch/arm/mach-davinci/dm355.c | 1 +
arch/arm/mach-davinci/dm644x.c | 1 +
arch/arm/mach-davinci/dm646x.c | 1 +
4 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 9f7d266faa0c..28c90bc372bd 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -216,6 +216,7 @@ static struct resource da850_edma1_resources[] = {
static const struct platform_device_info da8xx_edma0_device __initconst = {
.name = "edma",
.id = 0,
+ .dma_mask = DMA_BIT_MASK(32),
.res = da8xx_edma0_resources,
.num_res = ARRAY_SIZE(da8xx_edma0_resources),
.data = &da8xx_edma0_pdata,
@@ -225,6 +226,7 @@ static const struct platform_device_info da8xx_edma0_device __initconst = {
static const struct platform_device_info da850_edma1_device __initconst = {
.name = "edma",
.id = 1,
+ .dma_mask = DMA_BIT_MASK(32),
.res = da850_edma1_resources,
.num_res = ARRAY_SIZE(da850_edma1_resources),
.data = &da850_edma1_pdata,
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 5f10c6695e31..609950b8c191 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -616,6 +616,7 @@ static struct resource edma_resources[] = {
static const struct platform_device_info dm355_edma_device __initconst = {
.name = "edma",
.id = 0,
+ .dma_mask = DMA_BIT_MASK(32),
.res = edma_resources,
.num_res = ARRAY_SIZE(edma_resources),
.data = &dm355_edma_pdata,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index aa3453b40d5f..d38f5049d56e 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -545,6 +545,7 @@ static struct resource edma_resources[] = {
static const struct platform_device_info dm644x_edma_device __initconst = {
.name = "edma",
.id = 0,
+ .dma_mask = DMA_BIT_MASK(32),
.res = edma_resources,
.num_res = ARRAY_SIZE(edma_resources),
.data = &dm644x_edma_pdata,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 79c1d8917dd3..70eb42725eec 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -592,6 +592,7 @@ static struct resource edma_resources[] = {
static const struct platform_device_info dm646x_edma_device __initconst = {
.name = "edma",
.id = 0,
+ .dma_mask = DMA_BIT_MASK(32),
.res = edma_resources,
.num_res = ARRAY_SIZE(edma_resources),
.data = &dm646x_edma_pdata,
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:40 +0200 |
| Subject | [PATCH v2 17/23] dmaengine: edma: Use the edma_write_slot instead open coded memcpy_toio |
| Message-ID | <q7vMv-1Di-29@gated-at.bofh.it> |
| In reply to | #1222789 |
edma_write_slot() is for writing an entire paRAM slot. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> --- drivers/dma/edma.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c index ed67206626e9..fcd612fbf00d 100644 --- a/drivers/dma/edma.c +++ b/drivers/dma/edma.c @@ -949,8 +949,7 @@ static void edma_free_channel(struct edma_cc *ecc, unsigned channel) edma_setup_interrupt(ecc, channel, NULL, NULL); /* REVISIT should probably take out of shadow region 0 */ - memcpy_toio(ecc->base + PARM_OFFSET(channel), &dummy_paramset, - PARM_SIZE); + edma_write_slot(ecc, channel, &dummy_paramset); clear_bit(channel, ecc->edma_inuse); } -- 2.5.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:40 +0200 |
| Subject | [PATCH v2 04/23] ARM: davinci/common: Convert edma driver to handle one eDMA instance per driver |
| Message-ID | <q7vMu-1Di-21@gated-at.bofh.it> |
| In reply to | #1222789 |
Currently we have one device created to handle all (maximum 2) eDMAs in the
system.
With this change all eDMA instance will have it's own device/driver.
This change is needed for further cleanups in the eDMA driver stack since
the one device/driver to handle all eDMAs in the system was not flexible
enough and prevents the upcoming work.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 357 +++++++++++++++-------------------
arch/arm/mach-davinci/devices-da8xx.c | 110 ++++-------
arch/arm/mach-davinci/dm355.c | 21 +-
arch/arm/mach-davinci/dm365.c | 25 +--
arch/arm/mach-davinci/dm644x.c | 21 +-
arch/arm/mach-davinci/dm646x.c | 27 ++-
6 files changed, 235 insertions(+), 326 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index e9c4cb16a47e..72fce68a959f 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -235,6 +235,7 @@ static inline void clear_bits(int offset, int len, unsigned long *p)
/* actual number of DMA channels and slots on this silicon */
struct edma {
+ struct device *dev;
/* how many dma resources of each type */
unsigned num_channels;
unsigned num_region;
@@ -246,6 +247,7 @@ struct edma {
const s8 *noevent;
struct edma_soc_info *info;
+ int id;
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
@@ -258,9 +260,6 @@ struct edma {
*/
DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
- unsigned irq_res_start;
- unsigned irq_res_end;
-
struct dma_interrupt_data {
void (*callback)(unsigned channel, unsigned short ch_status,
void *data);
@@ -349,17 +348,6 @@ setup_dma_interrupt(unsigned lch,
}
}
-static int irq2ctlr(int irq)
-{
- if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
- return 0;
- else if (irq >= edma_cc[1]->irq_res_start &&
- irq <= edma_cc[1]->irq_res_end)
- return 1;
-
- return -1;
-}
-
/******************************************************************************
*
* DMA interrupt handler
@@ -367,16 +355,17 @@ static int irq2ctlr(int irq)
*****************************************************************************/
static irqreturn_t dma_irq_handler(int irq, void *data)
{
+ struct edma *cc = data;
int ctlr;
u32 sh_ier;
u32 sh_ipr;
u32 bank;
- ctlr = irq2ctlr(irq);
+ ctlr = cc->id;
if (ctlr < 0)
return IRQ_NONE;
- dev_dbg(data, "dma_irq_handler\n");
+ dev_dbg(cc->dev, "dma_irq_handler\n");
sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
if (!sh_ipr) {
@@ -394,7 +383,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
u32 slot;
u32 channel;
- dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
+ dev_dbg(cc->dev, "IPR%d %08x\n", bank, sh_ipr);
slot = __ffs(sh_ipr);
sh_ipr &= ~(BIT(slot));
@@ -404,11 +393,11 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
/* Clear the corresponding IPR bits */
edma_shadow0_write_array(ctlr, SH_ICR, bank,
BIT(slot));
- if (edma_cc[ctlr]->intr_data[channel].callback)
- edma_cc[ctlr]->intr_data[channel].callback(
+ if (cc->intr_data[channel].callback)
+ cc->intr_data[channel].callback(
EDMA_CTLR_CHAN(ctlr, channel),
EDMA_DMA_COMPLETE,
- edma_cc[ctlr]->intr_data[channel].data);
+ cc->intr_data[channel].data);
}
} while (sh_ipr);
@@ -423,15 +412,16 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
*****************************************************************************/
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
+ struct edma *cc = data;
int i;
int ctlr;
unsigned int cnt = 0;
- ctlr = irq2ctlr(irq);
+ ctlr = cc->id;
if (ctlr < 0)
return IRQ_NONE;
- dev_dbg(data, "dma_ccerr_handler\n");
+ dev_dbg(cc->dev, "dma_ccerr_handler\n");
if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
(edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
@@ -446,8 +436,8 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
else if (edma_read_array(ctlr, EDMA_EMR, 1))
j = 1;
if (j >= 0) {
- dev_dbg(data, "EMR%d %08x\n", j,
- edma_read_array(ctlr, EDMA_EMR, j));
+ dev_dbg(cc->dev, "EMR%d %08x\n", j,
+ edma_read_array(ctlr, EDMA_EMR, j));
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
if (edma_read_array(ctlr, EDMA_EMR, j) &
@@ -458,19 +448,16 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
/* Clear any SER */
edma_shadow0_write_array(ctlr, SH_SECR,
j, BIT(i));
- if (edma_cc[ctlr]->intr_data[k].
- callback) {
- edma_cc[ctlr]->intr_data[k].
- callback(
- EDMA_CTLR_CHAN(ctlr, k),
- EDMA_DMA_CC_ERROR,
- edma_cc[ctlr]->intr_data
- [k].data);
+ if (cc->intr_data[k].callback) {
+ cc->intr_data[k].callback(
+ EDMA_CTLR_CHAN(ctlr, k),
+ EDMA_DMA_CC_ERROR,
+ cc->intr_data[k].data);
}
}
}
} else if (edma_read(ctlr, EDMA_QEMR)) {
- dev_dbg(data, "QEMR %02x\n",
+ dev_dbg(cc->dev, "QEMR %02x\n",
edma_read(ctlr, EDMA_QEMR));
for (i = 0; i < 8; i++) {
if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
@@ -483,7 +470,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
}
}
} else if (edma_read(ctlr, EDMA_CCERR)) {
- dev_dbg(data, "CCERR %08x\n",
+ dev_dbg(cc->dev, "CCERR %08x\n",
edma_read(ctlr, EDMA_CCERR));
/* FIXME: CCERR.BIT(16) ignored! much better
* to just write CCERRCLR with CCERR value...
@@ -1239,21 +1226,19 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
static int edma_probe(struct platform_device *pdev)
{
- struct edma_soc_info **info = pdev->dev.platform_data;
- struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
+ struct edma_soc_info *info = pdev->dev.platform_data;
s8 (*queue_priority_mapping)[2];
- int i, j, off, ln, found = 0;
- int status = -1;
+ int i, off, ln;
const s16 (*rsv_chans)[2];
const s16 (*rsv_slots)[2];
const s16 (*xbar_chans)[2];
- int irq[EDMA_MAX_CC] = {0, 0};
- int err_irq[EDMA_MAX_CC] = {0, 0};
- struct resource *r[EDMA_MAX_CC] = {NULL};
- struct resource res[EDMA_MAX_CC];
- char res_name[10];
+ int irq;
+ char *irq_name;
+ struct resource *mem;
struct device_node *node = pdev->dev.of_node;
struct device *dev = &pdev->dev;
+ int dev_id = pdev->id;
+ struct edma *cc;
int ret;
struct platform_device_info edma_dev_info = {
.name = "edma-dma-engine",
@@ -1261,6 +1246,17 @@ static int edma_probe(struct platform_device *pdev)
.parent = &pdev->dev,
};
+ /* When booting with DT the pdev->id is -1 */
+ if (dev_id < 0)
+ dev_id = arch_num_cc;
+
+ if (dev_id >= EDMA_MAX_CC) {
+ dev_err(dev,
+ "eDMA3 with device id 0 and 1 is supported (id: %d)\n",
+ dev_id);
+ return -EINVAL;
+ }
+
if (node) {
/* Check if this is a second instance registered */
if (arch_num_cc) {
@@ -1268,13 +1264,11 @@ static int edma_probe(struct platform_device *pdev)
return -ENODEV;
}
- ninfo[0] = edma_setup_info_from_dt(dev, node);
- if (IS_ERR(ninfo[0])) {
+ info = edma_setup_info_from_dt(dev, node);
+ if (IS_ERR(info)) {
dev_err(dev, "failed to get DT data\n");
- return PTR_ERR(ninfo[0]);
+ return PTR_ERR(info);
}
-
- info = ninfo;
}
if (!info)
@@ -1287,154 +1281,133 @@ static int edma_probe(struct platform_device *pdev)
return ret;
}
- for (j = 0; j < EDMA_MAX_CC; j++) {
- if (!info[j]) {
- if (!found)
- return -ENODEV;
- break;
- }
- if (node) {
- ret = of_address_to_resource(node, j, &res[j]);
- if (!ret)
- r[j] = &res[j];
- } else {
- sprintf(res_name, "edma_cc%d", j);
- r[j] = platform_get_resource_byname(pdev,
- IORESOURCE_MEM,
- res_name);
- }
- if (!r[j]) {
- if (found)
- break;
- else
- return -ENODEV;
- } else {
- found = 1;
+ mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
+ if (!mem) {
+ dev_dbg(dev, "mem resource not found, using index 0\n");
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem) {
+ dev_err(dev, "no mem resource?\n");
+ return -ENODEV;
}
+ }
- edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
- if (IS_ERR(edmacc_regs_base[j]))
- return PTR_ERR(edmacc_regs_base[j]);
+ edmacc_regs_base[dev_id] = devm_ioremap_resource(dev, mem);
+ if (IS_ERR(edmacc_regs_base[dev_id]))
+ return PTR_ERR(edmacc_regs_base[dev_id]);
- edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
- GFP_KERNEL);
- if (!edma_cc[j])
- return -ENOMEM;
+ edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
+ if (!edma_cc[dev_id])
+ return -ENOMEM;
- /* Get eDMA3 configuration from IP */
- ret = edma_setup_from_hw(dev, info[j], edma_cc[j], j);
- if (ret)
- return ret;
+ cc = edma_cc[dev_id];
+ cc->dev = dev;
+ cc->id = dev_id;
+ dev_set_drvdata(dev, cc);
- edma_cc[j]->default_queue = info[j]->default_queue;
+ /* Get eDMA3 configuration from IP */
+ ret = edma_setup_from_hw(dev, info, cc, dev_id);
+ if (ret)
+ return ret;
- dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
- edmacc_regs_base[j]);
+ cc->default_queue = info->default_queue;
- for (i = 0; i < edma_cc[j]->num_slots; i++)
- memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
- &dummy_paramset, PARM_SIZE);
+ dev_dbg(dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[dev_id]);
- /* Mark all channels as unused */
- memset(edma_cc[j]->edma_unused, 0xff,
- sizeof(edma_cc[j]->edma_unused));
+ for (i = 0; i < cc->num_slots; i++)
+ memcpy_toio(edmacc_regs_base[dev_id] + PARM_OFFSET(i),
+ &dummy_paramset, PARM_SIZE);
- if (info[j]->rsv) {
+ /* Mark all channels as unused */
+ memset(cc->edma_unused, 0xff, sizeof(cc->edma_unused));
- /* Clear the reserved channels in unused list */
- rsv_chans = info[j]->rsv->rsv_chans;
- if (rsv_chans) {
- for (i = 0; rsv_chans[i][0] != -1; i++) {
- off = rsv_chans[i][0];
- ln = rsv_chans[i][1];
- clear_bits(off, ln,
- edma_cc[j]->edma_unused);
- }
- }
+ if (info->rsv) {
- /* Set the reserved slots in inuse list */
- rsv_slots = info[j]->rsv->rsv_slots;
- if (rsv_slots) {
- for (i = 0; rsv_slots[i][0] != -1; i++) {
- off = rsv_slots[i][0];
- ln = rsv_slots[i][1];
- set_bits(off, ln,
- edma_cc[j]->edma_inuse);
- }
+ /* Clear the reserved channels in unused list */
+ rsv_chans = info->rsv->rsv_chans;
+ if (rsv_chans) {
+ for (i = 0; rsv_chans[i][0] != -1; i++) {
+ off = rsv_chans[i][0];
+ ln = rsv_chans[i][1];
+ clear_bits(off, ln, cc->edma_unused);
}
}
- /* Clear the xbar mapped channels in unused list */
- xbar_chans = info[j]->xbar_chans;
- if (xbar_chans) {
- for (i = 0; xbar_chans[i][1] != -1; i++) {
- off = xbar_chans[i][1];
- clear_bits(off, 1,
- edma_cc[j]->edma_unused);
+ /* Set the reserved slots in inuse list */
+ rsv_slots = info->rsv->rsv_slots;
+ if (rsv_slots) {
+ for (i = 0; rsv_slots[i][0] != -1; i++) {
+ off = rsv_slots[i][0];
+ ln = rsv_slots[i][1];
+ set_bits(off, ln, cc->edma_inuse);
}
}
+ }
- if (node) {
- irq[j] = irq_of_parse_and_map(node, 0);
- err_irq[j] = irq_of_parse_and_map(node, 2);
- } else {
- char irq_name[10];
-
- sprintf(irq_name, "edma%d", j);
- irq[j] = platform_get_irq_byname(pdev, irq_name);
-
- sprintf(irq_name, "edma%d_err", j);
- err_irq[j] = platform_get_irq_byname(pdev, irq_name);
- }
- edma_cc[j]->irq_res_start = irq[j];
- edma_cc[j]->irq_res_end = err_irq[j];
-
- status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
- "edma", dev);
- if (status < 0) {
- dev_dbg(&pdev->dev,
- "devm_request_irq %d failed --> %d\n",
- irq[j], status);
- return status;
+ /* Clear the xbar mapped channels in unused list */
+ xbar_chans = info->xbar_chans;
+ if (xbar_chans) {
+ for (i = 0; xbar_chans[i][1] != -1; i++) {
+ off = xbar_chans[i][1];
+ clear_bits(off, 1, cc->edma_unused);
}
+ }
- status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
- "edma_error", dev);
- if (status < 0) {
- dev_dbg(&pdev->dev,
- "devm_request_irq %d failed --> %d\n",
- err_irq[j], status);
- return status;
+ irq = platform_get_irq_byname(pdev, "edma3_ccint");
+ if (irq < 0 && node)
+ irq = irq_of_parse_and_map(node, 0);
+
+ if (irq >= 0) {
+ irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint\n",
+ dev_name(dev));
+ ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
+ cc);
+ if (ret) {
+ dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
+ return ret;
}
+ }
- for (i = 0; i < edma_cc[j]->num_channels; i++)
- map_dmach_queue(j, i, info[j]->default_queue);
+ irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
+ if (irq < 0 && node)
+ irq = irq_of_parse_and_map(node, 2);
+
+ if (irq >= 0) {
+ irq_name = devm_kasprintf(dev, GFP_KERNEL,
+ "%s_ccerrint\n",
+ dev_name(dev));
+ ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
+ cc);
+ if (ret) {
+ dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
+ return ret;
+ }
+ }
- queue_priority_mapping = info[j]->queue_priority_mapping;
+ for (i = 0; i < cc->num_channels; i++)
+ map_dmach_queue(dev_id, i, info->default_queue);
- /* Event queue priority mapping */
- for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(j,
- queue_priority_mapping[i][0],
- queue_priority_mapping[i][1]);
+ queue_priority_mapping = info->queue_priority_mapping;
- /* Map the channel to param entry if channel mapping logic
- * exist
- */
- if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(j);
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ assign_priority_to_queue(dev_id, queue_priority_mapping[i][0],
+ queue_priority_mapping[i][1]);
- for (i = 0; i < edma_cc[j]->num_region; i++) {
- edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
- edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
- edma_write_array(j, EDMA_QRAE, i, 0x0);
- }
- edma_cc[j]->info = info[j];
- arch_num_cc++;
+ /* Map the channel to param entry if channel mapping logic exist */
+ if (edma_read(dev_id, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(dev_id);
- edma_dev_info.id = j;
- platform_device_register_full(&edma_dev_info);
+ for (i = 0; i < cc->num_region; i++) {
+ edma_write_array2(dev_id, EDMA_DRAE, i, 0, 0x0);
+ edma_write_array2(dev_id, EDMA_DRAE, i, 1, 0x0);
+ edma_write_array(dev_id, EDMA_QRAE, i, 0x0);
}
+ cc->info = info;
+ arch_num_cc++;
+
+ edma_dev_info.id = dev_id;
+
+ platform_device_register_full(&edma_dev_info);
return 0;
}
@@ -1442,38 +1415,30 @@ static int edma_probe(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int edma_pm_resume(struct device *dev)
{
- int i, j;
+ struct edma *cc = dev_get_drvdata(dev);
+ int i;
+ s8 (*queue_priority_mapping)[2];
- for (j = 0; j < arch_num_cc; j++) {
- struct edma *cc = edma_cc[j];
+ queue_priority_mapping = cc->info->queue_priority_mapping;
- s8 (*queue_priority_mapping)[2];
+ /* Event queue priority mapping */
+ for (i = 0; queue_priority_mapping[i][0] != -1; i++)
+ assign_priority_to_queue(cc->id, queue_priority_mapping[i][0],
+ queue_priority_mapping[i][1]);
- queue_priority_mapping = cc->info->queue_priority_mapping;
+ /* Map the channel to param entry if channel mapping logic */
+ if (edma_read(cc->id, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(cc->id);
- /* Event queue priority mapping */
- for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(j,
- queue_priority_mapping[i][0],
- queue_priority_mapping[i][1]);
+ for (i = 0; i < cc->num_channels; i++) {
+ if (test_bit(i, cc->edma_inuse)) {
+ /* ensure access through shadow region 0 */
+ edma_or_array2(cc->id, EDMA_DRAE, 0, i >> 5,
+ BIT(i & 0x1f));
- /*
- * Map the channel to param entry if channel mapping logic
- * exist
- */
- if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(j);
-
- for (i = 0; i < cc->num_channels; i++) {
- if (test_bit(i, cc->edma_inuse)) {
- /* ensure access through shadow region 0 */
- edma_or_array2(j, EDMA_DRAE, 0, i >> 5,
- BIT(i & 0x1f));
-
- setup_dma_interrupt(i,
- cc->intr_data[i].callback,
- cc->intr_data[i].data);
- }
+ setup_dma_interrupt(EDMA_CTLR_CHAN(cc->id, i),
+ cc->intr_data[i].callback,
+ cc->intr_data[i].data);
}
}
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 29e08aac8294..9ae049ae816a 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -147,150 +147,114 @@ static s8 da850_queue_priority_mapping[][2] = {
{-1, -1}
};
-static struct edma_soc_info da830_edma_cc0_info = {
+static struct edma_soc_info da8xx_edma0_pdata = {
.queue_priority_mapping = da8xx_queue_priority_mapping,
.default_queue = EVENTQ_1,
};
-static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
- &da830_edma_cc0_info,
+static struct edma_soc_info da850_edma1_pdata = {
+ .queue_priority_mapping = da850_queue_priority_mapping,
+ .default_queue = EVENTQ_0,
};
-static struct edma_soc_info da850_edma_cc_info[] = {
+static struct resource da8xx_edma0_resources[] = {
{
- .queue_priority_mapping = da8xx_queue_priority_mapping,
- .default_queue = EVENTQ_1,
- },
- {
- .queue_priority_mapping = da850_queue_priority_mapping,
- .default_queue = EVENTQ_0,
- },
-};
-
-static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
- &da850_edma_cc_info[0],
- &da850_edma_cc_info[1],
-};
-
-static struct resource da830_edma_resources[] = {
- {
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = DA8XX_TPCC_BASE,
.end = DA8XX_TPCC_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = DA8XX_TPTC0_BASE,
.end = DA8XX_TPTC0_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = DA8XX_TPTC1_BASE,
.end = DA8XX_TPTC1_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_DA8XX_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_DA8XX_CCERRINT,
.flags = IORESOURCE_IRQ,
},
};
-static struct resource da850_edma_resources[] = {
- {
- .name = "edma_cc0",
- .start = DA8XX_TPCC_BASE,
- .end = DA8XX_TPCC_BASE + SZ_32K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma_tc0",
- .start = DA8XX_TPTC0_BASE,
- .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
+static struct resource da850_edma1_resources[] = {
{
- .name = "edma_tc1",
- .start = DA8XX_TPTC1_BASE,
- .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .name = "edma_cc1",
+ .name = "edma3_cc",
.start = DA850_TPCC1_BASE,
.end = DA850_TPCC1_BASE + SZ_32K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc2",
+ .name = "edma3_tc0",
.start = DA850_TPTC2_BASE,
.end = DA850_TPTC2_BASE + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
- .start = IRQ_DA8XX_CCINT0,
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma0_err",
- .start = IRQ_DA8XX_CCERRINT,
- .flags = IORESOURCE_IRQ,
- },
- {
- .name = "edma1",
+ .name = "edma3_ccint",
.start = IRQ_DA850_CCINT1,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma1_err",
+ .name = "edma3_ccerrint",
.start = IRQ_DA850_CCERRINT1,
.flags = IORESOURCE_IRQ,
},
};
-static struct platform_device da830_edma_device = {
+static struct platform_device da8xx_edma0_device = {
.name = "edma",
- .id = -1,
+ .id = 0,
.dev = {
- .platform_data = da830_edma_info,
+ .platform_data = &da8xx_edma0_pdata,
},
- .num_resources = ARRAY_SIZE(da830_edma_resources),
- .resource = da830_edma_resources,
+ .num_resources = ARRAY_SIZE(da8xx_edma0_resources),
+ .resource = da8xx_edma0_resources,
};
-static struct platform_device da850_edma_device = {
+static struct platform_device da850_edma1_device = {
.name = "edma",
- .id = -1,
+ .id = 1,
.dev = {
- .platform_data = da850_edma_info,
+ .platform_data = &da850_edma1_pdata,
},
- .num_resources = ARRAY_SIZE(da850_edma_resources),
- .resource = da850_edma_resources,
+ .num_resources = ARRAY_SIZE(da850_edma1_resources),
+ .resource = da850_edma1_resources,
};
int __init da830_register_edma(struct edma_rsv_info *rsv)
{
- da830_edma_cc0_info.rsv = rsv;
+ da8xx_edma0_pdata.rsv = rsv;
- return platform_device_register(&da830_edma_device);
+ return platform_device_register(&da8xx_edma0_device);
}
int __init da850_register_edma(struct edma_rsv_info *rsv[2])
{
+ int ret;
+
if (rsv) {
- da850_edma_cc_info[0].rsv = rsv[0];
- da850_edma_cc_info[1].rsv = rsv[1];
+ da8xx_edma0_pdata.rsv = rsv[0];
+ da850_edma1_pdata.rsv = rsv[1];
}
- return platform_device_register(&da850_edma_device);
+ ret = platform_device_register(&da8xx_edma0_device);
+ if (ret) {
+ pr_warn("%s: Failed to register eDMA0\n", __func__);
+ return ret;
+ }
+ return platform_device_register(&da850_edma1_device);
}
static struct resource da8xx_i2c_resources0[] = {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 567dc56fe8cd..a50bb9c66952 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -569,49 +569,44 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
-static s8
-queue_priority_mapping[][2] = {
+static s8 queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
{1, 7},
{-1, -1},
};
-static struct edma_soc_info edma_cc0_info = {
+static struct edma_soc_info dm355_edma_pdata = {
.queue_priority_mapping = queue_priority_mapping,
.default_queue = EVENTQ_1,
};
-static struct edma_soc_info *dm355_edma_info[EDMA_MAX_CC] = {
- &edma_cc0_info,
-};
-
static struct resource edma_resources[] = {
{
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.flags = IORESOURCE_IRQ,
},
@@ -621,7 +616,7 @@ static struct resource edma_resources[] = {
static struct platform_device dm355_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = dm355_edma_info,
+ .dev.platform_data = &dm355_edma_pdata,
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 6a890a8486d0..2068cbeaeb03 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -853,8 +853,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
};
/* Four Transfer Controllers on DM365 */
-static s8
-dm365_queue_priority_mapping[][2] = {
+static s8 dm365_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 7},
{1, 7},
@@ -863,53 +862,49 @@ dm365_queue_priority_mapping[][2] = {
{-1, -1},
};
-static struct edma_soc_info edma_cc0_info = {
+static struct edma_soc_info dm365_edma_pdata = {
.queue_priority_mapping = dm365_queue_priority_mapping,
.default_queue = EVENTQ_3,
};
-static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
- &edma_cc0_info,
-};
-
static struct resource edma_resources[] = {
{
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc2",
+ .name = "edma3_tc2",
.start = 0x01c10800,
.end = 0x01c10800 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc3",
+ .name = "edma3_tc3",
.start = 0x01c10c00,
.end = 0x01c10c00 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.flags = IORESOURCE_IRQ,
},
@@ -919,7 +914,7 @@ static struct resource edma_resources[] = {
static struct platform_device dm365_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = dm365_edma_info,
+ .dev.platform_data = &dm365_edma_pdata,
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index dc52657909c4..d759ca8e58e8 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -498,49 +498,44 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
-static s8
-queue_priority_mapping[][2] = {
+static s8 queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 3},
{1, 7},
{-1, -1},
};
-static struct edma_soc_info edma_cc0_info = {
+static struct edma_soc_info dm644x_edma_pdata = {
.queue_priority_mapping = queue_priority_mapping,
.default_queue = EVENTQ_1,
};
-static struct edma_soc_info *dm644x_edma_info[EDMA_MAX_CC] = {
- &edma_cc0_info,
-};
-
static struct resource edma_resources[] = {
{
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.flags = IORESOURCE_IRQ,
},
@@ -550,7 +545,7 @@ static struct resource edma_resources[] = {
static struct platform_device dm644x_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = dm644x_edma_info,
+ .dev.platform_data = &dm644x_edma_pdata,
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 3f842bb266d6..219ebc8f674a 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -531,8 +531,7 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
/*----------------------------------------------------------------------*/
/* Four Transfer Controllers on DM646x */
-static s8
-dm646x_queue_priority_mapping[][2] = {
+static s8 dm646x_queue_priority_mapping[][2] = {
/* {event queue no, Priority} */
{0, 4},
{1, 0},
@@ -541,53 +540,49 @@ dm646x_queue_priority_mapping[][2] = {
{-1, -1},
};
-static struct edma_soc_info edma_cc0_info = {
+static struct edma_soc_info dm646x_edma_pdata = {
.queue_priority_mapping = dm646x_queue_priority_mapping,
.default_queue = EVENTQ_1,
};
-static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
- &edma_cc0_info,
-};
-
static struct resource edma_resources[] = {
{
- .name = "edma_cc0",
+ .name = "edma3_cc",
.start = 0x01c00000,
.end = 0x01c00000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc0",
+ .name = "edma3_tc0",
.start = 0x01c10000,
.end = 0x01c10000 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc1",
+ .name = "edma3_tc1",
.start = 0x01c10400,
.end = 0x01c10400 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc2",
+ .name = "edma3_tc2",
.start = 0x01c10800,
.end = 0x01c10800 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma_tc3",
+ .name = "edma3_tc3",
.start = 0x01c10c00,
.end = 0x01c10c00 + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
{
- .name = "edma0",
+ .name = "edma3_ccint",
.start = IRQ_CCINT0,
.flags = IORESOURCE_IRQ,
},
{
- .name = "edma0_err",
+ .name = "edma3_ccerrint",
.start = IRQ_CCERRINT,
.flags = IORESOURCE_IRQ,
},
@@ -597,7 +592,7 @@ static struct resource edma_resources[] = {
static struct platform_device dm646x_edma_device = {
.name = "edma",
.id = 0,
- .dev.platform_data = dm646x_edma_info,
+ .dev.platform_data = &dm646x_edma_pdata,
.num_resources = ARRAY_SIZE(edma_resources),
.resource = edma_resources,
};
@@ -936,7 +931,7 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
int __init dm646x_init_edma(struct edma_rsv_info *rsv)
{
- edma_cc0_info.rsv = rsv;
+ dm646x_edma_pdata.rsv = rsv;
return platform_device_register(&dm646x_edma_device);
}
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-18 13:50 +0200 |
| Subject | Re: [PATCH v2 04/23] ARM: davinci/common: Convert edma driver to handle one eDMA instance per driver |
| Message-ID | <qa2kW-1xG-11@gated-at.bofh.it> |
| In reply to | #1222807 |
On 09/11/2015 03:27 PM, Peter Ujfalusi wrote:
> + if (irq >= 0) {
> + irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint\n",
The '\n' should not be in the format string.
> + dev_name(dev));
> + ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
> + cc);
> + if (ret) {
> + dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
> + return ret;
> }
> + }
>
> - for (i = 0; i < edma_cc[j]->num_channels; i++)
> - map_dmach_queue(j, i, info[j]->default_queue);
> + irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
> + if (irq < 0 && node)
> + irq = irq_of_parse_and_map(node, 2);
> +
> + if (irq >= 0) {
> + irq_name = devm_kasprintf(dev, GFP_KERNEL,
> + "%s_ccerrint\n",
Same here.
> + dev_name(dev));
> + ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
> + cc);
> + if (ret) {
> + dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
> + return ret;
> + }
> + }
--
Péter
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:40 +0200 |
| Subject | [PATCH v2 12/23] dmaengine: edma: Allocate memory dynamically for bitmaps and structures |
| Message-ID | <q7vMw-1Di-49@gated-at.bofh.it> |
| In reply to | #1222789 |
Instead of using defines to specify the size of different arrays and
bitmaps, allocate the memory for them based on the information we get from
the HW itself.
Since these defines are set based on the worst case, there are devices
where they are not valid.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
drivers/dma/edma.c | 62 ++++++++++++++++++++++++++++++------------------------
1 file changed, 34 insertions(+), 28 deletions(-)
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index 8912049111a2..a08ca0800b95 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -113,23 +113,6 @@
#define CHMAP_EXIST BIT(24)
/*
- * This will go away when the private EDMA API is folded
- * into this driver and the platform device(s) are
- * instantiated in the arch code. We can only get away
- * with this simplification because DA8XX may not be built
- * in the same kernel image with other DaVinci parts. This
- * avoids having to sprinkle dmaengine driver platform devices
- * and data throughout all the existing board files.
- */
-#ifdef CONFIG_ARCH_DAVINCI_DA8XX
-#define EDMA_CTLRS 2
-#define EDMA_CHANS 32
-#else
-#define EDMA_CTLRS 1
-#define EDMA_CHANS 64
-#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
-
-/*
* Max of 20 segments per channel to conserve PaRAM slots
* Also note that MAX_NR_SG should be atleast the no.of periods
* that are required for ASoC, otherwise DMA prep calls will
@@ -140,16 +123,12 @@
#define EDMA_MAX_SLOTS MAX_NR_SG
#define EDMA_DESCRIPTORS 16
-#define EDMA_MAX_PARAMENTRY 512
-
#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
#define EDMA_CONT_PARAMS_ANY 1001
#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-#define EDMA_MAX_CC 2
-
/* PaRAM slots are laid out like this */
struct edmacc_param {
u32 opt;
@@ -256,22 +235,22 @@ struct edma_cc {
/* The edma_inuse bit for each PaRAM slot is clear unless the
* channel is in use ... by ARM or DSP, for QDMA, or whatever.
*/
- DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
+ unsigned long *edma_inuse;
/* The edma_unused bit for each channel is clear unless
* it is not being used on this platform. It uses a bit
* of SOC-specific initialization code.
*/
- DECLARE_BITMAP(edma_unused, EDMA_CHANS);
+ unsigned long *edma_unused;
struct dma_interrupt_data {
void (*callback)(unsigned channel, unsigned short ch_status,
void *data);
void *data;
- } intr_data[EDMA_CHANS];
+ } *intr_data;
struct dma_device dma_slave;
- struct edma_chan slave_chans[EDMA_CHANS];
+ struct edma_chan *slave_chans;
int dummy_slot;
};
@@ -431,6 +410,8 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
struct edma_cc *ecc = data;
+ int dma_req_min = EDMA_CTLR_CHAN(ecc->id, 0);
+ int dma_req_max = dma_req_min + ecc->num_channels;
int i, count;
struct of_phandle_args dma_spec;
@@ -466,11 +447,15 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
/* For non-OF case */
for (i = 0; i < pdev->num_resources; i++) {
struct resource *res = &pdev->resource[i];
+ int dma_req;
+
+ if (!(res->flags & IORESOURCE_DMA))
+ continue;
- if ((res->flags & IORESOURCE_DMA) && (int)res->start >= 0) {
+ dma_req = (int)res->start;
+ if (dma_req >= dma_req_min && dma_req < dma_req_max)
clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
ecc->edma_unused);
- }
}
return 0;
@@ -1953,7 +1938,7 @@ static void __init edma_chan_init(struct edma_cc *ecc,
{
int i, j;
- for (i = 0; i < EDMA_CHANS; i++) {
+ for (i = 0; i < ecc->num_channels; i++) {
struct edma_chan *echan = &echans[i];
echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
echan->ecc = ecc;
@@ -2222,6 +2207,27 @@ static int edma_probe(struct platform_device *pdev)
if (ret)
return ret;
+ /* Allocate memory based on the information we got from the IP */
+ ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
+ sizeof(*ecc->slave_chans), GFP_KERNEL);
+ if (!ecc->slave_chans)
+ return -ENOMEM;
+
+ ecc->intr_data = devm_kcalloc(dev, ecc->num_channels,
+ sizeof(*ecc->intr_data), GFP_KERNEL);
+ if (!ecc->intr_data)
+ return -ENOMEM;
+
+ ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels),
+ sizeof(unsigned long), GFP_KERNEL);
+ if (!ecc->edma_unused)
+ return -ENOMEM;
+
+ ecc->edma_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
+ sizeof(unsigned long), GFP_KERNEL);
+ if (!ecc->edma_inuse)
+ return -ENOMEM;
+
ecc->default_queue = info->default_queue;
for (i = 0; i < ecc->num_slots; i++)
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:40 +0200 |
| Subject | [PATCH v2 02/23] ARM: common: edma: Remove unused functions |
| Message-ID | <q7vMu-1Di-23@gated-at.bofh.it> |
| In reply to | #1222789 |
We no longer have users for these functions so they can be removed.
Remove also unused enums from the header file.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 376 -------------------------------------
include/linux/platform_data/edma.h | 33 ----
2 files changed, 409 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 56fc339571f9..e9c4cb16a47e 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -510,62 +510,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
return IRQ_HANDLED;
}
-static int reserve_contiguous_slots(int ctlr, unsigned int id,
- unsigned int num_slots,
- unsigned int start_slot)
-{
- int i, j;
- unsigned int count = num_slots;
- int stop_slot = start_slot;
- DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
-
- for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
- j = EDMA_CHAN_SLOT(i);
- if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
- /* Record our current beginning slot */
- if (count == num_slots)
- stop_slot = i;
-
- count--;
- set_bit(j, tmp_inuse);
-
- if (count == 0)
- break;
- } else {
- clear_bit(j, tmp_inuse);
-
- if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
- stop_slot = i;
- break;
- } else {
- count = num_slots;
- }
- }
- }
-
- /*
- * We have to clear any bits that we set
- * if we run out parameter RAM slots, i.e we do find a set
- * of contiguous parameter RAM slots but do not find the exact number
- * requested as we may reach the total number of parameter RAM slots
- */
- if (i == edma_cc[ctlr]->num_slots)
- stop_slot = i;
-
- j = start_slot;
- for_each_set_bit_from(j, tmp_inuse, stop_slot)
- clear_bit(j, edma_cc[ctlr]->edma_inuse);
-
- if (count)
- return -EBUSY;
-
- for (j = i - num_slots + 1; j <= i; ++j)
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
- &dummy_paramset, PARM_SIZE);
-
- return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
-}
-
static int prepare_unused_channel_list(struct device *dev, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -818,186 +762,11 @@ void edma_free_slot(unsigned slot)
}
EXPORT_SYMBOL(edma_free_slot);
-
-/**
- * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
- * The API will return the starting point of a set of
- * contiguous parameter RAM slots that have been requested
- *
- * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
- * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- * @count: number of contiguous Paramter RAM slots
- * @slot - the start value of Parameter RAM slot that should be passed if id
- * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
- *
- * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
- * contiguous Parameter RAM slots from parameter RAM 64 in the case of
- * DaVinci SOCs and 32 in the case of DA8xx SOCs.
- *
- * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
- * set of contiguous parameter RAM slots from the "slot" that is passed as an
- * argument to the API.
- *
- * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
- * starts looking for a set of contiguous parameter RAMs from the "slot"
- * that is passed as an argument to the API. On failure the API will try to
- * find a set of contiguous Parameter RAM slots from the remaining Parameter
- * RAM slots
- */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
-{
- /*
- * The start slot requested should be greater than
- * the number of channels and lesser than the total number
- * of slots
- */
- if ((id != EDMA_CONT_PARAMS_ANY) &&
- (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots))
- return -EINVAL;
-
- /*
- * The number of parameter RAM slots requested cannot be less than 1
- * and cannot be more than the number of slots minus the number of
- * channels
- */
- if (count < 1 || count >
- (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
- return -EINVAL;
-
- switch (id) {
- case EDMA_CONT_PARAMS_ANY:
- return reserve_contiguous_slots(ctlr, id, count,
- edma_cc[ctlr]->num_channels);
- case EDMA_CONT_PARAMS_FIXED_EXACT:
- case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
- return reserve_contiguous_slots(ctlr, id, count, slot);
- default:
- return -EINVAL;
- }
-
-}
-EXPORT_SYMBOL(edma_alloc_cont_slots);
-
-/**
- * edma_free_cont_slots - deallocate DMA parameter RAM slots
- * @slot: first parameter RAM of a set of parameter RAM slots to be freed
- * @count: the number of contiguous parameter RAM slots to be freed
- *
- * This deallocates the parameter RAM slots allocated by
- * edma_alloc_cont_slots.
- * Callers/applications need to keep track of sets of contiguous
- * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
- * API.
- * Callers are responsible for ensuring the slots are inactive, and will
- * not be activated.
- */
-int edma_free_cont_slots(unsigned slot, int count)
-{
- unsigned ctlr, slot_to_free;
- int i;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_channels ||
- slot >= edma_cc[ctlr]->num_slots ||
- count < 1)
- return -EINVAL;
-
- for (i = slot; i < slot + count; ++i) {
- ctlr = EDMA_CTLR(i);
- slot_to_free = EDMA_CHAN_SLOT(i);
-
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
- &dummy_paramset, PARM_SIZE);
- clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
- }
-
- return 0;
-}
-EXPORT_SYMBOL(edma_free_cont_slots);
-
/*-----------------------------------------------------------------------*/
/* Parameter RAM operations (i) -- read/write partial slots */
/**
- * edma_set_src - set initial DMA source address in parameter RAM slot
- * @slot: parameter RAM slot being configured
- * @src_port: physical address of source (memory, controller FIFO, etc)
- * @addressMode: INCR, except in very rare cases
- * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- *
- * Note that the source address is modified during the DMA transfer
- * according to edma_set_src_index().
- */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
- enum address_mode mode, enum fifo_width width)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-
- if (mode) {
- /* set SAM and program FWID */
- i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
- } else {
- /* clear SAM */
- i &= ~SAM;
- }
- edma_parm_write(ctlr, PARM_OPT, slot, i);
-
- /* set the source port address
- in source register of param structure */
- edma_parm_write(ctlr, PARM_SRC, slot, src_port);
- }
-}
-EXPORT_SYMBOL(edma_set_src);
-
-/**
- * edma_set_dest - set initial DMA destination address in parameter RAM slot
- * @slot: parameter RAM slot being configured
- * @dest_port: physical address of destination (memory, controller FIFO, etc)
- * @addressMode: INCR, except in very rare cases
- * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
- * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
- *
- * Note that the destination address is modified during the DMA transfer
- * according to edma_set_dest_index().
- */
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- enum address_mode mode, enum fifo_width width)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
-
- if (mode) {
- /* set DAM and program FWID */
- i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
- } else {
- /* clear DAM */
- i &= ~DAM;
- }
- edma_parm_write(ctlr, PARM_OPT, slot, i);
- /* set the destination port address
- in dest register of param structure */
- edma_parm_write(ctlr, PARM_DST, slot, dest_port);
- }
-}
-EXPORT_SYMBOL(edma_set_dest);
-
-/**
* edma_get_position - returns the current transfer point
* @slot: parameter RAM slot being examined
* @dst: true selects the dest position, false the source
@@ -1017,110 +786,6 @@ dma_addr_t edma_get_position(unsigned slot, bool dst)
}
/**
- * edma_set_src_index - configure DMA source address indexing
- * @slot: parameter RAM slot being configured
- * @src_bidx: byte offset between source arrays in a frame
- * @src_cidx: byte offset between source frames in a block
- *
- * Offsets are specified to support either contiguous or discontiguous
- * memory transfers, or repeated access to a hardware register, as needed.
- * When accessing hardware registers, both offsets are normally zero.
- */
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- 0xffff0000, src_bidx);
- edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- 0xffff0000, src_cidx);
- }
-}
-EXPORT_SYMBOL(edma_set_src_index);
-
-/**
- * edma_set_dest_index - configure DMA destination address indexing
- * @slot: parameter RAM slot being configured
- * @dest_bidx: byte offset between destination arrays in a frame
- * @dest_cidx: byte offset between destination frames in a block
- *
- * Offsets are specified to support either contiguous or discontiguous
- * memory transfers, or repeated access to a hardware register, as needed.
- * When accessing hardware registers, both offsets are normally zero.
- */
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
- 0x0000ffff, dest_bidx << 16);
- edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
- 0x0000ffff, dest_cidx << 16);
- }
-}
-EXPORT_SYMBOL(edma_set_dest_index);
-
-/**
- * edma_set_transfer_params - configure DMA transfer parameters
- * @slot: parameter RAM slot being configured
- * @acnt: how many bytes per array (at least one)
- * @bcnt: how many arrays per frame (at least one)
- * @ccnt: how many frames per block (at least one)
- * @bcnt_rld: used only for A-Synchronized transfers; this specifies
- * the value to reload into bcnt when it decrements to zero
- * @sync_mode: ASYNC or ABSYNC
- *
- * See the EDMA3 documentation to understand how to configure and link
- * transfers using the fields in PaRAM slots. If you are not doing it
- * all at once with edma_write_slot(), you will use this routine
- * plus two calls each for source and destination, setting the initial
- * address and saying how to index that address.
- *
- * An example of an A-Synchronized transfer is a serial link using a
- * single word shift register. In that case, @acnt would be equal to
- * that word size; the serial controller issues a DMA synchronization
- * event to transfer each word, and memory access by the DMA transfer
- * controller will be word-at-a-time.
- *
- * An example of an AB-Synchronized transfer is a device using a FIFO.
- * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
- * The controller with the FIFO issues DMA synchronization events when
- * the FIFO threshold is reached, and the DMA transfer controller will
- * transfer one frame to (or from) the FIFO. It will probably use
- * efficient burst modes to access memory.
- */
-void edma_set_transfer_params(unsigned slot,
- u16 acnt, u16 bcnt, u16 ccnt,
- u16 bcnt_rld, enum sync_dimension sync_mode)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(slot);
- slot = EDMA_CHAN_SLOT(slot);
-
- if (slot < edma_cc[ctlr]->num_slots) {
- edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
- 0x0000ffff, bcnt_rld << 16);
- if (sync_mode == ASYNC)
- edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
- else
- edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
- /* Set the acount, bcount, ccount registers */
- edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
- edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
- }
-}
-EXPORT_SYMBOL(edma_set_transfer_params);
-
-/**
* edma_link - link one parameter RAM slot to another
* @from: parameter RAM slot originating the link
* @to: parameter RAM slot which is the link target
@@ -1145,26 +810,6 @@ void edma_link(unsigned from, unsigned to)
}
EXPORT_SYMBOL(edma_link);
-/**
- * edma_unlink - cut link from one parameter RAM slot
- * @from: parameter RAM slot originating the link
- *
- * The originating slot should not be part of any active DMA transfer.
- * Its link is set to 0xffff.
- */
-void edma_unlink(unsigned from)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(from);
- from = EDMA_CHAN_SLOT(from);
-
- if (from >= edma_cc[ctlr]->num_slots)
- return;
- edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
-}
-EXPORT_SYMBOL(edma_unlink);
-
/*-----------------------------------------------------------------------*/
/* Parameter RAM operations (ii) -- read/write whole parameter sets */
@@ -1402,27 +1047,6 @@ void edma_clean_channel(unsigned channel)
EXPORT_SYMBOL(edma_clean_channel);
/*
- * edma_clear_event - clear an outstanding event on the DMA channel
- * Arguments:
- * channel - channel number
- */
-void edma_clear_event(unsigned channel)
-{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(channel);
- channel = EDMA_CHAN_SLOT(channel);
-
- if (channel >= edma_cc[ctlr]->num_channels)
- return;
- if (channel < 32)
- edma_write(ctlr, EDMA_ECR, BIT(channel));
- else
- edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
-}
-EXPORT_SYMBOL(edma_clear_event);
-
-/*
* edma_assign_channel_eventq - move given channel to desired eventq
* Arguments:
* channel - channel number
diff --git a/include/linux/platform_data/edma.h b/include/linux/platform_data/edma.h
index bdb2710e2aab..c1862423b356 100644
--- a/include/linux/platform_data/edma.h
+++ b/include/linux/platform_data/edma.h
@@ -72,20 +72,6 @@ struct edmacc_param {
#define EDMA_DMA_TC1_ERROR 3
#define EDMA_DMA_TC2_ERROR 4
-enum address_mode {
- INCR = 0,
- FIFO = 1
-};
-
-enum fifo_width {
- W8BIT = 0,
- W16BIT = 1,
- W32BIT = 2,
- W64BIT = 3,
- W128BIT = 4,
- W256BIT = 5
-};
-
enum dma_event_q {
EVENTQ_0 = 0,
EVENTQ_1 = 1,
@@ -94,11 +80,6 @@ enum dma_event_q {
EVENTQ_DEFAULT = -1
};
-enum sync_dimension {
- ASYNC = 0,
- ABSYNC = 1
-};
-
#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
#define EDMA_CTLR(i) ((i) >> 16)
#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
@@ -121,22 +102,9 @@ void edma_free_channel(unsigned channel);
int edma_alloc_slot(unsigned ctlr, int slot);
void edma_free_slot(unsigned slot);
-/* alloc/free a set of contiguous parameter RAM slots */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-int edma_free_cont_slots(unsigned slot, int count);
-
/* calls that operate on part of a parameter RAM slot */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
- enum address_mode mode, enum fifo_width);
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
- enum address_mode mode, enum fifo_width);
dma_addr_t edma_get_position(unsigned slot, bool dst);
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
- u16 bcnt_rld, enum sync_dimension sync_mode);
void edma_link(unsigned from, unsigned to);
-void edma_unlink(unsigned from);
/* calls that operate on an entire parameter RAM slot */
void edma_write_slot(unsigned slot, const struct edmacc_param *params);
@@ -146,7 +114,6 @@ void edma_read_slot(unsigned slot, struct edmacc_param *params);
int edma_start(unsigned channel);
void edma_stop(unsigned channel);
void edma_clean_channel(unsigned channel);
-void edma_clear_event(unsigned channel);
void edma_pause(unsigned channel);
void edma_resume(unsigned channel);
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-11 14:40 +0200 |
| Subject | [PATCH v2 06/23] ARM: common: edma: Internal API to use pointer to 'struct edma' |
| Message-ID | <q7vMw-1Di-55@gated-at.bofh.it> |
| In reply to | #1222789 |
Merge the iomem into the 'struct edma' and change the internal (static)
functions to use pointer to the edma_cc instead of the ctlr number.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/common/edma.c | 400 ++++++++++++++++++++++++-------------------------
1 file changed, 197 insertions(+), 203 deletions(-)
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index dc960de1a95f..5fd8293a48aa 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -114,108 +114,141 @@
#define EDMA_MAX_PARAMENTRY 512
/*****************************************************************************/
+struct edma {
+ struct device *dev;
+ void __iomem *base;
+
+ /* how many dma resources of each type */
+ unsigned num_channels;
+ unsigned num_region;
+ unsigned num_slots;
+ unsigned num_tc;
+ enum dma_event_q default_queue;
-static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
+ /* list of channels with no even trigger; terminated by "-1" */
+ const s8 *noevent;
+
+ struct edma_soc_info *info;
+ int id;
+
+ /* The edma_inuse bit for each PaRAM slot is clear unless the
+ * channel is in use ... by ARM or DSP, for QDMA, or whatever.
+ */
+ DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
-static inline unsigned int edma_read(unsigned ctlr, int offset)
+ /* The edma_unused bit for each channel is clear unless
+ * it is not being used on this platform. It uses a bit
+ * of SOC-specific initialization code.
+ */
+ DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
+
+ struct dma_interrupt_data {
+ void (*callback)(unsigned channel, unsigned short ch_status,
+ void *data);
+ void *data;
+ } intr_data[EDMA_MAX_DMACH];
+};
+/*****************************************************************************/
+
+static inline unsigned int edma_read(struct edma *cc, int offset)
{
- return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
+ return (unsigned int)__raw_readl(cc->base + offset);
}
-static inline void edma_write(unsigned ctlr, int offset, int val)
+static inline void edma_write(struct edma *cc, int offset, int val)
{
- __raw_writel(val, edmacc_regs_base[ctlr] + offset);
+ __raw_writel(val, cc->base + offset);
}
-static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
- unsigned or)
+static inline void edma_modify(struct edma *cc, int offset, unsigned and,
+ unsigned or)
{
- unsigned val = edma_read(ctlr, offset);
+ unsigned val = edma_read(cc, offset);
val &= and;
val |= or;
- edma_write(ctlr, offset, val);
+ edma_write(cc, offset, val);
}
-static inline void edma_and(unsigned ctlr, int offset, unsigned and)
+static inline void edma_and(struct edma *cc, int offset, unsigned and)
{
- unsigned val = edma_read(ctlr, offset);
+ unsigned val = edma_read(cc, offset);
val &= and;
- edma_write(ctlr, offset, val);
+ edma_write(cc, offset, val);
}
-static inline void edma_or(unsigned ctlr, int offset, unsigned or)
+static inline void edma_or(struct edma *cc, int offset, unsigned or)
{
- unsigned val = edma_read(ctlr, offset);
+ unsigned val = edma_read(cc, offset);
val |= or;
- edma_write(ctlr, offset, val);
+ edma_write(cc, offset, val);
}
-static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
+static inline unsigned int edma_read_array(struct edma *cc, int offset, int i)
{
- return edma_read(ctlr, offset + (i << 2));
+ return edma_read(cc, offset + (i << 2));
}
-static inline void edma_write_array(unsigned ctlr, int offset, int i,
+static inline void edma_write_array(struct edma *cc, int offset, int i,
unsigned val)
{
- edma_write(ctlr, offset + (i << 2), val);
+ edma_write(cc, offset + (i << 2), val);
}
-static inline void edma_modify_array(unsigned ctlr, int offset, int i,
+static inline void edma_modify_array(struct edma *cc, int offset, int i,
unsigned and, unsigned or)
{
- edma_modify(ctlr, offset + (i << 2), and, or);
+ edma_modify(cc, offset + (i << 2), and, or);
}
-static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
+static inline void edma_or_array(struct edma *cc, int offset, int i, unsigned or)
{
- edma_or(ctlr, offset + (i << 2), or);
+ edma_or(cc, offset + (i << 2), or);
}
-static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
+static inline void edma_or_array2(struct edma *cc, int offset, int i, int j,
unsigned or)
{
- edma_or(ctlr, offset + ((i*2 + j) << 2), or);
+ edma_or(cc, offset + ((i*2 + j) << 2), or);
}
-static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
+static inline void edma_write_array2(struct edma *cc, int offset, int i, int j,
unsigned val)
{
- edma_write(ctlr, offset + ((i*2 + j) << 2), val);
+ edma_write(cc, offset + ((i*2 + j) << 2), val);
}
-static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
+static inline unsigned int edma_shadow0_read(struct edma *cc, int offset)
{
- return edma_read(ctlr, EDMA_SHADOW0 + offset);
+ return edma_read(cc, EDMA_SHADOW0 + offset);
}
-static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
+static inline unsigned int edma_shadow0_read_array(struct edma *cc, int offset,
int i)
{
- return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
+ return edma_read(cc, EDMA_SHADOW0 + offset + (i << 2));
}
-static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
+static inline void edma_shadow0_write(struct edma *cc, int offset, unsigned val)
{
- edma_write(ctlr, EDMA_SHADOW0 + offset, val);
+ edma_write(cc, EDMA_SHADOW0 + offset, val);
}
-static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
+static inline void edma_shadow0_write_array(struct edma *cc, int offset, int i,
unsigned val)
{
- edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
+ edma_write(cc, EDMA_SHADOW0 + offset + (i << 2), val);
}
-static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
+static inline unsigned int edma_parm_read(struct edma *cc, int offset,
int param_no)
{
- return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
+ return edma_read(cc, EDMA_PARM + offset + (param_no << 5));
}
-static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
+static inline void edma_parm_write(struct edma *cc, int offset, int param_no,
unsigned val)
{
- edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
+ edma_write(cc, EDMA_PARM + offset + (param_no << 5), val);
}
-static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
+static inline void edma_parm_modify(struct edma *cc, int offset, int param_no,
unsigned and, unsigned or)
{
- edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
+ edma_modify(cc, EDMA_PARM + offset + (param_no << 5), and, or);
}
-static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
+static inline void edma_parm_and(struct edma *cc, int offset, int param_no,
unsigned and)
{
- edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
+ edma_and(cc, EDMA_PARM + offset + (param_no << 5), and);
}
-static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
+static inline void edma_parm_or(struct edma *cc, int offset, int param_no,
unsigned or)
{
- edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
+ edma_or(cc, EDMA_PARM + offset + (param_no << 5), or);
}
static inline void set_bits(int offset, int len, unsigned long *p)
@@ -231,41 +264,6 @@ static inline void clear_bits(int offset, int len, unsigned long *p)
}
/*****************************************************************************/
-
-/* actual number of DMA channels and slots on this silicon */
-struct edma {
- struct device *dev;
- /* how many dma resources of each type */
- unsigned num_channels;
- unsigned num_region;
- unsigned num_slots;
- unsigned num_tc;
- enum dma_event_q default_queue;
-
- /* list of channels with no even trigger; terminated by "-1" */
- const s8 *noevent;
-
- struct edma_soc_info *info;
- int id;
-
- /* The edma_inuse bit for each PaRAM slot is clear unless the
- * channel is in use ... by ARM or DSP, for QDMA, or whatever.
- */
- DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
-
- /* The edma_unused bit for each channel is clear unless
- * it is not being used on this platform. It uses a bit
- * of SOC-specific initialization code.
- */
- DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
-
- struct dma_interrupt_data {
- void (*callback)(unsigned channel, unsigned short ch_status,
- void *data);
- void *data;
- } intr_data[EDMA_MAX_DMACH];
-};
-
static struct edma *edma_cc[EDMA_MAX_CC];
static int arch_num_cc;
@@ -282,26 +280,25 @@ static const struct of_device_id edma_of_ids[] = {
/*****************************************************************************/
-static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
- enum dma_event_q queue_no)
+static void map_dmach_queue(struct edma *cc, unsigned ch_no,
+ enum dma_event_q queue_no)
{
int bit = (ch_no & 0x7) * 4;
/* default to low priority queue */
if (queue_no == EVENTQ_DEFAULT)
- queue_no = edma_cc[ctlr]->default_queue;
+ queue_no = cc->default_queue;
queue_no &= 7;
- edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
- ~(0x7 << bit), queue_no << bit);
+ edma_modify_array(cc, EDMA_DMAQNUM, (ch_no >> 3),
+ ~(0x7 << bit), queue_no << bit);
}
-static void assign_priority_to_queue(unsigned ctlr, int queue_no,
- int priority)
+static void assign_priority_to_queue(struct edma *cc, int queue_no,
+ int priority)
{
int bit = queue_no * 4;
- edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
- ((priority & 0x7) << bit));
+ edma_modify(cc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
}
/**
@@ -315,35 +312,30 @@ static void assign_priority_to_queue(unsigned ctlr, int queue_no,
* included in that particular EDMA variant (Eg : dm646x)
*
*/
-static void map_dmach_param(unsigned ctlr)
+static void map_dmach_param(struct edma *cc)
{
int i;
for (i = 0; i < EDMA_MAX_DMACH; i++)
- edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
+ edma_write_array(cc, EDMA_DCHMAP , i , (i << 5));
}
-static inline void
-setup_dma_interrupt(unsigned lch,
+static inline void setup_dma_interrupt(struct edma *cc, unsigned lch,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data)
{
- unsigned ctlr;
-
- ctlr = EDMA_CTLR(lch);
lch = EDMA_CHAN_SLOT(lch);
if (!callback)
- edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
- BIT(lch & 0x1f));
+ edma_shadow0_write_array(cc, SH_IECR, lch >> 5,
+ BIT(lch & 0x1f));
- edma_cc[ctlr]->intr_data[lch].callback = callback;
- edma_cc[ctlr]->intr_data[lch].data = data;
+ cc->intr_data[lch].callback = callback;
+ cc->intr_data[lch].data = data;
if (callback) {
- edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
- BIT(lch & 0x1f));
- edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
- BIT(lch & 0x1f));
+ edma_shadow0_write_array(cc, SH_ICR, lch >> 5, BIT(lch & 0x1f));
+ edma_shadow0_write_array(cc, SH_IESR, lch >> 5,
+ BIT(lch & 0x1f));
}
}
@@ -366,15 +358,15 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
dev_dbg(cc->dev, "dma_irq_handler\n");
- sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
+ sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 0);
if (!sh_ipr) {
- sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
+ sh_ipr = edma_shadow0_read_array(cc, SH_IPR, 1);
if (!sh_ipr)
return IRQ_NONE;
- sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
+ sh_ier = edma_shadow0_read_array(cc, SH_IER, 1);
bank = 1;
} else {
- sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
+ sh_ier = edma_shadow0_read_array(cc, SH_IER, 0);
bank = 0;
}
@@ -390,8 +382,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
if (sh_ier & BIT(slot)) {
channel = (bank << 5) | slot;
/* Clear the corresponding IPR bits */
- edma_shadow0_write_array(ctlr, SH_ICR, bank,
- BIT(slot));
+ edma_shadow0_write_array(cc, SH_ICR, bank, BIT(slot));
if (cc->intr_data[channel].callback)
cc->intr_data[channel].callback(
EDMA_CTLR_CHAN(ctlr, channel),
@@ -400,7 +391,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
}
} while (sh_ipr);
- edma_shadow0_write(ctlr, SH_IEVAL, 1);
+ edma_shadow0_write(cc, SH_IEVAL, 1);
return IRQ_HANDLED;
}
@@ -422,30 +413,30 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
dev_dbg(cc->dev, "dma_ccerr_handler\n");
- if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
- (edma_read(ctlr, EDMA_QEMR) == 0) &&
- (edma_read(ctlr, EDMA_CCERR) == 0))
+ if ((edma_read_array(cc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(cc, EDMA_EMR, 1) == 0) &&
+ (edma_read(cc, EDMA_QEMR) == 0) &&
+ (edma_read(cc, EDMA_CCERR) == 0))
return IRQ_NONE;
while (1) {
int j = -1;
- if (edma_read_array(ctlr, EDMA_EMR, 0))
+ if (edma_read_array(cc, EDMA_EMR, 0))
j = 0;
- else if (edma_read_array(ctlr, EDMA_EMR, 1))
+ else if (edma_read_array(cc, EDMA_EMR, 1))
j = 1;
if (j >= 0) {
dev_dbg(cc->dev, "EMR%d %08x\n", j,
- edma_read_array(ctlr, EDMA_EMR, j));
+ edma_read_array(cc, EDMA_EMR, j));
for (i = 0; i < 32; i++) {
int k = (j << 5) + i;
- if (edma_read_array(ctlr, EDMA_EMR, j) &
+ if (edma_read_array(cc, EDMA_EMR, j) &
BIT(i)) {
/* Clear the corresponding EMR bits */
- edma_write_array(ctlr, EDMA_EMCR, j,
- BIT(i));
+ edma_write_array(cc, EDMA_EMCR, j,
+ BIT(i));
/* Clear any SER */
- edma_shadow0_write_array(ctlr, SH_SECR,
+ edma_shadow0_write_array(cc, SH_SECR,
j, BIT(i));
if (cc->intr_data[k].callback) {
cc->intr_data[k].callback(
@@ -455,44 +446,44 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
}
}
}
- } else if (edma_read(ctlr, EDMA_QEMR)) {
+ } else if (edma_read(cc, EDMA_QEMR)) {
dev_dbg(cc->dev, "QEMR %02x\n",
- edma_read(ctlr, EDMA_QEMR));
+ edma_read(cc, EDMA_QEMR));
for (i = 0; i < 8; i++) {
- if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
+ if (edma_read(cc, EDMA_QEMR) & BIT(i)) {
/* Clear the corresponding IPR bits */
- edma_write(ctlr, EDMA_QEMCR, BIT(i));
- edma_shadow0_write(ctlr, SH_QSECR,
- BIT(i));
+ edma_write(cc, EDMA_QEMCR, BIT(i));
+ edma_shadow0_write(cc, SH_QSECR,
+ BIT(i));
/* NOTE: not reported!! */
}
}
- } else if (edma_read(ctlr, EDMA_CCERR)) {
+ } else if (edma_read(cc, EDMA_CCERR)) {
dev_dbg(cc->dev, "CCERR %08x\n",
- edma_read(ctlr, EDMA_CCERR));
+ edma_read(cc, EDMA_CCERR));
/* FIXME: CCERR.BIT(16) ignored! much better
* to just write CCERRCLR with CCERR value...
*/
for (i = 0; i < 8; i++) {
- if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
+ if (edma_read(cc, EDMA_CCERR) & BIT(i)) {
/* Clear the corresponding IPR bits */
- edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
+ edma_write(cc, EDMA_CCERRCLR, BIT(i));
/* NOTE: not reported!! */
}
}
}
- if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
- (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
- (edma_read(ctlr, EDMA_QEMR) == 0) &&
- (edma_read(ctlr, EDMA_CCERR) == 0))
+ if ((edma_read_array(cc, EDMA_EMR, 0) == 0) &&
+ (edma_read_array(cc, EDMA_EMR, 1) == 0) &&
+ (edma_read(cc, EDMA_QEMR) == 0) &&
+ (edma_read(cc, EDMA_CCERR) == 0))
break;
cnt++;
if (cnt > 10)
break;
}
- edma_write(ctlr, EDMA_EEVAL, 1);
+ edma_write(cc, EDMA_EEVAL, 1);
return IRQ_HANDLED;
}
@@ -629,18 +620,19 @@ int edma_alloc_channel(int channel,
}
/* ensure access through shadow region 0 */
- edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
+ edma_or_array2(edma_cc[ctlr], EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
/* ensure no events are pending */
edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ PARM_SIZE);
if (callback)
- setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
- callback, data);
+ setup_dma_interrupt(edma_cc[ctlr],
+ EDMA_CTLR_CHAN(ctlr, channel), callback,
+ data);
- map_dmach_queue(ctlr, channel, eventq_no);
+ map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
return EDMA_CTLR_CHAN(ctlr, channel);
}
@@ -668,11 +660,11 @@ void edma_free_channel(unsigned channel)
if (channel >= edma_cc[ctlr]->num_channels)
return;
- setup_dma_interrupt(channel, NULL, NULL);
+ setup_dma_interrupt(edma_cc[ctlr], channel, NULL, NULL);
/* REVISIT should probably take out of shadow region 0 */
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(channel), &dummy_paramset,
+ PARM_SIZE);
clear_bit(channel, edma_cc[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_channel);
@@ -716,8 +708,8 @@ int edma_alloc_slot(unsigned ctlr, int slot)
return -EBUSY;
}
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
+ PARM_SIZE);
return EDMA_CTLR_CHAN(ctlr, slot);
}
@@ -742,8 +734,8 @@ void edma_free_slot(unsigned slot)
slot >= edma_cc[ctlr]->num_slots)
return;
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), &dummy_paramset,
+ PARM_SIZE);
clear_bit(slot, edma_cc[ctlr]->edma_inuse);
}
EXPORT_SYMBOL(edma_free_slot);
@@ -768,7 +760,7 @@ dma_addr_t edma_get_position(unsigned slot, bool dst)
offs = PARM_OFFSET(slot);
offs += dst ? PARM_DST : PARM_SRC;
- return edma_read(ctlr, offs);
+ return edma_read(edma_cc[ctlr], offs);
}
/**
@@ -791,7 +783,7 @@ void edma_link(unsigned from, unsigned to)
return;
if (to >= edma_cc[ctlr_to]->num_slots)
return;
- edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
+ edma_parm_modify(edma_cc[ctlr_from], PARM_LINK_BCNTRLD, from, 0xffff0000,
PARM_OFFSET(to));
}
EXPORT_SYMBOL(edma_link);
@@ -819,8 +811,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
if (slot >= edma_cc[ctlr]->num_slots)
return;
- memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
- PARM_SIZE);
+ memcpy_toio(edma_cc[ctlr]->base + PARM_OFFSET(slot), param, PARM_SIZE);
}
EXPORT_SYMBOL(edma_write_slot);
@@ -841,8 +832,8 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
if (slot >= edma_cc[ctlr]->num_slots)
return;
- memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
- PARM_SIZE);
+ memcpy_fromio(param, edma_cc[ctlr]->base + PARM_OFFSET(slot),
+ PARM_SIZE);
}
EXPORT_SYMBOL(edma_read_slot);
@@ -867,7 +858,8 @@ void edma_pause(unsigned channel)
if (channel < edma_cc[ctlr]->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
+ edma_shadow0_write_array(edma_cc[ctlr], SH_EECR, channel >> 5,
+ mask);
}
}
EXPORT_SYMBOL(edma_pause);
@@ -888,7 +880,8 @@ void edma_resume(unsigned channel)
if (channel < edma_cc[ctlr]->num_channels) {
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
+ edma_shadow0_write_array(edma_cc[ctlr], SH_EESR, channel >> 5,
+ mask);
}
}
EXPORT_SYMBOL(edma_resume);
@@ -902,10 +895,11 @@ int edma_trigger_channel(unsigned channel)
channel = EDMA_CHAN_SLOT(channel);
mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
+ edma_shadow0_write_array(edma_cc[ctlr], SH_ESR, (channel >> 5), mask);
pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
- edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
+ edma_shadow0_read_array(edma_cc[ctlr], SH_ESR,
+ (channel >> 5)));
return 0;
}
EXPORT_SYMBOL(edma_trigger_channel);
@@ -929,28 +923,29 @@ int edma_start(unsigned channel)
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_cc[ctlr]->num_channels) {
+ struct edma *cc = edma_cc[ctlr];
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
/* EDMA channels without event association */
- if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
+ if (test_bit(channel, cc->edma_unused)) {
pr_debug("EDMA: ESR%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_ESR, j));
- edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
+ edma_shadow0_read_array(cc, SH_ESR, j));
+ edma_shadow0_write_array(cc, SH_ESR, j, mask);
return 0;
}
/* EDMA channel with event association */
pr_debug("EDMA: ER%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_ER, j));
+ edma_shadow0_read_array(cc, SH_ER, j));
/* Clear any pending event or error */
- edma_write_array(ctlr, EDMA_ECR, j, mask);
- edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ edma_write_array(cc, EDMA_ECR, j, mask);
+ edma_write_array(cc, EDMA_EMCR, j, mask);
/* Clear any SER */
- edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
+ edma_shadow0_write_array(cc, SH_SECR, j, mask);
+ edma_shadow0_write_array(cc, SH_EESR, j, mask);
pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_EER, j));
+ edma_shadow0_read_array(cc, SH_EER, j));
return 0;
}
@@ -975,19 +970,20 @@ void edma_stop(unsigned channel)
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_cc[ctlr]->num_channels) {
+ struct edma *cc = edma_cc[ctlr];
int j = channel >> 5;
unsigned int mask = BIT(channel & 0x1f);
- edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
- edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
- edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ edma_shadow0_write_array(cc, SH_EECR, j, mask);
+ edma_shadow0_write_array(cc, SH_ECR, j, mask);
+ edma_shadow0_write_array(cc, SH_SECR, j, mask);
+ edma_write_array(cc, EDMA_EMCR, j, mask);
/* clear possibly pending completion interrupt */
- edma_shadow0_write_array(ctlr, SH_ICR, j, mask);
+ edma_shadow0_write_array(cc, SH_ICR, j, mask);
pr_debug("EDMA: EER%d %08x\n", j,
- edma_shadow0_read_array(ctlr, SH_EER, j));
+ edma_shadow0_read_array(cc, SH_EER, j));
/* REVISIT: consider guarding against inappropriate event
* chaining by overwriting with dummy_paramset.
@@ -1017,17 +1013,18 @@ void edma_clean_channel(unsigned channel)
channel = EDMA_CHAN_SLOT(channel);
if (channel < edma_cc[ctlr]->num_channels) {
+ struct edma *cc = edma_cc[ctlr];
int j = (channel >> 5);
unsigned int mask = BIT(channel & 0x1f);
pr_debug("EDMA: EMR%d %08x\n", j,
- edma_read_array(ctlr, EDMA_EMR, j));
- edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
+ edma_read_array(cc, EDMA_EMR, j));
+ edma_shadow0_write_array(cc, SH_ECR, j, mask);
/* Clear the corresponding EMR bits */
- edma_write_array(ctlr, EDMA_EMCR, j, mask);
+ edma_write_array(cc, EDMA_EMCR, j, mask);
/* Clear any SER */
- edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
- edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
+ edma_shadow0_write_array(cc, SH_SECR, j, mask);
+ edma_write(cc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
}
}
EXPORT_SYMBOL(edma_clean_channel);
@@ -1056,7 +1053,7 @@ void edma_assign_channel_eventq(unsigned channel, enum dma_event_q eventq_no)
if (eventq_no >= edma_cc[ctlr]->num_tc)
return;
- map_dmach_queue(ctlr, channel, eventq_no);
+ map_dmach_queue(edma_cc[ctlr], channel, eventq_no);
}
EXPORT_SYMBOL(edma_assign_channel_eventq);
@@ -1068,7 +1065,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
s8 (*queue_priority_map)[2];
/* Decode the eDMA3 configuration from CCCFG register */
- cccfg = edma_read(cc_id, EDMA_CCCFG);
+ cccfg = edma_read(edma_cc, EDMA_CCCFG);
value = GET_NUM_REGN(cccfg);
edma_cc->num_region = BIT(value);
@@ -1281,10 +1278,6 @@ static int edma_probe(struct platform_device *pdev)
}
}
- edmacc_regs_base[dev_id] = devm_ioremap_resource(dev, mem);
- if (IS_ERR(edmacc_regs_base[dev_id]))
- return PTR_ERR(edmacc_regs_base[dev_id]);
-
edma_cc[dev_id] = devm_kzalloc(dev, sizeof(struct edma), GFP_KERNEL);
if (!edma_cc[dev_id])
return -ENOMEM;
@@ -1294,6 +1287,10 @@ static int edma_probe(struct platform_device *pdev)
cc->id = dev_id;
dev_set_drvdata(dev, cc);
+ cc->base = devm_ioremap_resource(dev, mem);
+ if (IS_ERR(cc->base))
+ return PTR_ERR(cc->base);
+
/* Get eDMA3 configuration from IP */
ret = edma_setup_from_hw(dev, info, cc, dev_id);
if (ret)
@@ -1301,11 +1298,9 @@ static int edma_probe(struct platform_device *pdev)
cc->default_queue = info->default_queue;
- dev_dbg(dev, "DMA REG BASE ADDR=%p\n", edmacc_regs_base[dev_id]);
-
for (i = 0; i < cc->num_slots; i++)
- memcpy_toio(edmacc_regs_base[dev_id] + PARM_OFFSET(i),
- &dummy_paramset, PARM_SIZE);
+ memcpy_toio(cc->base + PARM_OFFSET(i), &dummy_paramset,
+ PARM_SIZE);
/* Mark all channels as unused */
memset(cc->edma_unused, 0xff, sizeof(cc->edma_unused));
@@ -1374,23 +1369,23 @@ static int edma_probe(struct platform_device *pdev)
}
for (i = 0; i < cc->num_channels; i++)
- map_dmach_queue(dev_id, i, info->default_queue);
+ map_dmach_queue(cc, i, info->default_queue);
queue_priority_mapping = info->queue_priority_mapping;
/* Event queue priority mapping */
for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(dev_id, queue_priority_mapping[i][0],
+ assign_priority_to_queue(cc, queue_priority_mapping[i][0],
queue_priority_mapping[i][1]);
/* Map the channel to param entry if channel mapping logic exist */
- if (edma_read(dev_id, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(dev_id);
+ if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(cc);
for (i = 0; i < cc->num_region; i++) {
- edma_write_array2(dev_id, EDMA_DRAE, i, 0, 0x0);
- edma_write_array2(dev_id, EDMA_DRAE, i, 1, 0x0);
- edma_write_array(dev_id, EDMA_QRAE, i, 0x0);
+ edma_write_array2(cc, EDMA_DRAE, i, 0, 0x0);
+ edma_write_array2(cc, EDMA_DRAE, i, 1, 0x0);
+ edma_write_array(cc, EDMA_QRAE, i, 0x0);
}
cc->info = info;
arch_num_cc++;
@@ -1413,20 +1408,19 @@ static int edma_pm_resume(struct device *dev)
/* Event queue priority mapping */
for (i = 0; queue_priority_mapping[i][0] != -1; i++)
- assign_priority_to_queue(cc->id, queue_priority_mapping[i][0],
+ assign_priority_to_queue(cc, queue_priority_mapping[i][0],
queue_priority_mapping[i][1]);
/* Map the channel to param entry if channel mapping logic */
- if (edma_read(cc->id, EDMA_CCCFG) & CHMAP_EXIST)
- map_dmach_param(cc->id);
+ if (edma_read(cc, EDMA_CCCFG) & CHMAP_EXIST)
+ map_dmach_param(cc);
for (i = 0; i < cc->num_channels; i++) {
if (test_bit(i, cc->edma_inuse)) {
/* ensure access through shadow region 0 */
- edma_or_array2(cc->id, EDMA_DRAE, 0, i >> 5,
- BIT(i & 0x1f));
+ edma_or_array2(cc, EDMA_DRAE, 0, i >> 5, BIT(i & 0x1f));
- setup_dma_interrupt(EDMA_CTLR_CHAN(cc->id, i),
+ setup_dma_interrupt(cc, EDMA_CTLR_CHAN(cc->id, i),
cc->intr_data[i].callback,
cc->intr_data[i].data);
}
--
2.5.1
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Sekhar Nori <nsekhar@ti.com> |
|---|---|
| Date | 2015-09-12 13:30 +0200 |
| Message-ID | <q7Rah-7uC-7@gated-at.bofh.it> |
| In reply to | #1222789 |
On Friday 11 September 2015 05:56 PM, Peter Ujfalusi wrote: > Hi, > > Changes since v1: > - Convert edma platform device registration to use platform_device_register_full > - Moved the PM callback also to the dmaengine driver - missed in v1 > - Commit message added to: > ARM/dmaengine: edma: Remove limitation on the number of eDMA controllers > - New patch which reads the flag for the channel mapping support in one place > > Cover letter: > > with this series the edma two driver setup will be changed to have only one > driver to support eDMA3. The legacy edma interface will be removed and eDMA can > only be used via dmaengine API from this point on. > In order to do the merge the following improvements has been done: > - One driver instance per eDMA: > - Any number of eDMA instances are supported (both legacy and DT boot) > - Not relying on global variables, arrays, etc > - Code simplification and optimizations in several places > > This change will also help us to do bigger changes in the eDMA driver since, > since now we have only one driver to work with. > > The series has been tested on: > da850-evm (OMAP-L138) > - with legacy and DT boot (both eDMA0 and eDMA1 is enabled) > - In code swapping the eDMA instances in legacy mode to make sure the second > instance is handled correctly. > > am335x-evmsk > - DT boot > > I think this series could go via the dmaengine tree. Changes are trivial under > arch/arm/ I looked at the series, it looks pretty good. Thanks for getting it done! No problem with entire series going through dmaengine. The week after next, when I am back in office, I would like to test on DM365 as well. But really no need to wait for it if the series is ready otherwise. Thanks, Sekhar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Tony Lindgren <tony@atomide.com> |
|---|---|
| Date | 2015-09-14 18:20 +0200 |
| Subject | Re: [PATCH v2 11/23] ARM/dmaengine: edma: Merge the two drivers under drivers/dmaengine |
| Message-ID | <q8EE1-2St-9@gated-at.bofh.it> |
| In reply to | #1222789 |
* Peter Ujfalusi <peter.ujfalusi@ti.com> [150911 05:35]: > Move the code out from arch/arm/common and merge it inside of the dmaengine > driver. > This change is done with as minimal change to the code as possible to avoid > any possibilities to introducing regression. You should check your git config so it uses -M option to git diff to detect renames. Anyways, assuming you're just moving code, for the omap parts: Acked-by: Tony Lindgren <tony@atomide.com> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [next] | [standalone]
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Date | 2015-09-15 08:50 +0200 |
| Subject | Re: [PATCH v2 11/23] ARM/dmaengine: edma: Merge the two drivers under drivers/dmaengine |
| Message-ID | <q8SdY-5qT-21@gated-at.bofh.it> |
| In reply to | #1224290 |
On 09/14/2015 07:12 PM, Tony Lindgren wrote: > * Peter Ujfalusi <peter.ujfalusi@ti.com> [150911 05:35]: >> Move the code out from arch/arm/common and merge it inside of the dmaengine >> driver. >> This change is done with as minimal change to the code as possible to avoid >> any possibilities to introducing regression. > > You should check your git config so it uses -M option to git diff > to detect renames. I'm moving the code form arch/arm/common/edma.c inside of the already existing drivers/dma/edma.c The diff looks the same with -M or -C since during the code move most line needed to be changed (struct edma -> struct edma_cc). But the merge itself does not change how the code works at this point. > Anyways, assuming you're just moving code, for > the omap parts: > > Acked-by: Tony Lindgren <tony@atomide.com> Thanks, Péter -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web