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[PATCH 00/11] ARM: STi: STiH407: Pinctrl updates

Started byPeter Griffin <peter.griffin@linaro.org>
First post2015-09-11 19:10 +0200
Last post2015-09-14 14:40 +0200
Articles 10 — 3 participants

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Contents

  [PATCH 00/11] ARM: STi: STiH407: Pinctrl updates Peter Griffin <peter.griffin@linaro.org> - 2015-09-11 19:10 +0200
    [PATCH 07/11] ARM: DT: STiH407: Add systrace pin configuration Peter Griffin <peter.griffin@linaro.org> - 2015-09-11 19:10 +0200
      Re: [PATCH 07/11] ARM: DT: STiH407: Add systrace pin configuration Lee Jones <lee.jones@linaro.org> - 2015-09-11 20:10 +0200
    [PATCH 06/11] ARM: DT: STiH407: Add NAND flash controller pin configuration Peter Griffin <peter.griffin@linaro.org> - 2015-09-11 19:10 +0200
    [PATCH 01/11] ARM: STi: DT: STiH407: Add a cec0 pin definition Peter Griffin <peter.griffin@linaro.org> - 2015-09-11 19:10 +0200
      Re: [PATCH 01/11] ARM: STi: DT: STiH407: Add a cec0 pin definition Lee Jones <lee.jones@linaro.org> - 2015-09-11 20:10 +0200
    [PATCH 09/11] ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX Peter Griffin <peter.griffin@linaro.org> - 2015-09-11 19:10 +0200
      Re: [PATCH 09/11] ARM: DT: STiH407: Add pinconfig for IRB UHF and  IRB TX Lee Jones <lee.jones@linaro.org> - 2015-09-11 20:00 +0200
    [PATCH 03/11] ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs Peter Griffin <peter.griffin@linaro.org> - 2015-09-11 19:20 +0200
    Re: [PATCH 00/11] ARM: STi: STiH407: Pinctrl updates Patrice Chotard <patrice.chotard@st.com> - 2015-09-14 14:40 +0200

#1222983 — [PATCH 00/11] ARM: STi: STiH407: Pinctrl updates

FromPeter Griffin <peter.griffin@linaro.org>
Date2015-09-11 19:10 +0200
Subject[PATCH 00/11] ARM: STi: STiH407: Pinctrl updates
Message-ID<q7zZL-7Wu-3@gated-at.bofh.it>
Hi Maxime / Patrice / Srini,

This series makes a series of updates to the stih407 pinctrl groups
and makes the upstream kernel more closely aligned in terms of pin
configuration to the vendor kernel.

A number of new periphs are added such as spi fsm, nand, cec0, and
for others such as SPI the various alternate function pin muxings have
been added. Finally for SPI the controller nodes have been updated
to have the default pin assignment in the controller node.

kind regards,

Peter.

Peter Griffin (11):
  ARM: STi: DT: STiH407: Add a cec0 pin definition
  ARM: STi: DT: STiH407: Add i2c3 alternate pin configs
  ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs
  ARM: DT: STiH407: Add serial3 pinctrl configuration
  ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config
  ARM: DT: STiH407: Add NAND flash controller pin configuration
  ARM: DT: STiH407: Add systrace pin configuration
  ARM: DT: STiH407: Add SD pinctrl config for mmc0 controller
  ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX
  ARM: DT: STiH407: Add RMII pinctrl support
  ARM: STi: STiH407: Add spi default pinctrl groups.

 arch/arm/boot/dts/stih407-family.dtsi  |  14 ++
 arch/arm/boot/dts/stih407-pinctrl.dtsi | 378 ++++++++++++++++++++++++++++++++-
 2 files changed, 387 insertions(+), 5 deletions(-)

-- 
1.9.1

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#1222986 — [PATCH 07/11] ARM: DT: STiH407: Add systrace pin configuration

FromPeter Griffin <peter.griffin@linaro.org>
Date2015-09-11 19:10 +0200
Subject[PATCH 07/11] ARM: DT: STiH407: Add systrace pin configuration
Message-ID<q7zZM-7Wu-25@gated-at.bofh.it>
In reply to#1222983
This patch adds the pin config for systrace for
STiH407 family silicon.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/boot/dts/stih407-pinctrl.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index cde776b..798d901 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -658,6 +658,18 @@
 					};
 				};
 			};
+
+			systrace {
+				pinctrl_systrace_default: systrace-default {
+					st,pins {
+						trc_data0 = <&pio11 3 ALT5 OUT>;
+						trc_data1 = <&pio11 4 ALT5 OUT>;
+						trc_data2 = <&pio11 5 ALT5 OUT>;
+						trc_data3 = <&pio11 6 ALT5 OUT>;
+						trc_clk   = <&pio11 7 ALT5 OUT>;
+					};
+				};
+			};
 		};
 
 		pin-controller-front1 {
-- 
1.9.1

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#1223021 — Re: [PATCH 07/11] ARM: DT: STiH407: Add systrace pin configuration

FromLee Jones <lee.jones@linaro.org>
Date2015-09-11 20:10 +0200
SubjectRe: [PATCH 07/11] ARM: DT: STiH407: Add systrace pin configuration
Message-ID<q7AVR-Tz-45@gated-at.bofh.it>
In reply to#1222986
On Fri, 11 Sep 2015, Peter Griffin wrote:

> This patch adds the pin config for systrace for
> STiH407 family silicon.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  arch/arm/boot/dts/stih407-pinctrl.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)

Besides the SoBs, which are a little confusing:

Acked-by: Lee Jones <lee.jones@linaro.org>

> diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> index cde776b..798d901 100644
> --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> @@ -658,6 +658,18 @@
>  					};
>  				};
>  			};
> +
> +			systrace {
> +				pinctrl_systrace_default: systrace-default {
> +					st,pins {
> +						trc_data0 = <&pio11 3 ALT5 OUT>;
> +						trc_data1 = <&pio11 4 ALT5 OUT>;
> +						trc_data2 = <&pio11 5 ALT5 OUT>;
> +						trc_data3 = <&pio11 6 ALT5 OUT>;
> +						trc_clk   = <&pio11 7 ALT5 OUT>;
> +					};
> +				};
> +			};
>  		};
>  
>  		pin-controller-front1 {

-- 
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Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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#1222987 — [PATCH 06/11] ARM: DT: STiH407: Add NAND flash controller pin configuration

FromPeter Griffin <peter.griffin@linaro.org>
Date2015-09-11 19:10 +0200
Subject[PATCH 06/11] ARM: DT: STiH407: Add NAND flash controller pin configuration
Message-ID<q7zZN-7Wu-31@gated-at.bofh.it>
In reply to#1222983
This patch adds NAND flash support controller pin configuration
for STiH407 family silicon.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/boot/dts/stih407-pinctrl.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index d0f5fdd..cde776b 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -885,6 +885,29 @@
 					};
 				};
 			};
+
+			nand {
+				pinctrl_nand: nand {
+					st,pins {
+						nand_cs1 = <&pio40 6 ALT3 OUT>;
+						nand_cs0 = <&pio40 7 ALT3 OUT>;
+						nand_d0 = <&pio41 0 ALT3 BIDIR>;
+						nand_d1 = <&pio41 1 ALT3 BIDIR>;
+						nand_d2 = <&pio41 2 ALT3 BIDIR>;
+						nand_d3 = <&pio41 3 ALT3 BIDIR>;
+						nand_d4 = <&pio41 4 ALT3 BIDIR>;
+						nand_d5 = <&pio41 5 ALT3 BIDIR>;
+						nand_d6 = <&pio41 6 ALT3 BIDIR>;
+						nand_d7 = <&pio41 7 ALT3 BIDIR>;
+						nand_we = <&pio42 0 ALT3 OUT>;
+						nand_dqs = <&pio42 1 ALT3 OUT>;
+						nand_ale = <&pio42 2 ALT3 OUT>;
+						nand_cle = <&pio42 3 ALT3 OUT>;
+						nand_rnb = <&pio42 4 ALT3 IN>;
+						nand_oe = <&pio42 5 ALT3 OUT>;
+					};
+				};
+			};
 		};
 	};
 };
-- 
1.9.1

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#1222988 — [PATCH 01/11] ARM: STi: DT: STiH407: Add a cec0 pin definition

FromPeter Griffin <peter.griffin@linaro.org>
Date2015-09-11 19:10 +0200
Subject[PATCH 01/11] ARM: STi: DT: STiH407: Add a cec0 pin definition
Message-ID<q7zZN-7Wu-35@gated-at.bofh.it>
In reply to#1222983
This pin setup provides the correct configuration in order to
interact with the CEC HW.

Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
Signed-off-by: Nicolas Vanhaelewyn <nicolas.vanhaelewyn@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/boot/dts/stih407-pinctrl.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 0a754f2..d86ccc8 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -107,6 +107,14 @@
 				st,retime-pin-mask = <0x3f>;
 			};
 
+			cec0 {
+				pinctrl_cec0_default: cec0-default {
+					st,pins {
+						hdmi_cec = <&pio2 4 ALT1 BIDIR>;
+					};
+				};
+			};
+
 			rc {
 				pinctrl_ir: ir0 {
 					st,pins {
-- 
1.9.1

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#1223017 — Re: [PATCH 01/11] ARM: STi: DT: STiH407: Add a cec0 pin definition

FromLee Jones <lee.jones@linaro.org>
Date2015-09-11 20:10 +0200
SubjectRe: [PATCH 01/11] ARM: STi: DT: STiH407: Add a cec0 pin definition
Message-ID<q7AVP-Tz-17@gated-at.bofh.it>
In reply to#1222988
On Fri, 11 Sep 2015, Peter Griffin wrote:

> This pin setup provides the correct configuration in order to
> interact with the CEC HW.
> 
> Signed-off-by: Erwan Le Ray <erwan.leray@st.com>
> Signed-off-by: Nicolas Vanhaelewyn <nicolas.vanhaelewyn@st.com>
> Acked-by: Patrice Chotard <patrice.chotard@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Duplicate.

> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  arch/arm/boot/dts/stih407-pinctrl.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)

For the patch: Acked-by: Lee Jones <lee.jones@linaro.org>

> diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> index 0a754f2..d86ccc8 100644
> --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> @@ -107,6 +107,14 @@
>  				st,retime-pin-mask = <0x3f>;
>  			};
>  
> +			cec0 {
> +				pinctrl_cec0_default: cec0-default {
> +					st,pins {
> +						hdmi_cec = <&pio2 4 ALT1 BIDIR>;
> +					};
> +				};
> +			};
> +
>  			rc {
>  				pinctrl_ir: ir0 {
>  					st,pins {

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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#1222992 — [PATCH 09/11] ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX

FromPeter Griffin <peter.griffin@linaro.org>
Date2015-09-11 19:10 +0200
Subject[PATCH 09/11] ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX
Message-ID<q7zZO-7Wu-51@gated-at.bofh.it>
In reply to#1222983
This patch adds the pinconfig for IRB TX and IRB UHF.

Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/boot/dts/stih407-pinctrl.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 3cd7e2a..473f2ea 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -121,6 +121,24 @@
 						ir = <&pio4 0 ALT2 IN>;
 					};
 				};
+
+				pinctrl_uhf: uhf0 {
+					st,pins {
+						ir = <&pio4 1 ALT2 IN>;
+					};
+				};
+
+				pinctrl_tx: tx0 {
+					st,pins {
+						tx = <&pio4 2 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_tx_od: tx_od0 {
+					st,pins {
+						tx_od = <&pio4 3 ALT2 OUT>;
+					};
+				};
 			};
 
 			/* SBC_ASC0 - UART10 */
-- 
1.9.1

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#1223014 — Re: [PATCH 09/11] ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX

FromLee Jones <lee.jones@linaro.org>
Date2015-09-11 20:00 +0200
SubjectRe: [PATCH 09/11] ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX
Message-ID<q7AMb-sV-39@gated-at.bofh.it>
In reply to#1222992
On Fri, 11 Sep 2015, Peter Griffin wrote:

> This patch adds the pinconfig for IRB TX and IRB UHF.
> 
> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@st.com>
> Acked-by: Patrice Chotard <patrice.chotard@st.com>
> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

I'd take out the Ack here.

> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>  arch/arm/boot/dts/stih407-pinctrl.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> index 3cd7e2a..473f2ea 100644
> --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> @@ -121,6 +121,24 @@
>  						ir = <&pio4 0 ALT2 IN>;
>  					};
>  				};
> +
> +				pinctrl_uhf: uhf0 {
> +					st,pins {
> +						ir = <&pio4 1 ALT2 IN>;
> +					};
> +				};
> +
> +				pinctrl_tx: tx0 {
> +					st,pins {
> +						tx = <&pio4 2 ALT2 OUT>;
> +					};
> +				};
> +
> +				pinctrl_tx_od: tx_od0 {
> +					st,pins {
> +						tx_od = <&pio4 3 ALT2 OUT>;
> +					};
> +				};
>  			};
>  
>  			/* SBC_ASC0 - UART10 */

-- 
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Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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#1222998 — [PATCH 03/11] ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs

FromPeter Griffin <peter.griffin@linaro.org>
Date2015-09-11 19:20 +0200
Subject[PATCH 03/11] ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs
Message-ID<q7A9s-89P-19@gated-at.bofh.it>
In reply to#1222983
This patch adds the spi pinctrl configurations for all SPI
controllers, and also the alternate muxings which
can be used depending on board design.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/boot/dts/stih407-pinctrl.dtsi | 239 ++++++++++++++++++++++++++++++++-
 1 file changed, 235 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index ce219a1..bb3b0c7 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -262,6 +262,57 @@
 					};
 				};
 			};
+
+			spi10 {
+				pinctrl_spi10_default: spi10-4w-alt1-0 {
+					st,pins {
+						mtsr = <&pio4 6 ALT1 OUT>;
+						mrst = <&pio4 7 ALT1 IN>;
+						scl = <&pio4 5 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
+					st,pins {
+						mtsr = <&pio4 6 ALT1 BIDIR_PU>;
+						scl = <&pio4 5 ALT1 OUT>;
+					};
+				};
+			};
+
+			spi11 {
+				pinctrl_spi11_default: spi11-4w-alt2-0 {
+					st,pins {
+						mtsr = <&pio3 1 ALT2 OUT>;
+						mrst = <&pio3 0 ALT2 IN>;
+						scl = <&pio3 2 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
+					st,pins {
+						mtsr = <&pio3 1 ALT2 BIDIR_PU>;
+						scl = <&pio3 2 ALT2 OUT>;
+					};
+				};
+			};
+
+			spi12 {
+				pinctrl_spi12_default: spi12-4w-alt2-0 {
+					st,pins {
+						mtsr = <&pio3 6 ALT2 OUT>;
+						mrst = <&pio3 4 ALT2 IN>;
+						scl = <&pio3 7 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
+					st,pins {
+						mtsr = <&pio3 6 ALT2 BIDIR_PU>;
+						scl = <&pio3 7 ALT2 OUT>;
+					};
+				};
+			};
 		};
 
 		pin-controller-front0 {
@@ -451,11 +502,159 @@
 			};
 
 			spi0 {
-				pinctrl_spi0_default: spi0-default {
+				pinctrl_spi0_default: spi0-4w-alt2-0 {
+					st,pins {
+						mtsr = <&pio10 6 ALT2 OUT>;
+						mrst = <&pio10 7 ALT2 IN>;
+						scl = <&pio10 5 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
 					st,pins {
-						mtsr = <&pio12 6 ALT2 BIDIR>;
-						mrst = <&pio12 7 ALT2 BIDIR>;
-						scl = <&pio12 5 ALT2 BIDIR>;
+						mtsr = <&pio10 6 ALT2 BIDIR_PU>;
+						scl = <&pio10 5 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
+					st,pins {
+						mtsr = <&pio19 7 ALT1 OUT>;
+						mrst = <&pio19 5 ALT1 IN>;
+						scl = <&pio19 6 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
+					st,pins {
+						mtsr = <&pio19 7 ALT1 BIDIR_PU>;
+						scl = <&pio19 6 ALT1 OUT>;
+					};
+				};
+			};
+
+			spi1 {
+				pinctrl_spi1_default: spi1-4w-alt2-0 {
+					st,pins {
+						mtsr = <&pio11 1 ALT2 OUT>;
+						mrst = <&pio11 2 ALT2 IN>;
+						scl = <&pio11 0 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
+					st,pins {
+						mtsr = <&pio11 1 ALT2 BIDIR_PU>;
+						scl = <&pio11 0 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
+					st,pins {
+						mtsr = <&pio14 3 ALT1 OUT>;
+						mrst = <&pio14 4 ALT1 IN>;
+						scl = <&pio14 2 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
+					st,pins {
+						mtsr = <&pio14 3 ALT1 BIDIR_PU>;
+						scl = <&pio14 2 ALT1 OUT>;
+					};
+				};
+			};
+
+			spi2 {
+				pinctrl_spi2_default: spi2-4w-alt2-0 {
+					st,pins {
+						mtsr = <&pio12 6 ALT2 OUT>;
+						mrst = <&pio12 7 ALT2 IN>;
+						scl = <&pio12 5 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
+					st,pins {
+						mtsr = <&pio12 6 ALT2 BIDIR_PU>;
+						scl = <&pio12 5 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
+					st,pins {
+						mtsr = <&pio14 6 ALT1 OUT>;
+						mrst = <&pio14 7 ALT1 IN>;
+						scl = <&pio14 5 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
+					st,pins {
+						mtsr = <&pio14 6 ALT1 BIDIR_PU>;
+						scl = <&pio14 5 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
+					st,pins {
+						mtsr = <&pio15 6 ALT2 OUT>;
+						mrst = <&pio15 7 ALT2 IN>;
+						scl = <&pio15 5 ALT2 OUT>;
+					};
+				};
+
+				pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
+					st,pins {
+						mtsr = <&pio15 6 ALT2 BIDIR_PU>;
+						scl = <&pio15 5 ALT2 OUT>;
+					};
+				};
+			};
+
+			spi3 {
+				pinctrl_spi3_default: spi3-4w-alt3-0 {
+					st,pins {
+						mtsr = <&pio13 6 ALT3 OUT>;
+						mrst = <&pio13 7 ALT3 IN>;
+						scl = <&pio13 5 ALT3 OUT>;
+					};
+				};
+
+				pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
+					st,pins {
+						mtsr = <&pio13 6 ALT3 BIDIR_PU>;
+						scl = <&pio13 5 ALT3 OUT>;
+					};
+				};
+
+				pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
+					st,pins {
+						mtsr = <&pio17 7 ALT1 OUT>;
+						mrst = <&pio17 5 ALT1 IN>;
+						scl = <&pio17 6 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
+					st,pins {
+						mtsr = <&pio17 7 ALT1 BIDIR_PU>;
+						scl = <&pio17 6 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
+					st,pins {
+						mtsr = <&pio18 6 ALT1 OUT>;
+						mrst = <&pio18 7 ALT1 IN>;
+						scl = <&pio18 5 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
+					st,pins {
+						mtsr = <&pio18 6 ALT1 BIDIR_PU>;
+						scl = <&pio18 5 ALT1 OUT>;
 					};
 				};
 			};
@@ -578,6 +777,38 @@
 					};
 				};
 			};
+
+			spi4 {
+				pinctrl_spi4_default: spi4-4w-alt1-0 {
+					st,pins {
+						mtsr = <&pio30 1 ALT1 OUT>;
+						mrst = <&pio30 2 ALT1 IN>;
+						scl = <&pio30 0 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
+					st,pins {
+						mtsr = <&pio30 1 ALT1 BIDIR_PU>;
+						scl = <&pio30 0 ALT1 OUT>;
+					};
+				};
+
+				pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
+					st,pins {
+						mtsr = <&pio34 1 ALT3 OUT>;
+						mrst = <&pio34 2 ALT3 IN>;
+						scl = <&pio34 0 ALT3 OUT>;
+					};
+				};
+
+				pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
+					st,pins {
+						mtsr = <&pio34 1 ALT3 BIDIR_PU>;
+						scl = <&pio34 0 ALT3 OUT>;
+					};
+				};
+			};
 		};
 
 		pin-controller-flash {
-- 
1.9.1

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#1224096

FromPatrice Chotard <patrice.chotard@st.com>
Date2015-09-14 14:40 +0200
Message-ID<q8Bd8-6hL-11@gated-at.bofh.it>
In reply to#1222983
Hi Peter

As already pointed by Lee, my signed-off needs to be removed from 
several patches
The overall series seems ok.

You can add my Acked-by

Thanks

On 09/11/2015 07:06 PM, Peter Griffin wrote:
> Hi Maxime / Patrice / Srini,
>
> This series makes a series of updates to the stih407 pinctrl groups
> and makes the upstream kernel more closely aligned in terms of pin
> configuration to the vendor kernel.
>
> A number of new periphs are added such as spi fsm, nand, cec0, and
> for others such as SPI the various alternate function pin muxings have
> been added. Finally for SPI the controller nodes have been updated
> to have the default pin assignment in the controller node.
>
> kind regards,
>
> Peter.
>
> Peter Griffin (11):
>    ARM: STi: DT: STiH407: Add a cec0 pin definition
>    ARM: STi: DT: STiH407: Add i2c3 alternate pin configs
>    ARM: DT: STiH407: Add SPI 3 wire and 4 wire pinctrl configs
>    ARM: DT: STiH407: Add serial3 pinctrl configuration
>    ARM: DT: STiH407: Add SPI FSM (NOR Flash) Controller pin config
>    ARM: DT: STiH407: Add NAND flash controller pin configuration
>    ARM: DT: STiH407: Add systrace pin configuration
>    ARM: DT: STiH407: Add SD pinctrl config for mmc0 controller
>    ARM: DT: STiH407: Add pinconfig for IRB UHF and IRB TX
>    ARM: DT: STiH407: Add RMII pinctrl support
>    ARM: STi: STiH407: Add spi default pinctrl groups.
>
>   arch/arm/boot/dts/stih407-family.dtsi  |  14 ++
>   arch/arm/boot/dts/stih407-pinctrl.dtsi | 378 ++++++++++++++++++++++++++++++++-
>   2 files changed, 387 insertions(+), 5 deletions(-)
>

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