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[PATCH] perf/x86/intel/pt: Export cpu frequency ratios needed by PT decoders

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  [PATCH] perf/x86/intel/pt: Export cpu frequency ratios needed by PT decoders Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2015-08-27 17:10 +0200
    Re: [PATCH] perf/x86/intel/pt: Export cpu frequency ratios needed by PT decoders Andi Kleen <andi@firstfloor.org> - 2015-08-28 21:40 +0200
      Re: [PATCH] perf/x86/intel/pt: Export cpu frequency ratios needed by PT decoders Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2015-08-31 15:00 +0200
        Re: [PATCH] perf/x86/intel/pt: Export cpu frequency ratios needed by  PT decoders Andi Kleen <andi@firstfloor.org> - 2015-08-31 22:10 +0200

#1214635 — [PATCH] perf/x86/intel/pt: Export cpu frequency ratios needed by PT decoders

In order for Intel PT decoders to infer correct crystal clock and bus
frequencies that are required to correctly decode timing information
from a PT stream (MTC and CBR packets), export them as sysfs attributes:

  * max_nonturbo_ratio: ratio between the invariant TSC and base clock;
  * tsc_art_ratio: TSC to core crystal clock ratio.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel_pt.c | 40 +++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_pt.c b/arch/x86/kernel/cpu/perf_event_intel_pt.c
index c534261068..e76aa5a30c 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_pt.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_pt.c
@@ -126,9 +126,49 @@ static struct attribute_group pt_format_group = {
 	.attrs	= pt_formats_attr,
 };
 
+static ssize_t
+pt_timing_attr_show(struct device *dev, struct device_attribute *attr,
+		    char *page)
+{
+	struct perf_pmu_events_attr *pmu_attr =
+		container_of(attr, struct perf_pmu_events_attr, attr);
+	u32 eax, ebx, ecx, edx;
+	unsigned long val;
+
+	switch (pmu_attr->id) {
+	case 0:
+		rdmsrl(MSR_PLATFORM_INFO, val);
+		val = (val & 0xff00) >> 8;
+		return sprintf(page, "%lu\n", val);
+	case 1:
+		cpuid(0x15, &eax, &ebx, &ecx, &edx);
+		return sprintf(page, "%u:%u\n", ebx, eax);
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+PMU_EVENT_ATTR(max_nonturbo_ratio, timing_attr_max_nonturbo_ratio, 0,
+	       pt_timing_attr_show);
+PMU_EVENT_ATTR(tsc_art_ratio, timing_attr_tsc_art_ratio, 1,
+	       pt_timing_attr_show);
+
+static struct attribute *pt_timing_attr[] = {
+	&timing_attr_max_nonturbo_ratio.attr.attr,
+	&timing_attr_tsc_art_ratio.attr.attr,
+	NULL,
+};
+
+static struct attribute_group pt_timing_group = {
+	.attrs	= pt_timing_attr,
+};
+
 static const struct attribute_group *pt_attr_groups[] = {
 	&pt_cap_group,
 	&pt_format_group,
+	&pt_timing_group,
 	NULL,
 };
 
-- 
2.5.0

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#1215532

Alexander Shishkin <alexander.shishkin@linux.intel.com> writes:
> +		return sprintf(page, "%lu\n", val);
> +	case 1:
> +		cpuid(0x15, &eax, &ebx, &ecx, &edx);

Surely this needs to be protected by a cpuid level check?
Broadwell for once doesn't have CPUID 0x15.

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only
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#1216168

Andi Kleen <andi@firstfloor.org> writes:

> Alexander Shishkin <alexander.shishkin@linux.intel.com> writes:
>> +		return sprintf(page, "%lu\n", val);
>> +	case 1:
>> +		cpuid(0x15, &eax, &ebx, &ecx, &edx);
>
> Surely this needs to be protected by a cpuid level check?
> Broadwell for once doesn't have CPUID 0x15.

I couldn't find where this is explicitly said in the SDM. However, the
leaf description says that CPUID.0x15.EBX[31:0]==0 means that the ratio
is not enumerated. I don't see how to better communicate this to
userspace though than to simply have 0 there.

Regards,
--
Alex
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#1216413 — Re: [PATCH] perf/x86/intel/pt: Export cpu frequency ratios needed by PT decoders

On Mon, Aug 31, 2015 at 03:59:08PM +0300, Alexander Shishkin wrote:
> Andi Kleen <andi@firstfloor.org> writes:
> 
> > Alexander Shishkin <alexander.shishkin@linux.intel.com> writes:
> >> +		return sprintf(page, "%lu\n", val);
> >> +	case 1:
> >> +		cpuid(0x15, &eax, &ebx, &ecx, &edx);
> >
> > Surely this needs to be protected by a cpuid level check?
> > Broadwell for once doesn't have CPUID 0x15.
> 
> I couldn't find where this is explicitly said in the SDM. However, the
> leaf description says that CPUID.0x15.EBX[31:0]==0 means that the ratio
> is not enumerated. I don't see how to better communicate this to
> userspace though than to simply have 0 there.

What I meant is -- the kernel may crash on a older CPU that does
not support CPUID 0x15. For example Broadwell doesn't have it.
For CPUID you always need to check the level.

-Andi
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