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[PATCH v2 0/2] staging: rtl8723au: core: endianness issues

Started byDavid Decotigny <ddecotig@gmail.com>
First post2015-06-08 02:50 +0200
Last post2015-06-08 02:50 +0200
Articles 2 — 1 participant

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  [PATCH v2 0/2] staging: rtl8723au: core: endianness issues David Decotigny <ddecotig@gmail.com> - 2015-06-08 02:50 +0200
    [PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion David Decotigny <ddecotig@gmail.com> - 2015-06-08 02:50 +0200

#1160192 — [PATCH v2 0/2] staging: rtl8723au: core: endianness issues

FromDavid Decotigny <ddecotig@gmail.com>
Date2015-06-08 02:50 +0200
Subject[PATCH v2 0/2] staging: rtl8723au: core: endianness issues
Message-ID<pyTqi-7sH-3@gated-at.bofh.it>
The code shows a couple inconsistencies (described in commit
descriptions) which would not be an issue on little-endian cpus, but
could cause breakage on non-LE cpus. Note: I could not test on real
hardware, these patches created based on sparse reports.

Hostory:
  - resending the same patches to correct recipients, only changed
    commit descriptions (credits to Dan Carpenter)

############################################
# Patch Set Summary:

David Decotigny (2):
  staging: rtl8723au: core: avoid bitwise arithmetic with forced
    endianness
  staging: rtl8723au: core: remove redundant endianness conversion

 drivers/staging/rtl8723au/core/rtw_mlme_ext.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

-- 
2.2.0.rc0.207.ga3a616c

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#1160193 — [PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion

FromDavid Decotigny <ddecotig@gmail.com>
Date2015-06-08 02:50 +0200
Subject[PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion
Message-ID<pyTqi-7sH-5@gated-at.bofh.it>
In reply to#1160192
Source and destination have the same little-endian annotation: this
patch removes incorrect byte-swap on non-LE cpus.

This addresses the following sparse warning:
drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56: warning: incorrect type in argument 1 (different base types)
drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56:    expected unsigned short [unsigned] [usertype] val
drivers/staging/rtl8723au/core/rtw_mlme_ext.c:3911:56:    got restricted __le16 [usertype] BA_timeout_value

Signed-off-by: David Decotigny <ddecotig@gmail.com>
---
 drivers/staging/rtl8723au/core/rtw_mlme_ext.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/rtl8723au/core/rtw_mlme_ext.c b/drivers/staging/rtl8723au/core/rtw_mlme_ext.c
index 7c3b5dd..142f214 100644
--- a/drivers/staging/rtl8723au/core/rtw_mlme_ext.c
+++ b/drivers/staging/rtl8723au/core/rtw_mlme_ext.c
@@ -3906,8 +3906,8 @@ void issue_action_BA23a(struct rtw_adapter *padapter,
 		put_unaligned_le16(BA_para_set,
 				   &mgmt->u.action.u.addba_resp.capab);
 
-		put_unaligned_le16(pmlmeinfo->ADDBA_req.BA_timeout_value,
-				   &mgmt->u.action.u.addba_resp.timeout);
+		mgmt->u.action.u.addba_resp.timeout
+			= pmlmeinfo->ADDBA_req.BA_timeout_value;
 
 		pattrib->pktlen += 8;
 		break;
-- 
2.2.0.rc0.207.ga3a616c

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