[PATCH v2 0/2] staging: rtl8723au: core: endianness issues

From	David Decotigny <ddecotig@gmail.com>
Newsgroups	linux.kernel
Subject	[PATCH v2 0/2] staging: rtl8723au: core: endianness issues
Date	2015-06-08 02:50 +0200
Message-ID	<pyTqi-7sH-3@gated-at.bofh.it> (permalink)
Organization	linux.* mail to news gateway

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The code shows a couple inconsistencies (described in commit
descriptions) which would not be an issue on little-endian cpus, but
could cause breakage on non-LE cpus. Note: I could not test on real
hardware, these patches created based on sparse reports.

Hostory:
  - resending the same patches to correct recipients, only changed
    commit descriptions (credits to Dan Carpenter)

############################################
# Patch Set Summary:

David Decotigny (2):
  staging: rtl8723au: core: avoid bitwise arithmetic with forced
    endianness
  staging: rtl8723au: core: remove redundant endianness conversion

 drivers/staging/rtl8723au/core/rtw_mlme_ext.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

-- 
2.2.0.rc0.207.ga3a616c

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[PATCH v2 0/2] staging: rtl8723au: core: endianness issues David Decotigny <ddecotig@gmail.com> - 2015-06-08 02:50 +0200
  [PATCH v2 2/2] staging: rtl8723au: core: remove redundant endianness conversion David Decotigny <ddecotig@gmail.com> - 2015-06-08 02:50 +0200

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