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[PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain

Started byGeert Uytterhoeven <geert+renesas@glider.be>
First post2015-08-04 14:40 +0200
Last post2015-08-06 03:00 +0200
Articles 12 — 3 participants

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  [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain Geert Uytterhoeven <geert+renesas@glider.be> - 2015-08-04 14:40 +0200
    [PATCH v4 11/16] ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain Geert Uytterhoeven <geert+renesas@glider.be> - 2015-08-04 14:40 +0200
    [PATCH v4 01/16] clk: shmobile: Add CPG/MSTP Clock Domain support Geert Uytterhoeven <geert+renesas@glider.be> - 2015-08-04 14:40 +0200
    [PATCH v4 12/16] ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain Geert Uytterhoeven <geert+renesas@glider.be> - 2015-08-04 14:40 +0200
    [PATCH v4 06/16] ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain Geert Uytterhoeven <geert+renesas@glider.be> - 2015-08-04 14:40 +0200
    [PATCH v4 16/16] ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers Geert Uytterhoeven <geert+renesas@glider.be> - 2015-08-04 14:40 +0200
    [PATCH v4 02/16] clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support Geert Uytterhoeven <geert+renesas@glider.be> - 2015-08-04 14:40 +0200
    [PATCH v4 07/16] ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain Geert Uytterhoeven <geert+renesas@glider.be> - 2015-08-04 14:40 +0200
    Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain Simon Horman <horms@verge.net.au> - 2015-08-04 15:50 +0200
      Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain Simon Horman <horms@verge.net.au> - 2015-08-05 03:00 +0200
        Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain Geert Uytterhoeven <geert@linux-m68k.org> - 2015-08-05 09:00 +0200
          Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain Simon Horman <horms@verge.net.au> - 2015-08-06 03:00 +0200

#1199782 — [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain

FromGeert Uytterhoeven <geert+renesas@glider.be>
Date2015-08-04 14:40 +0200
Subject[PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
Message-ID<pTJvX-1ZY-7@gated-at.bofh.it>
	Hi all,

This patch series adds Clock Domain support to the Clock Pulse Generator
(CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain, to
be used on shmobile SoCs without device power domains (R-Car Gen1 and
Gen2, RZ).  This allows to power-manage the module clocks of SoC devices
that are part of the CPG/MSTP Clock Domain using Runtime PM, or for
system suspend/resume, similar to SoCs with device power domains
(SH-Mobile and R-Mobile).

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock are tagged in DT with a proper
"power-domains" property, also serving as a visual clue. This applies to
most on-SoC devices, which have a one-to-one mapping from SoC device to
DT device node.  Notable exceptions are "display" and "sound" device
nodes, which represent multiple SoC devices, each having their own MSTP
clocks. Hence drivers for such devices still have to manage their
(multiple module) clocks themselves.

The (MSTP) clock to use for power-management is found by scanning for
clocks that are compatible with "renesas,cpg-mstp-clocks".
In V1, the "first" clock tied to each device (con_id NULL) was used,
being a bit ad-hoc. It was suggested to use the "fck" clock instead,
but this may conflict with DT bindings for devices we don't control
(e.g. GIC-400 plans to mandate "clk" for the clk-name of its single
clock). Looking for real MSTP clocks avoids this problem.

Logically, the CPG/MSTP Clock Domain operates on the SoC CPG/MSTP block.
As there's no single device node in DT representing this block (there
are separate device nodes for the CPG and for the individual MSTP
clocks), I bound the logic to the CPG device node.  Perhaps this is
something we should change for future SoCs?

Finally, the legacy default PM domain hack in drivers/sh/pm_runtime.c
is no longer needed when running an ARM multi-platform kernel on an
shmobile SoC with genpd support. Please note that this hack is still
needed for legacy (SH/ARM) platforms, and for the CONFIG_PM=n case.
Perhaps we should unconditionally enable PM when building shmobile
multi-platform kernels?

Compared to the legacy default PM domain hack, the CPG/MSTP Clock Domain
has several advantages:
  - It only affects on-SoC devices, not all platform devices,
  - It only affects the on-SoC devices we want, as specified in DT,
  - Allmost all module clocks of all on-SoC devices (barring devices
    needed for wake-up) are now gated during s2ram, saving more power.

By adding a small quirk to the CPG/MSTP Clock Domain code, its functions
to attach/detach devices to a PM Domain can be reused by the pm-rmobile
driver, reducing code duplication.

Here's a list of all devices in the CPG/MSTP Clock Domain on r8a7791:

root@koelsch:~# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
    domain                      status         slaves
           /device                                      runtime status
----------------------------------------------------------------------
cpg_clocks                      on               
    /devices/platform/e61c0000.interrupt-controller     active
    /devices/platform/e60b0000.i2c                      suspended
    /devices/platform/ffca0000.timer                    suspended
    /devices/platform/e6590100.usb-phy                  unsupported
    /devices/platform/e6050000.gpio                     active
    /devices/platform/e6051000.gpio                     active
    /devices/platform/e6052000.gpio                     active
    /devices/platform/e6053000.gpio                     active
    /devices/platform/e6054000.gpio                     active
    /devices/platform/e6055000.gpio                     active
    /devices/platform/e6055400.gpio                     active
    /devices/platform/e6055800.gpio                     active
    /devices/platform/ee090000.pci                      active
    /devices/platform/ee0d0000.pci                      active
    /devices/platform/fe000000.pcie                     unsupported
    /devices/platform/e6700000.dma-controller           active
    /devices/platform/e6720000.dma-controller           active
    /devices/platform/ec700000.dma-controller           active
    /devices/platform/ec720000.dma-controller           suspended
    /devices/platform/e65a0000.dma-controller           suspended
    /devices/platform/e65b0000.dma-controller           suspended
    /devices/platform/e6e60000.serial                   active
    /devices/platform/e6e68000.serial                   active
    /devices/platform/ee300000.sata                     unsupported
    /devices/platform/e6b10000.spi                      suspended
    /devices/platform/e6e20000.spi                      suspended
    /devices/platform/ee700000.ethernet                 active
    /devices/platform/e6530000.i2c                      suspended
    /devices/platform/e6ef1000.video                    suspended
    /devices/platform/e61f0000.thermal                  active
    /devices/platform/ee100000.sd                       active
    /devices/platform/ee140000.sd                       active
    /devices/platform/ee160000.sd                       active
root@koelsch:~# 

Patch overview:
  - Patch 1 adds the core CPG/MSTP Clock Domain code to the CPG MSTP
    driver,
  - Patches 2-5 adds CPG/MSTP Clock Domain driver support for all
    Renesas SoCs that have MSTP clocks, but no device power domains, and
    updates the DT binding documentation accordingly,
  - Patches 6-12 add CPG/MSTP Clock Domains to the dtsi files,
  - Patches 13 and 14 disable the legacy default PM domain hack on all
    ARM multi-platform builds with genpd support, now it's no longer
    needed nor wanted,
  - Patch 15 adds a quirk for r8a73a4 and sh73a0, where the Bus State
    Controller is not power-managed by an MSTP clock, but by a plain
    CPG clock,
  - Patch 16 makes the R-Mobile PM Domain driver use the CPG/MSTP Clock
    Domain attach/detach helpers, as they're more future-proof, and to
    reduce code duplication.

Changes compared to v3 ("[PATCH v3 00/16] ARM: shmobile: Add CPG/MSTP
Clock Domain", https://lkml.org/lkml/2015/7/1/408):
  - clk-mstp.c needs to #include <linux/clk.h> due to recent
    <linux/clk*.h> shuffling,
  - Add "power-domains" properties to recently introduced device nodes
    (jpu, mmcif0),
  - Consistently add "power-domains" properties after clock and dma
    properties,
  - Add Reviewed-by,

Changes compared to v2 ("[PATCH v2 00/14] ARM: shmobile: Add CPG Clock
Domains", https://lkml.org/lkml/2015/5/28/590):
  - Add Acked-by,
  - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
  - Drop bogus addition of #includes to clk-rcar-gen2.c,
  - Call pm_clk_destroy() from cpg_mstp_detach_dev() only if
    cpg_mstp_attach_dev() actually added a clock,
  - Add "power-domains" property to recently introduced Ethernet AVB
    device node,
  - Add CPG/MSTP Clock Domain to recently introduced r8a7793 SoC,
  - The legacy default PM Domain runtime check must stay for the ARM
    multiplatform CONFIG_PM=n case, to prevent the code from running on
    non-shmobile machines,
  - Provide backwards-compatibility with old DTs (mainly for R-Car
    Gen2),
  - Extract EMMA Mobile EV2 removal into a separate patch,
  - Replace explicit platform checks in the legacy default PM Domain
    code by a check for the presence of MSTP clocks,
  - Drop references to legacy r8a7740/sh73a0, which are gone.

Changes compared to v1 ("[PATCH/RFC 0/5] ARM: shmobile: rcar-gen2: Add
CPG Clock Domain",
https://www.marc.info/?l=linux-pm&m=142670805530085&w=3):
  - Add Acked-by and Reviewed-by.
  - Move core CPG Clock Domain code from the R-Car Gen2 driver to the
    CPG MSTP Clocks driver, as it's generic, and can be used on other
    Renesas SoCs that have a CPG/MSTP block,
  - Scan for an MSTP clock instead of using the first clock tied to the
    device (con_id NULL),
  - Add support for R-Car Gen1 and RZ, in addition to R-Car Gen2,
    allowing to drop the legacy default PM domain hack completely in
    multi-platform builds,
  - Reuse the CPG Clock Domain attach/detach helpers for pm-rmobile.
More detailed change logs are available in the individual patches.

Dependencies:
  - This series is against renesas-devel-20150803-v4.2-rc5 (not
    renesas-drivers-2015-08-04-v4.2-rc5, as that tree has more changes
    to the .dtsi files),
  - As usual when involving clocks and/or PM Domains, there are stringent
    dependencies between the (subsets of) patches:
      - Patches 2-5 depend on patch 1,
      - Patches 6-12 depend on patches 2-5,
      - Patch 14 depends on patches 6-13,
      - Patch 15 depends on patch 1 only,
      - Patch 16 depends on patch 15.

All of this was tested on:
  - r8a73a4/ape6evm,
  - r8a7740/armadillo,
  - r8a7791/koelsch (with and without CONFIG_PM),
  - sh73a0/kzm9g.

Testing on other shmobile platforms (esp. R-Car Gen1 and RZ) would be
appreciated.

I think this series goes best in through Simon's shmobile tree.

Thanks for applying!

Geert Uytterhoeven (16):
  clk: shmobile: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
  clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
  clk: shmobile: rz: Add CPG/MSTP Clock Domain support
  ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
  drivers: sh: Disable legacy default PM Domain on emev2
  drivers: sh: Disable PM runtime for multi-platform ARM with genpd
  clk: shmobile: mstp: Consider "zb_clk" suitable for power management
  ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach
    helpers

 .../bindings/clock/renesas,r8a7778-cpg-clocks.txt  | 29 ++++++-
 .../bindings/clock/renesas,r8a7779-cpg-clocks.txt  | 30 ++++++-
 .../clock/renesas,rcar-gen2-cpg-clocks.txt         | 26 ++++++-
 .../bindings/clock/renesas,rz-cpg-clocks.txt       | 29 ++++++-
 arch/arm/boot/dts/r7s72100.dtsi                    | 19 +++++
 arch/arm/boot/dts/r8a7778.dtsi                     | 22 ++++++
 arch/arm/boot/dts/r8a7779.dtsi                     | 23 ++++++
 arch/arm/boot/dts/r8a7790.dtsi                     | 86 +++++++++++++++++---
 arch/arm/boot/dts/r8a7791.dtsi                     | 88 +++++++++++++++++++--
 arch/arm/boot/dts/r8a7793.dtsi                     |  7 ++
 arch/arm/boot/dts/r8a7794.dtsi                     | 29 +++++++
 arch/arm/mach-shmobile/Kconfig                     |  2 +
 arch/arm/mach-shmobile/pm-rmobile.c                | 35 +--------
 drivers/clk/shmobile/clk-mstp.c                    | 91 ++++++++++++++++++++++
 drivers/clk/shmobile/clk-r8a7778.c                 |  2 +
 drivers/clk/shmobile/clk-r8a7779.c                 |  2 +
 drivers/clk/shmobile/clk-rcar-gen2.c               |  2 +
 drivers/clk/shmobile/clk-rz.c                      |  3 +
 drivers/sh/pm_runtime.c                            | 19 ++---
 include/linux/clk/shmobile.h                       | 12 +++
 20 files changed, 482 insertions(+), 74 deletions(-)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds
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#1199783 — [PATCH v4 11/16] ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain

FromGeert Uytterhoeven <geert+renesas@glider.be>
Date2015-08-04 14:40 +0200
Subject[PATCH v4 11/16] ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
Message-ID<pTJFD-2bp-15@gated-at.bofh.it>
In reply to#1199782
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
  - Add Reviewed-by,

v3:
  - New.
---
 arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 3355c487d108360f..c4654047e684ff09 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -68,6 +68,7 @@
 			     <0 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0x60>;
 
@@ -87,6 +88,7 @@
 			     <0 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0xff>;
 
@@ -109,6 +111,7 @@
 			     <0 16 IRQ_TYPE_LEVEL_HIGH>,
 			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	scif0: serial@e6e60000 {
@@ -117,6 +120,7 @@
 		interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -126,6 +130,7 @@
 		interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -134,6 +139,7 @@
 		reg = <0 0xee700000 0 0x400>;
 		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
+		power-domains = <&cpg_clocks>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -164,6 +170,7 @@
 			clock-output-names = "main", "pll0", "pll1", "pll3",
 					     "lb", "qspi", "sdh", "sd0", "z",
 					     "rcan", "adsp";
+			#power-domain-cells = <0>;
 		};
 
 		/* Variable factor clocks */
-- 
1.9.1

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#1199784 — [PATCH v4 01/16] clk: shmobile: Add CPG/MSTP Clock Domain support

FromGeert Uytterhoeven <geert+renesas@glider.be>
Date2015-08-04 14:40 +0200
Subject[PATCH v4 01/16] clk: shmobile: Add CPG/MSTP Clock Domain support
Message-ID<pTJFE-2bp-19@gated-at.bofh.it>
In reply to#1199782
Add Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain.  This allows to
power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a
proper "power-domains" property.

The CPG/MSTP Clock Domain code will scan such devices for clocks that
are suitable for power-managing the device, by looking for a clock that
is compatible with "renesas,cpg-mstp-clocks".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
---
v4:
  - clk-mstp.c needs to #include <linux/clk.h> due to recent
    <linux/clk*.h> shuffling,

v3:
  - Add Acked-by,
  - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
  - Drop bogus addition of #includes to clk-rcar-gen2.c,
  - Call pm_clk_destroy() from cpg_mstp_detach_dev() only if
    cpg_mstp_attach_dev() actually added a clock,

v2:
  - Add Acked-by and Reviewed-by,
  - Move core CPG Clock Domain code from the R-Car Gen2 driver to the
    CPG MSTP Clock driver, as it's generic, and can be used on other
    Renesas SoCs that have a CPG/MSTP block,
  - Scan for an MSTP clock instead of using the first clock tied to the
    device (con_id NULL),
  - Extract R-Car Gen2 specifics to a separate patch.
---
 drivers/clk/shmobile/clk-mstp.c | 87 +++++++++++++++++++++++++++++++++++++++++
 include/linux/clk/shmobile.h    | 12 ++++++
 2 files changed, 99 insertions(+)

diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
index 2d2fe773ac8168f9..b1df7b2f1e970adb 100644
--- a/drivers/clk/shmobile/clk-mstp.c
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -2,6 +2,7 @@
  * R-Car MSTP clocks
  *
  * Copyright (C) 2013 Ideas On Board SPRL
+ * Copyright (C) 2015 Glider bvba
  *
  * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  *
@@ -10,11 +11,16 @@
  * the Free Software Foundation; version 2 of the License.
  */
 
+#include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
 #include <linux/spinlock.h>
 
 /*
@@ -236,3 +242,84 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
 	of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
 }
 CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
+
+
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+	struct of_phandle_args clkspec;
+	struct clk *clk;
+	int i = 0;
+	int error;
+
+	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
+					   &clkspec)) {
+		if (of_device_is_compatible(clkspec.np,
+					    "renesas,cpg-mstp-clocks"))
+			goto found;
+
+		of_node_put(clkspec.np);
+		i++;
+	}
+
+	return 0;
+
+found:
+	clk = of_clk_get_from_provider(&clkspec);
+	of_node_put(clkspec.np);
+
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	error = pm_clk_create(dev);
+	if (error) {
+		dev_err(dev, "pm_clk_create failed %d\n", error);
+		goto fail_put;
+	}
+
+	error = pm_clk_add_clk(dev, clk);
+	if (error) {
+		dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
+		goto fail_destroy;
+	}
+
+	return 0;
+
+fail_destroy:
+	pm_clk_destroy(dev);
+fail_put:
+	clk_put(clk);
+	return error;
+}
+
+void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+	if (!list_empty(&dev->power.subsys_data->clock_list))
+		pm_clk_destroy(dev);
+}
+
+void __init cpg_mstp_add_clk_domain(struct device_node *np)
+{
+	struct generic_pm_domain *pd;
+	u32 ncells;
+
+	if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
+		pr_warn("%s lacks #power-domain-cells\n", np->full_name);
+		return;
+	}
+
+	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+	if (!pd)
+		return;
+
+	pd->name = np->name;
+
+	pd->flags = GENPD_FLAG_PM_CLK;
+	pm_genpd_init(pd, &simple_qos_governor, false);
+	pd->attach_dev = cpg_mstp_attach_dev;
+	pd->detach_dev = cpg_mstp_detach_dev;
+
+	of_genpd_add_provider_simple(np, pd);
+}
+#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index 63a8159c4e64153d..cb19cc1865ca5cfb 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -16,8 +16,20 @@
 
 #include <linux/types.h>
 
+struct device;
+struct device_node;
+struct generic_pm_domain;
+
 void r8a7778_clocks_init(u32 mode);
 void r8a7779_clocks_init(u32 mode);
 void rcar_gen2_clocks_init(u32 mode);
 
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+void cpg_mstp_add_clk_domain(struct device_node *np);
+int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev);
+void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev);
+#else
+static inline void cpg_mstp_add_clk_domain(struct device_node *np) {}
+#endif
+
 #endif
-- 
1.9.1

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#1199785 — [PATCH v4 12/16] ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain

FromGeert Uytterhoeven <geert+renesas@glider.be>
Date2015-08-04 14:40 +0200
Subject[PATCH v4 12/16] ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
Message-ID<pTJFE-2bp-21@gated-at.bofh.it>
In reply to#1199782
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
  - Add "power-domains" properties to recently introduced mmcif0 device
    node,
  - Consistently add "power-domains" properties after clock and dma
    properties,

v3:
  - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",

v2:
  - Add Reviewed-by,
  - Add "power-domains" properties to recently introduced USB-DMAC
    device nodes,
  - Drop adding "power-domains" properties to the GIC device node, as
    adding the INTC_SYS clock is postponed.
---
 arch/arm/boot/dts/r8a7794.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 43acf185ecc43f40..97c8e9ace5ebee1e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -57,6 +57,7 @@
 			     <0 143 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0x60>;
 
@@ -76,6 +77,7 @@
 			     <0 127 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		renesas,channels-mask = <0xff>;
 
@@ -106,6 +108,7 @@
 			     <0 16 IRQ_TYPE_LEVEL_HIGH>,
 			     <0 17 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
+		power-domains = <&cpg_clocks>;
 	};
 
 	pfc: pin-controller@e6060000 {
@@ -140,6 +143,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
@@ -170,6 +174,7 @@
 				"ch12", "ch13", "ch14";
 		clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		#dma-cells = <1>;
 		dma-channels = <15>;
 	};
@@ -182,6 +187,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x21>, <&dmac0 0x22>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -193,6 +199,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x25>, <&dmac0 0x26>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -204,6 +211,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x27>, <&dmac0 0x28>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -215,6 +223,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -226,6 +235,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -237,6 +247,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x23>, <&dmac0 0x24>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -248,6 +259,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -259,6 +271,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -270,6 +283,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -281,6 +295,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -292,6 +307,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -303,6 +319,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -314,6 +331,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -325,6 +343,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -336,6 +355,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -347,6 +367,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -358,6 +379,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -369,6 +391,7 @@
 		clock-names = "sci_ick";
 		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -377,6 +400,7 @@
 		reg = <0 0xee700000 0 0x400>;
 		interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
+		power-domains = <&cpg_clocks>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -390,6 +414,7 @@
 		clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
 		dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 		dma-names = "tx", "rx";
+		power-domains = <&cpg_clocks>;
 		reg-io-width = <4>;
 		status = "disabled";
 	};
@@ -399,6 +424,7 @@
 		reg = <0 0xee100000 0 0x200>;
 		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -407,6 +433,7 @@
 		reg = <0 0xee140000 0 0x100>;
 		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -415,6 +442,7 @@
 		reg = <0 0xee160000 0 0x100>;
 		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -441,6 +469,7 @@
 			#clock-cells = <1>;
 			clock-output-names = "main", "pll0", "pll1", "pll3",
 					     "lb", "qspi", "sdh", "sd0", "z";
+			#power-domain-cells = <0>;
 		};
 		/* Variable factor clocks */
 		sd2_clk: sd2_clk@e6150078 {
-- 
1.9.1

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#1199786 — [PATCH v4 06/16] ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain

FromGeert Uytterhoeven <geert+renesas@glider.be>
Date2015-08-04 14:40 +0200
Subject[PATCH v4 06/16] ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
Message-ID<pTJFE-2bp-23@gated-at.bofh.it>
In reply to#1199782
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
  - Add Reviewed-by,

v3:
  - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",

v2:
  - New.
---
 arch/arm/boot/dts/r7s72100.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 277e73c110e5d40c..060c32cbd66923ed 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -86,6 +86,7 @@
 			reg = <0xfcfe0000 0x18>;
 			clocks = <&extal_clk>, <&usb_x1_clk>;
 			clock-output-names = "pll", "i", "g";
+			#power-domain-cells = <0>;
 		};
 
 		/* MSTP clocks */
@@ -157,6 +158,7 @@
 			     <0 189 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -169,6 +171,7 @@
 			     <0 193 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -181,6 +184,7 @@
 			     <0 197 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -193,6 +197,7 @@
 			     <0 201 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -205,6 +210,7 @@
 			     <0 205 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -217,6 +223,7 @@
 			     <0 209 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -229,6 +236,7 @@
 			     <0 213 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -241,6 +249,7 @@
 			     <0 217 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -252,6 +261,7 @@
 			     <0 240 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+		power-domains = <&cpg_clocks>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -266,6 +276,7 @@
 			     <0 243 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+		power-domains = <&cpg_clocks>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -280,6 +291,7 @@
 			     <0 246 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+		power-domains = <&cpg_clocks>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -294,6 +306,7 @@
 			     <0 249 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+		power-domains = <&cpg_clocks>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -308,6 +321,7 @@
 			     <0 252 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "error", "rx", "tx";
 		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+		power-domains = <&cpg_clocks>;
 		num-cs = <1>;
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -338,6 +352,7 @@
 			     <0 164 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
 		clock-frequency = <100000>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -356,6 +371,7 @@
 			     <0 172 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
 		clock-frequency = <100000>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -374,6 +390,7 @@
 			     <0 180 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
 		clock-frequency = <100000>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -392,6 +409,7 @@
 			     <0 188 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
 		clock-frequency = <100000>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -402,6 +420,7 @@
 		interrupt-names = "tgi0a";
 		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 };
-- 
1.9.1

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#1199787 — [PATCH v4 16/16] ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers

FromGeert Uytterhoeven <geert+renesas@glider.be>
Date2015-08-04 14:40 +0200
Subject[PATCH v4 16/16] ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
Message-ID<pTJFE-2bp-27@gated-at.bofh.it>
In reply to#1199782
The R-Mobile PM Domain driver manages both power domains and a clock
domain.

The clock domain part is very similar to the CPG/MSTP Clock Domain,
which is used on shmobile SoCs without device power domains, except for
the way how clocks suitable for power management are selected:
  - The former uses the first clock tied to the device through the NULL
    con_id, which is a relic from the legacy pm_clk_notifier-based
    method in drivers/sh/pm_runtime.c,
  - The latter looks for suitable clocks in DT, which is more
    future-proof.

All platforms using this driver are now supported in DT-based ARM
multi-platform builds only, hence switch to using the CPG/MSTP Clock
Domain helpers.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
  - Add Reviewed-by,

v3:
  - Drop -legacy support, hence this patch depends on r8a7740/sh73a0
    legacy removal,
  - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",

v2:
  - New.
---
 arch/arm/mach-shmobile/pm-rmobile.c | 35 +++--------------------------------
 1 file changed, 3 insertions(+), 32 deletions(-)

diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index a5b96b990aea8dfc..89068c8ec50f2c76 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -12,6 +12,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
+#include <linux/clk/shmobile.h>
 #include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/of.h>
@@ -124,36 +125,6 @@ static bool rmobile_pd_active_wakeup(struct device *dev)
 	return true;
 }
 
-static int rmobile_pd_attach_dev(struct generic_pm_domain *domain,
-				 struct device *dev)
-{
-	int error;
-
-	error = pm_clk_create(dev);
-	if (error) {
-		dev_err(dev, "pm_clk_create failed %d\n", error);
-		return error;
-	}
-
-	error = pm_clk_add(dev, NULL);
-	if (error) {
-		dev_err(dev, "pm_clk_add failed %d\n", error);
-		goto fail;
-	}
-
-	return 0;
-
-fail:
-	pm_clk_destroy(dev);
-	return error;
-}
-
-static void rmobile_pd_detach_dev(struct generic_pm_domain *domain,
-				  struct device *dev)
-{
-	pm_clk_destroy(dev);
-}
-
 static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
 {
 	struct generic_pm_domain *genpd = &rmobile_pd->genpd;
@@ -164,8 +135,8 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
 	genpd->dev_ops.active_wakeup	= rmobile_pd_active_wakeup;
 	genpd->power_off		= rmobile_pd_power_down;
 	genpd->power_on			= rmobile_pd_power_up;
-	genpd->attach_dev		= rmobile_pd_attach_dev;
-	genpd->detach_dev		= rmobile_pd_detach_dev;
+	genpd->attach_dev		= cpg_mstp_attach_dev;
+	genpd->detach_dev		= cpg_mstp_detach_dev;
 	__rmobile_pd_power_up(rmobile_pd, false);
 }
 
-- 
1.9.1

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#1199788 — [PATCH v4 02/16] clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support

FromGeert Uytterhoeven <geert+renesas@glider.be>
Date2015-08-04 14:40 +0200
Subject[PATCH v4 02/16] clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
Message-ID<pTJFE-2bp-29@gated-at.bofh.it>
In reply to#1199782
Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain.  This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
  - Add Reviewed-by,

v3:
  - Add Acked-by,
  - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",

v2:
  - New.
---
 .../bindings/clock/renesas,r8a7778-cpg-clocks.txt  | 29 +++++++++++++++++++---
 arch/arm/mach-shmobile/Kconfig                     |  1 +
 drivers/clk/shmobile/clk-r8a7778.c                 |  2 ++
 3 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
index 2f3747fdcf1c5305..e4cdaf1cb3333012 100644
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -1,7 +1,9 @@
 * Renesas R8A7778 Clock Pulse Generator (CPG)
 
 The CPG generates core clocks for the R8A7778. It includes two PLLs and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
 
 Required Properties:
 
@@ -10,10 +12,18 @@ Required Properties:
   - #clock-cells: Must be 1
   - clock-output-names: The names of the clocks. Supported clocks are
     "plla", "pllb", "b", "out", "p", "s", and "s1".
+  - #power-domain-cells: Must be 0
 
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
 
-Example
--------
+
+Examples
+--------
+
+  - CPG device node:
 
 	cpg_clocks: cpg_clocks@ffc80000 {
 		compatible = "renesas,r8a7778-cpg-clocks";
@@ -22,4 +32,17 @@ Example
 		clocks = <&extal_clk>;
 		clock-output-names = "plla", "pllb", "b",
 				     "out", "p", "s", "s1";
+		#power-domain-cells = <0>;
+	};
+
+
+  - CPG/MSTP Clock Domain member device node:
+
+	sdhi0: sd@ffe4c000 {
+		compatible = "renesas,sdhi-r8a7778";
+		reg = <0xffe4c000 0x100>;
+		interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
 	};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index aa38a438af8990ef..5b1f9eca7c871aee 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
 
 config PM_RCAR
 	bool
+	select PM_GENERIC_DOMAINS if PM
 
 config PM_RMOBILE
 	bool
diff --git a/drivers/clk/shmobile/clk-r8a7778.c b/drivers/clk/shmobile/clk-r8a7778.c
index e97e28fcfc13d102..87c1d2f2fb57a46c 100644
--- a/drivers/clk/shmobile/clk-r8a7778.c
+++ b/drivers/clk/shmobile/clk-r8a7778.c
@@ -124,6 +124,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
 	}
 
 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+	cpg_mstp_add_clk_domain(np);
 }
 
 CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
-- 
1.9.1

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#1199789 — [PATCH v4 07/16] ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain

FromGeert Uytterhoeven <geert+renesas@glider.be>
Date2015-08-04 14:40 +0200
Subject[PATCH v4 07/16] ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
Message-ID<pTJFE-2bp-31@gated-at.bofh.it>
In reply to#1199782
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.  A notable
exception is the "sound" node, which represents multiple SoC devices,
each having their own MSTP clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
  - Add Reviewed-by,

v3:
  - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",

v2:
  - New.
---
 arch/arm/boot/dts/r8a7778.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 7ce9f5fd586504f2..4b1fa9f42ad5457b 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -53,6 +53,7 @@
 		reg = <0xfde00000 0x400>;
 		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
+		power-domains = <&cpg_clocks>;
 		phy-mode = "rmii";
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -152,6 +153,7 @@
 		reg = <0xffc70000 0x1000>;
 		interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -162,6 +164,7 @@
 		reg = <0xffc71000 0x1000>;
 		interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -172,6 +175,7 @@
 		reg = <0xffc72000 0x1000>;
 		interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -182,6 +186,7 @@
 		reg = <0xffc73000 0x1000>;
 		interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -193,6 +198,7 @@
 			     <0 34 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		#renesas,channels = <3>;
 
@@ -207,6 +213,7 @@
 			     <0 38 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		#renesas,channels = <3>;
 
@@ -221,6 +228,7 @@
 			     <0 42 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
 		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
 
 		#renesas,channels = <3>;
 
@@ -288,6 +296,7 @@
 		interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -297,6 +306,7 @@
 		interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -306,6 +316,7 @@
 		interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -315,6 +326,7 @@
 		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -324,6 +336,7 @@
 		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -333,6 +346,7 @@
 		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
 		clock-names = "sci_ick";
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -341,6 +355,7 @@
 		reg = <0xffe4e000 0x100>;
 		interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7778_CLK_MMC>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -349,6 +364,7 @@
 		reg = <0xffe4c000 0x100>;
 		interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -357,6 +373,7 @@
 		reg = <0xffe4d000 0x100>;
 		interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -365,6 +382,7 @@
 		reg = <0xffe4f000 0x100>;
 		interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
+		power-domains = <&cpg_clocks>;
 		status = "disabled";
 	};
 
@@ -373,6 +391,7 @@
 		reg = <0xfffc7000 0x18>;
 		interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -383,6 +402,7 @@
 		reg = <0xfffc8000 0x18>;
 		interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -393,6 +413,7 @@
 		reg = <0xfffc6000 0x18>;
 		interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+		power-domains = <&cpg_clocks>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 		status = "disabled";
@@ -419,6 +440,7 @@
 			clocks = <&extal_clk>;
 			clock-output-names = "plla", "pllb", "b",
 					     "out", "p", "s", "s1";
+			#power-domain-cells = <0>;
 		};
 
 		/* Audio clocks; frequencies are set by boards if applicable. */
-- 
1.9.1

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#1199841

FromSimon Horman <horms@verge.net.au>
Date2015-08-04 15:50 +0200
Message-ID<pTKLn-3IO-1@gated-at.bofh.it>
In reply to#1199782
Thanks Geert,

I have tentatively queued this up in its own branch,
cpg-mstp-clock-domain-for-v4.3.
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#1200331

FromSimon Horman <horms@verge.net.au>
Date2015-08-05 03:00 +0200
Message-ID<pTVdL-2dL-1@gated-at.bofh.it>
In reply to#1199841
On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> Thanks Geert,
> 
> I have tentatively queued this up in its own branch,
> cpg-mstp-clock-domain-for-v4.3.

Where possible I prefer not to apply non-DTS/DTSI patches on top of
DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
maintainers like things handled.  With this in mind I have shuffled things
around a little, the result is:

1. The following are (still) queued up for v4.3 in their own
   cpg-mstp-clock-domain-for-v4.3 branch:

   clk: shmobile: Add CPG/MSTP Clock Domain support
   clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
   clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
   clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
   clk: shmobile: rz: Add CPG/MSTP Clock Domain support
   ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
   ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
   ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
   ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
   ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
   ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
   ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain

2. The following are now queued up for v4.3 in a separate
   sh-drivers-for-v4.3 branch. That branch is on top of the
   cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
   to Linus if/when a v4.3-rc has been released with the patches
   listed in 1. present.

   drivers: sh: Disable legacy default PM Domain on emev2
   drivers: sh: Disable PM runtime for multi-platform ARM with genpd

3. I have deferred the remaining two patches, listed below, for v4.4.
   they currently reside in cpg-mstp-clock-domain-for-v4.4. That
   branch is based on the sh-drivers-for-v4.3 branch.

   clk: shmobile: mstp: Consider "zb_clk" suitable for power management
   ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers


This means that the last two patches will disappear from next until
after v4.3-rc1 is released but they, along with all the other patches,
will be present in the renesas devel branch.
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#1200460

FromGeert Uytterhoeven <geert@linux-m68k.org>
Date2015-08-05 09:00 +0200
Message-ID<pU0Qa-22l-21@gated-at.bofh.it>
In reply to#1200331
Hi Simon,

On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
>> I have tentatively queued this up in its own branch,
>> cpg-mstp-clock-domain-for-v4.3.
>
> Where possible I prefer not to apply non-DTS/DTSI patches on top of
> DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> maintainers like things handled.  With this in mind I have shuffled things
> around a little, the result is:
>
> 1. The following are (still) queued up for v4.3 in their own
>    cpg-mstp-clock-domain-for-v4.3 branch:
>
>    clk: shmobile: Add CPG/MSTP Clock Domain support
>    clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
>    clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
>    clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
>    clk: shmobile: rz: Add CPG/MSTP Clock Domain support
>    ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
>    ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
>    ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
>    ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
>    ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
>    ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
>    ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain

OK.

> 2. The following are now queued up for v4.3 in a separate
>    sh-drivers-for-v4.3 branch. That branch is on top of the
>    cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
>    to Linus if/when a v4.3-rc has been released with the patches
>    listed in 1. present.
>
>    drivers: sh: Disable legacy default PM Domain on emev2
>    drivers: sh: Disable PM runtime for multi-platform ARM with genpd

OK

> 3. I have deferred the remaining two patches, listed below, for v4.4.
>    they currently reside in cpg-mstp-clock-domain-for-v4.4. That
>    branch is based on the sh-drivers-for-v4.3 branch.
>
>    clk: shmobile: mstp: Consider "zb_clk" suitable for power management
>    ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
>
> This means that the last two patches will disappear from next until
> after v4.3-rc1 is released but they, along with all the other patches,
> will be present in the renesas devel branch.

OK.

Note that as the last two depend on patch 1 only, you could e.g. queue
them up in group 1, between the clk and dtsi patches.
But it's up to you to reconsider.
I'm happy as-is, as the last two patches are just a code duplication clean up.

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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#1201374

FromSimon Horman <horms@verge.net.au>
Date2015-08-06 03:00 +0200
Message-ID<pUhHj-19S-3@gated-at.bofh.it>
In reply to#1200460
On Wed, Aug 05, 2015 at 08:58:29AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
> 
> On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> >> I have tentatively queued this up in its own branch,
> >> cpg-mstp-clock-domain-for-v4.3.
> >
> > Where possible I prefer not to apply non-DTS/DTSI patches on top of
> > DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> > maintainers like things handled.  With this in mind I have shuffled things
> > around a little, the result is:
> >
> > 1. The following are (still) queued up for v4.3 in their own
> >    cpg-mstp-clock-domain-for-v4.3 branch:
> >
> >    clk: shmobile: Add CPG/MSTP Clock Domain support
> >    clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> >    clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> >    clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> >    clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> >    ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> >    ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> >    ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> >    ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> >    ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> >    ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> >    ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
> 
> OK.
> 
> > 2. The following are now queued up for v4.3 in a separate
> >    sh-drivers-for-v4.3 branch. That branch is on top of the
> >    cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> >    to Linus if/when a v4.3-rc has been released with the patches
> >    listed in 1. present.
> >
> >    drivers: sh: Disable legacy default PM Domain on emev2
> >    drivers: sh: Disable PM runtime for multi-platform ARM with genpd
> 
> OK
> 
> > 3. I have deferred the remaining two patches, listed below, for v4.4.
> >    they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> >    branch is based on the sh-drivers-for-v4.3 branch.
> >
> >    clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> >    ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
> >
> > This means that the last two patches will disappear from next until
> > after v4.3-rc1 is released but they, along with all the other patches,
> > will be present in the renesas devel branch.
> 
> OK.
> 
> Note that as the last two depend on patch 1 only, you could e.g. queue
> them up in group 1, between the clk and dtsi patches.
> But it's up to you to reconsider.
> I'm happy as-is, as the last two patches are just a code duplication clean up.

Thanks, and sorry for not realising that.

For now I will keep things as-is because I would like to stabilise my
branches.
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