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Groups > linux.kernel > #1194982 > unrolled thread
| Started by | Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
|---|---|
| First post | 2015-07-29 11:20 +0200 |
| Last post | 2015-07-29 21:40 +0200 |
| Articles | 4 — 3 participants |
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[PATCH v3 0/3] x86/pci/intel-mid-pci: fix to get eMMC detected Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2015-07-29 11:20 +0200
[PATCH v3 2/3] x86/pci/intel_mid_pci: propagate actual return code Andy Shevchenko <andriy.shevchenko@linux.intel.com> - 2015-07-29 11:20 +0200
[tip:x86/platform] x86/pci/intel_mid_pci: Propagate actual return code tip-bot for Andy Shevchenko <tipbot@zytor.com> - 2015-07-29 21:40 +0200
Re: [PATCH v3 0/3] x86/pci/intel-mid-pci: fix to get eMMC detected Thomas Gleixner <tglx@linutronix.de> - 2015-07-29 21:40 +0200
| From | Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
|---|---|
| Date | 2015-07-29 11:20 +0200 |
| Subject | [PATCH v3 0/3] x86/pci/intel-mid-pci: fix to get eMMC detected |
| Message-ID | <pRvGN-3OC-3@gated-at.bofh.it> |
On Intel Edison we have an interesting implementation of x86 platform without legacy PIC and with specific PCI. There are devices which are not using interrupt line 0, but have it assigned in the PCI configuration. By default first come gets it, though the first eMMC host controller is the actual user for IRQ0. So, this series provides a quirk (patch 1) to resolve the issue, a small fix of error code (patch 2), and a sparse warning fix (patch 3). Changelog v3: - address Thomas' comments - massage changelog (what Thomas proposed) Changelog v2: - rearrange patches 1 and 2 to provide fix first with Fixes: tag - append patch 3 - rebase on top of recent linux-next Andy Shevchenko (3): x86/pci/intel_mid_pci: work around for IRQ0 assignment x86/pci/intel_mid_pci: propagate actual return code x86/pci/intel_mid_pci: fix a sparse warning arch/x86/pci/intel_mid_pci.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) -- 2.4.6 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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| From | Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
|---|---|
| Date | 2015-07-29 11:20 +0200 |
| Subject | [PATCH v3 2/3] x86/pci/intel_mid_pci: propagate actual return code |
| Message-ID | <pRvGP-3OC-19@gated-at.bofh.it> |
| In reply to | #1194982 |
mp_map_gsi_to_irq() returns different codes if it fails.
intel_mid_pci_irq_enable() hides this under -EBUSY. The patch replaces it by
what is actually returned.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/pci/intel_mid_pci.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 7553921..3361f0a 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -213,6 +213,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
{
struct irq_alloc_info info;
int polarity;
+ int ret;
if (dev->irq_managed && dev->irq > 0)
return 0;
@@ -244,8 +245,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
* IOAPIC RTE entries, so we just enable RTE for the device.
*/
- if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0)
- return -EBUSY;
+ ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
+ if (ret < 0)
+ return ret;
dev->irq_managed = 1;
--
2.4.6
--
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| From | tip-bot for Andy Shevchenko <tipbot@zytor.com> |
|---|---|
| Date | 2015-07-29 21:40 +0200 |
| Subject | [tip:x86/platform] x86/pci/intel_mid_pci: Propagate actual return code |
| Message-ID | <pRFmO-LX-19@gated-at.bofh.it> |
| In reply to | #1194985 |
Commit-ID: 2a61c8eaf1879db99286c3f5fe5e78086c7edb85
Gitweb: http://git.kernel.org/tip/2a61c8eaf1879db99286c3f5fe5e78086c7edb85
Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Wed, 29 Jul 2015 12:16:48 +0300
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 29 Jul 2015 21:23:50 +0200
x86/pci/intel_mid_pci: Propagate actual return code
mp_map_gsi_to_irq() returns different codes if it fails.
intel_mid_pci_irq_enable() hides this under -EBUSY.
Return the actual failure code.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Link: http://lkml.kernel.org/r/1438161409-4671-3-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/pci/intel_mid_pci.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 7553921..3361f0a 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -213,6 +213,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
{
struct irq_alloc_info info;
int polarity;
+ int ret;
if (dev->irq_managed && dev->irq > 0)
return 0;
@@ -244,8 +245,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
* IOAPIC RTE entries, so we just enable RTE for the device.
*/
- if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0)
- return -EBUSY;
+ ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
+ if (ret < 0)
+ return ret;
dev->irq_managed = 1;
--
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| From | Thomas Gleixner <tglx@linutronix.de> |
|---|---|
| Date | 2015-07-29 21:40 +0200 |
| Message-ID | <pRFmO-LX-21@gated-at.bofh.it> |
| In reply to | #1194982 |
On Wed, 29 Jul 2015, Andy Shevchenko wrote:
> On Intel Edison we have an interesting implementation of x86 platform without
> legacy PIC and with specific PCI. There are devices which are not using
> interrupt line 0, but have it assigned in the PCI configuration. By default
> first come gets it, though the first eMMC host controller is the actual user
> for IRQ0.
>
> So, this series provides a quirk (patch 1) to resolve the issue, a small fix of
> error code (patch 2), and a sparse warning fix (patch 3).
>
> Changelog v3:
> - address Thomas' comments
> - massage changelog (what Thomas proposed)
>
> Andy Shevchenko (3):
> x86/pci/intel_mid_pci: work around for IRQ0 assignment
> x86/pci/intel_mid_pci: propagate actual return code
> x86/pci/intel_mid_pci: fix a sparse warning
I've picked them up. If you get the tip-bot mails, you might notice a
few edits on the changelogs.
- Sentence starts with an upper case letter.
- You cannot fix a sparse warning.
- "This patch does ...." is just horrible. When one reads a patch
he already knows that it is a patch.
Please avoid these things in the future.
Thanks,
tglx
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