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Re: [PATCH 1/2] PM / devfreq: exynos-ppmu: Add the support of PPMUv2 for Exynos5433

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  Re: [PATCH 1/2] PM / devfreq: exynos-ppmu: Add the support of PPMUv2  for Exynos5433 Chanwoo Choi <cwchoi00@gmail.com> - 2015-07-23 16:20 +0200

#1190948 — Re: [PATCH 1/2] PM / devfreq: exynos-ppmu: Add the support of PPMUv2 for Exynos5433

On Thu, Jul 23, 2015 at 11:43 AM, Dan Carpenter
<dan.carpenter@oracle.com> wrote:
> On Thu, Jul 23, 2015 at 10:57:18AM +0900, Chanwoo Choi wrote:
>> +static int exynos_ppmu_v2_disable(struct devfreq_event_dev *edev)
>> +{
>> +     struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
>> +     u32 pmnc, clear;
>> +
>> +     /* Disable all counters */
>> +     clear = (PPMU_CCNT_MASK | PPMU_PMCNT0_MASK | PPMU_PMCNT1_MASK
>> +             | PPMU_PMCNT2_MASK | PPMU_PMCNT3_MASK);
>> +
>> +     __raw_writel(clear, info->ppmu.base + PPMUv2_FLAG);
>
> Why aren't you using normal readl()/writel()?  What are the endiannesses
> here?

There are no special reason. Usually I used the __raw_readl/writel to
access the SFR registers

Thanks,
Chanwoo Choi
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