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Re: [RFC 4/4] mmc: sdhci-msm: Handle unexpected interrupt case on enabling legacy IRQs on CQE halt

From Adrian Hunter <adrian.hunter@intel.com>
Newsgroups linux.kernel
Subject Re: [RFC 4/4] mmc: sdhci-msm: Handle unexpected interrupt case on enabling legacy IRQs on CQE halt
Date 2017-08-31 09:50 +0200
Message-ID <uksoG-2N0-21@gated-at.bofh.it> (permalink)
References <ukaUN-i2-1@gated-at.bofh.it> <ukaUP-i2-35@gated-at.bofh.it>
Organization Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki

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On 30/08/17 16:04, Ritesh Harjani wrote:
> There is a case when enabling the legacy IRQs and halting CQE is
> resuling into a command response interrupt without any command in
> progress. This patch handles such case here.
> 
> Error signature without this patch:-
> mmc0: Got command interrupt 0x00000001 even though no command operation
> was in progress.
> 
> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>

Seems fine, but this is a necessary part of enabling i.e. put all the
sdhci-msm changes into one patch.

> ---
>  drivers/mmc/host/sdhci-msm.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index baa3409..8fdc2c0 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -1124,10 +1124,21 @@ void sdhci_msm_cqe_enable(struct mmc_host *mmc)
>  void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
>  {
>  	struct sdhci_host *host = mmc_priv(mmc);
> +	unsigned long flags;
> +	u32 ctrl;
>  
>  	if (host->flags & SDHCI_USE_64_BIT_DMA)
>  		host->desc_sz = 16;
>  
> +	spin_lock_irqsave(&host->lock, flags);
> +

Could use a comment here.

> +	ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
> +	ctrl |= SDHCI_INT_RESPONSE;
> +	sdhci_writel(host,  ctrl, SDHCI_INT_ENABLE);
> +	sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
> +
> +	spin_unlock_irqrestore(&host->lock, flags);
> +
>  	sdhci_cqe_disable(mmc, recovery);
>  }
>  
> 

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Thread

[RFC 0/4] mmc: sdhci-msm: Add CQE support for sdhci-msm Ritesh Harjani <riteshh@codeaurora.org> - 2017-08-30 15:10 +0200
  [RFC 2/4] mmc: sdhci-msm: Add CQHCI support for sdhci-msm Ritesh Harjani <riteshh@codeaurora.org> - 2017-08-30 15:10 +0200
    Re: [RFC 2/4] mmc: sdhci-msm: Add CQHCI support for sdhci-msm Adrian Hunter <adrian.hunter@intel.com> - 2017-08-31 09:40 +0200
      Re: [RFC 2/4] mmc: sdhci-msm: Add CQHCI support for sdhci-msm Ritesh Harjani <riteshh@codeaurora.org> - 2017-09-02 07:20 +0200
  [RFC 3/4] mmc: sdhci-msm: Change the desc_sz on cqe_enable/disable. Ritesh Harjani <riteshh@codeaurora.org> - 2017-08-30 15:10 +0200
    Re: [RFC 3/4] mmc: sdhci-msm: Change the desc_sz on  cqe_enable/disable. Adrian Hunter <adrian.hunter@intel.com> - 2017-08-31 08:50 +0200
      Re: [RFC 3/4] mmc: sdhci-msm: Change the desc_sz on  cqe_enable/disable. Ritesh Harjani <riteshh@codeaurora.org> - 2017-09-02 07:20 +0200
  [RFC 1/4] mmc: cqhci: Move CQHCI_ENABLE before setting TDLBA/TDLBAU Ritesh Harjani <riteshh@codeaurora.org> - 2017-08-30 15:10 +0200
    Re: [RFC 1/4] mmc: cqhci: Move CQHCI_ENABLE before setting  TDLBA/TDLBAU Adrian Hunter <adrian.hunter@intel.com> - 2017-08-31 08:20 +0200
      Re: [RFC 1/4] mmc: cqhci: Move CQHCI_ENABLE before setting  TDLBA/TDLBAU Ritesh Harjani <riteshh@codeaurora.org> - 2017-09-02 07:10 +0200
  [RFC 4/4] mmc: sdhci-msm: Handle unexpected interrupt case on enabling legacy IRQs on CQE halt Ritesh Harjani <riteshh@codeaurora.org> - 2017-08-30 15:10 +0200
    Re: [RFC 4/4] mmc: sdhci-msm: Handle unexpected interrupt case on  enabling legacy IRQs on CQE halt Adrian Hunter <adrian.hunter@intel.com> - 2017-08-31 09:50 +0200
      Re: [RFC 4/4] mmc: sdhci-msm: Handle unexpected interrupt case on  enabling legacy IRQs on CQE halt Ritesh Harjani <riteshh@codeaurora.org> - 2017-09-02 07:20 +0200
  Re: [RFC 0/4] mmc: sdhci-msm: Add CQE support for sdhci-msm Adrian Hunter <adrian.hunter@intel.com> - 2017-08-31 10:50 +0200
    Re: [RFC 0/4] mmc: sdhci-msm: Add CQE support for sdhci-msm Ritesh Harjani <riteshh@codeaurora.org> - 2017-09-02 07:20 +0200

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