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Groups > linux.kernel > #1717828
| From | Vineet Gupta <Vineet.Gupta1@synopsys.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency |
| Date | 2017-08-22 22:50 +0200 |
| Message-ID | <uhohA-7x1-31@gated-at.bofh.it> (permalink) |
| References | <ueqfT-6mT-1@gated-at.bofh.it> <ueqfV-6mT-35@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> Add core pll node (core_clk) to manage cpu frequency.
> core_clk represents pll itself.
> input_clk represents clock signal source (basically xtal) which
> comes to pll input.
>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> ---
> arch/arc/boot/dts/axc003.dtsi | 11 +++++++++--
> arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++--
> 2 files changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
> index cc9239e..dca7e39 100644
> --- a/arch/arc/boot/dts/axc003.dtsi
> +++ b/arch/arc/boot/dts/axc003.dtsi
> @@ -24,10 +24,17 @@
>
> ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
>
> - core_clk: core_clk {
> + input_clk: input-clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - clock-frequency = <90000000>;
> + clock-frequency = <33333333>;
> + };
> +
> + core_clk: core-clk@80 {
> + compatible = "snps,axs10x-arc-pll-clock";
> + reg = <0x80 0x10>, <0x100 0x10>;
> + #clock-cells = <0>;
> + clocks = <&input_clk>;
> };
>
> core_intc: archs-intc@cpu {
> diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
> index 4ebb2170..5b56bef 100644
> --- a/arch/arc/boot/dts/axc003_idu.dtsi
> +++ b/arch/arc/boot/dts/axc003_idu.dtsi
> @@ -24,10 +24,17 @@
>
> ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
>
> - core_clk: core_clk {
> + input_clk: input-clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - clock-frequency = <100000000>;
> + clock-frequency = <33333333>;
> + };
> +
> + core_clk: core-clk@80 {
> + compatible = "snps,axs10x-arc-pll-clock";
> + reg = <0x80 0x10>, <0x100 0x10>;
> + #clock-cells = <0>;
> + clocks = <&input_clk>;
> };
>
> core_intc: archs-intc@cpu {
Do we have a bisectability issue here - isn't system broken temporarily at 2/5 -
and only 3/5 makes it work again - if so we need to squash them together !
-Vineet
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[PATCH 0/5] Updates to arc clock tree managment Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> - 2017-08-14 18:20 +0200
[PATCH 2/5] ARC: AXS103: Get rid of platform specific cpu clock configuration Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> - 2017-08-14 18:20 +0200
Re: [PATCH 2/5] ARC: AXS103: Get rid of platform specific cpu clock configuration Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-08-22 22:40 +0200
[PATCH 1/5] ARC: set and print cpu frequency at boot time Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> - 2017-08-14 18:20 +0200
[PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> - 2017-08-14 18:20 +0200
Re: [PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-08-22 22:50 +0200
Re: [PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-08-22 22:50 +0200
Re: [PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> - 2017-08-23 14:20 +0200
[PATCH 4/5] ARC: AXS103: DTS: Set cpu frequency explicitly via dts Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> - 2017-08-14 18:20 +0200
Re: [PATCH 4/5] ARC: AXS103: DTS: Set cpu frequency explicitly via dts Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-08-22 23:50 +0200
Re: [PATCH 4/5] ARC: AXS103: DTS: Set cpu frequency explicitly via dts Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> - 2017-08-23 13:30 +0200
Re: [PATCH 4/5] ARC: AXS103: DTS: Set cpu frequency explicitly via dts Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-08-23 18:50 +0200
[PATCH 5/5] ARC: AXS103: use cpu-freq param instead of /cpu_card/core_clk Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> - 2017-08-14 18:20 +0200
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