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RE: [PATCH V5] perf: Add PERF_SAMPLE_PHYS_ADDR

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> 
> On Thu, Aug 17, 2017 at 02:17:23PM -0400, kan.liang@intel.com wrote:
> > diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
> > index a3b873f..6783c69 100644
> > --- a/include/linux/perf_event.h
> > +++ b/include/linux/perf_event.h
> > @@ -944,6 +944,8 @@ struct perf_sample_data {
> >
> >  	struct perf_regs		regs_intr;
> >  	u64				stack_user_size;
> > +
> > +	u64				phys_addr;
> >  } ____cacheline_aligned;
> >
> >  /* default value for data source */
> > @@ -964,6 +966,7 @@ static inline void perf_sample_data_init(struct
> perf_sample_data *data,
> >  	data->weight = 0;
> >  	data->data_src.val = PERF_MEM_NA;
> >  	data->txn = 0;
> > +	data->phys_addr = 0;
> >  }
> 
> So this is very unfortunate...
> 
> struct perf_sample_data {
>         u64                        addr;                 /*     0     8 */
>         struct perf_raw_record *   raw;                  /*     8     8 */
>         struct perf_branch_stack * br_stack;             /*    16     8 */
>         u64                        period;               /*    24     8 */
>         u64                        weight;               /*    32     8 */
>         u64                        txn;                  /*    40     8 */
>         union perf_mem_data_src    data_src;             /*    48     8 */
>         u64                        type;                 /*    56     8 */
>         /* --- cacheline 1 boundary (64 bytes) --- */
>         u64                        ip;                   /*    64     8 */
>         struct {
>                 u32                pid;                  /*    72     4 */
>                 u32                tid;                  /*    76     4 */
>         } tid_entry;                                     /*    72     8 */
>         u64                        time;                 /*    80     8 */
>         u64                        id;                   /*    88     8 */
>         u64                        stream_id;            /*    96     8 */
>         struct {
>                 u32                cpu;                  /*   104     4 */
>                 u32                reserved;             /*   108     4 */
>         } cpu_entry;                                     /*   104     8 */
>         struct perf_callchain_entry * callchain;         /*   112     8 */
>         struct perf_regs           regs_user;            /*   120    16 */
>         /* --- cacheline 2 boundary (128 bytes) was 8 bytes ago --- */
>         struct pt_regs             regs_user_copy;       /*   136   168 */
>         /* --- cacheline 4 boundary (256 bytes) was 48 bytes ago --- */
>         struct perf_regs           regs_intr;            /*   304    16 */
>         /* --- cacheline 5 boundary (320 bytes) --- */
>         u64                        stack_user_size;      /*   320     8 */
> 
>         /* size: 384, cachelines: 6, members: 19 */
>         /* padding: 56 */
> };
> 
> 
> static inline void perf_sample_data_init(struct perf_sample_data *data,
> 					 u64 addr, u64 period)
> {
> 	/* remaining struct members initialized in perf_prepare_sample() */
> 	data->addr = addr;
> 	data->raw  = NULL;
> 	data->br_stack = NULL;
> 	data->period = period;
> 	data->weight = 0;
> 	data->data_src.val = PERF_MEM_NA;
> 	data->txn = 0;
> }
> 
> You'll note that that only touches the first cacheline of the data structure,
> and you just wrecked that. Back when I did that this made a measurable
> difference.

It looks there is still one room in cacheline 1.
Could I use it?

diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index b14095b..bcd1007 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -915,6 +915,7 @@ struct perf_sample_data {
 	u64				weight;
 	u64				txn;
 	union  perf_mem_data_src	data_src;
+	u64				phys_addr;
 
 	/*
 	 * The other fields, optionally {set,used} by
@@ -964,6 +966,7 @@ static inline void perf_sample_data_init(struct perf_sample_data *data,
 	data->weight = 0;
 	data->data_src.val = PERF_MEM_NA;
 	data->txn = 0;
+	data->phys_addr = 0;
 }

Thanks,
Kan

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Thread

[PATCH V5] perf: Add PERF_SAMPLE_PHYS_ADDR kan.liang@intel.com - 2017-08-17 20:20 +0200
  Re: [PATCH V5] perf: Add PERF_SAMPLE_PHYS_ADDR Peter Zijlstra <peterz@infradead.org> - 2017-08-22 19:00 +0200
    RE: [PATCH V5] perf: Add PERF_SAMPLE_PHYS_ADDR "Liang, Kan" <kan.liang@intel.com> - 2017-08-22 20:00 +0200
      Re: [PATCH V5] perf: Add PERF_SAMPLE_PHYS_ADDR Peter Zijlstra <peterz@infradead.org> - 2017-08-22 20:30 +0200
  Re: [PATCH V5] perf: Add PERF_SAMPLE_PHYS_ADDR Peter Zijlstra <peterz@infradead.org> - 2017-08-22 19:10 +0200
    RE: [PATCH V5] perf: Add PERF_SAMPLE_PHYS_ADDR "Liang, Kan" <kan.liang@intel.com> - 2017-08-22 19:20 +0200
    Re: [PATCH V5] perf: Add PERF_SAMPLE_PHYS_ADDR Andi Kleen <ak@linux.intel.com> - 2017-08-22 19:40 +0200

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