Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to improve performance on some archs

From	Will Deacon <will.deacon@arm.com>
Newsgroups	linux.kernel
Subject	Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to improve performance on some archs
Date	2017-08-15 20:50 +0200
Message-ID	<ueP4B-4UD-7@gated-at.bofh.it> (permalink)
References	(5 earlier) <ucYvo-83r-25@gated-at.bofh.it> <ud0dQ-Jr-15@gated-at.bofh.it> <ude78-1CC-17@gated-at.bofh.it> <uemlX-3Zn-9@gated-at.bofh.it> <uesB5-7Hs-37@gated-at.bofh.it>
Organization	linux.* mail to news gateway

Show all headers | View raw

On Mon, Aug 14, 2017 at 08:47:11PM +0200, Peter Zijlstra wrote:
> On Mon, Aug 14, 2017 at 01:01:22PM +0100, Will Deacon wrote:
> > Yeah, that's right, you can't use the STXR status flag to create control
> > dependencies.
> 
> Just for my elucidation; you can't use it to create a control dependency
> on the store, but you can use it to create a control dependency on the
> corresponding load, right?

Hmm, sort of, but I'd say that the reads are really ordered due to
read-after-read ordering in that case. Control dependencies to loads
don't give you order.

> Now, IIRC, we've defined control dependencies as being LOAD->STORE
> ordering, so in that respect nothing is lost. But maybe we should
> explicitly mention that if the LOAD is part of an (otherwise) atomic RmW
> the STORE is not constrained.

I could well be misreading your suggestion, but it feels like that's too
weak. You can definitely still have control dependencies off the LL part
of the LL/SC pair, just not off the SC part.

E.g. this version of LB is forbidden on arm64:

P0:
if (atomic_inc_return_relaxed(&x) == 2)
	atomic_set(&y, 1);

P1:
if (atomic_inc_return_relaxed(&y) == 2)
	atomic_set(&x, 1);

Perhaps when you say "the STORE", you mean the store in the atomic RmW,
rather than the store in the LOAD->STORE control dependency?

Will

Thread

Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to  improve performance on some archs Will Deacon <will.deacon@arm.com> - 2017-08-14 14:10 +0200
  Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to improve  performance on some archs Waiman Long <longman@redhat.com> - 2017-08-14 17:10 +0200
    Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to  improve performance on some archs Will Deacon <will.deacon@arm.com> - 2017-08-14 18:10 +0200
  Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to  improve performance on some archs Peter Zijlstra <peterz@infradead.org> - 2017-08-14 20:50 +0200
    Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to  improve performance on some archs Will Deacon <will.deacon@arm.com> - 2017-08-15 20:50 +0200
      Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to  improve performance on some archs Peter Zijlstra <peterz@infradead.org> - 2017-08-21 13:00 +0200
        Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to  improve performance on some archs Will Deacon <will.deacon@arm.com> - 2017-08-21 20:10 +0200
          Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to  improve performance on some archs Peter Zijlstra <peterz@infradead.org> - 2017-08-21 21:30 +0200
            Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to  improve performance on some archs Peter Zijlstra <peterz@infradead.org> - 2017-08-21 21:50 +0200
              Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to improve  performance on some archs Waiman Long <longman@redhat.com> - 2017-08-22 17:40 +0200
            Re: [RESEND PATCH v5] locking/pvqspinlock: Relax cmpxchg's to  improve performance on some archs Will Deacon <will.deacon@arm.com> - 2017-08-22 12:50 +0200

csiph-web