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Groups > linux.kernel > #1695605
| From | Peter De Schrijver <pdeschrijver@nvidia.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 13/14] clk: tegra: Correct Tegra210 UTMIPLL poweron delay |
| Date | 2017-07-25 12:50 +0200 |
| Message-ID | <u75zz-1Fi-5@gated-at.bofh.it> (permalink) |
| References | <u75pT-1BV-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Alex Frid <afrid@nvidia.com> Increased Tegra210 UTMIPLL power on delay to 20us (spec maximum is 15us). Also remove a few empty lines to make it more clear the ACTIVE_DLY_COUNT and ENABLE_DLY_COUNT fields. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> --- drivers/clk/tegra/clk-tegra210.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 4fa7ab3..fd04b0e 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2472,15 +2472,14 @@ static void tegra210_utmi_param_configure(void) reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); - reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count); writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); /* Program UTMIP PLL delay and oscillator frequency counts */ reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); - reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); + reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count); @@ -2496,7 +2495,8 @@ static void tegra210_utmi_param_configure(void) reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); - udelay(1); + + udelay(20); /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */ reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); -- 1.9.1
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[PATCH 00/14] Fixes for Tegra clocks Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 03/14] clk: tegra: disable SSC for PLL_D2 Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 02/14] clk: tegra: Enable PLL_SS for Tegra210 Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 01/14] clk: tegra: fix SS control on PLL enable/disable Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 09/14] clk: tegra: don't warn for pll_d2 defaults unnecessarily Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 07/14] clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 08/14] clk: tegra: change post IDDQ release delay to 5us Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 05/14] clk: tegra: Init cfg structure in _get_pll_mnp Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 04/14] clk: tegra210: remove non-existing VFIR clock Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 06/14] clk: tegra: Fix T210 effective NDIV calculation Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
[PATCH 13/14] clk: tegra: Correct Tegra210 UTMIPLL poweron delay Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
[PATCH 11/14] clk: tegra: Update T210 PLLSS (D2/DP) registration Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
[PATCH 14/14] clk: tegra: Fix Tegra210 PLLU initialization Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
[PATCH 10/14] clk: tegra: Re-factor T210 PLLX registration Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
[PATCH 12/14] clk: tegra: Fix T210 PLLRE registration Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
Re: [PATCH 00/14] Fixes for Tegra clocks Stephen Boyd <sboyd@codeaurora.org> - 2017-07-26 03:40 +0200
Re: [PATCH 00/14] Fixes for Tegra clocks Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-26 10:30 +0200
Re: [PATCH 00/14] Fixes for Tegra clocks Stephen Boyd <sboyd@codeaurora.org> - 2017-07-27 21:00 +0200
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