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Groups > linux.kernel > #1695598

[PATCH 05/14] clk: tegra: Init cfg structure in _get_pll_mnp

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Not all fields are read from the hw depending on the PLL type. Make sure
the other fields are 0 by clearing the structure beforehand to prevent
users such as the rate re-calculation code from using bogus values.

Based on work by  Alex Frid <afrid@nvidia.com>

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-pll.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index fbd8726..1c36b8a 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -690,6 +690,8 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll,
 	struct tegra_clk_pll_params *params = pll->params;
 	struct div_nmp *div_nmp = params->div_nmp;
 
+	*cfg = (struct tegra_clk_pll_freq_table) { };
+
 	if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) &&
 		(pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &
 			PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) {
-- 
1.9.1

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[PATCH 00/14] Fixes for Tegra clocks Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 03/14] clk: tegra: disable SSC for PLL_D2 Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 02/14] clk: tegra: Enable PLL_SS for Tegra210 Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 01/14] clk: tegra: fix SS control on PLL enable/disable Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 09/14] clk: tegra: don't warn for pll_d2 defaults unnecessarily Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 07/14] clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 08/14] clk: tegra: change post IDDQ release delay to 5us Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 05/14] clk: tegra: Init cfg structure in _get_pll_mnp Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 04/14] clk: tegra210: remove non-existing VFIR clock Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 06/14] clk: tegra: Fix T210 effective NDIV calculation Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:40 +0200
  [PATCH 13/14] clk: tegra: Correct Tegra210 UTMIPLL poweron delay Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
  [PATCH 11/14] clk: tegra: Update T210 PLLSS (D2/DP) registration Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
  [PATCH 14/14] clk: tegra: Fix Tegra210 PLLU initialization Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
  [PATCH 10/14] clk: tegra: Re-factor T210 PLLX registration Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
  [PATCH 12/14] clk: tegra: Fix T210 PLLRE registration Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-25 12:50 +0200
  Re: [PATCH 00/14] Fixes for Tegra clocks Stephen Boyd <sboyd@codeaurora.org> - 2017-07-26 03:40 +0200
    Re: [PATCH 00/14] Fixes for Tegra clocks Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-07-26 10:30 +0200
      Re: [PATCH 00/14] Fixes for Tegra clocks Stephen Boyd <sboyd@codeaurora.org> - 2017-07-27 21:00 +0200

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