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[PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600 TMC

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The coresight SoC 600 supports ETR save-restore which allows us
to restore a trace session by retaining the RRP/RWP/STS.Full values
when the TMC leaves the Disabled state. However, the TMC doesn't
have a scatter-gather unit in built.

Also, TMCs have different PIDs in different configurations (ETF,
ETB & ETR), unlike the previous generation.

While the DEVID exposes some of the features/changes in the TMC,
it doesn't explicitly advertises the new save-restore feature
as described above.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-tmc.c | 16 ++++++++++++++++
 drivers/hwtracing/coresight/coresight-tmc.h |  4 ++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index c4a5dea..e754a3e 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -442,6 +442,22 @@ static struct amba_id tmc_ids[] = {
 		.id     = 0x000bb961,
 		.mask   = 0x000fffff,
 	},
+	{
+		/* Coresight SoC 600 TMC-ETR/ETS */
+		.id	= 0x000bb9e8,
+		.mask	= 0x000fffff,
+		.data	= (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS,
+	},
+	{
+		/* Coresight SoC 600 TMC-ETB */
+		.id	= 0x000bb9e9,
+		.mask	= 0x000fffff,
+	},
+	{
+		/* Coresight SoC 600 TMC-ETF */
+		.id	= 0x000bb9ea,
+		.mask	= 0x000fffff,
+	},
 	{ 0, 0},
 };
 
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 08f1aea..f24e89a 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -130,6 +130,10 @@ enum tmc_mem_intf_width {
  */
 #define TMC_ETR_SAVE_RESTORE		(0x1U << 2)
 
+/* Coresight SoC-600 TMC-ETR unadvertised capabilities */
+#define CORESIGHT_SOC_600_ETR_CAPS	\
+	(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
+
 /**
  * struct tmc_drvdata - specifics associated to an TMC component
  * @base:	memory mapped base address for this component.
-- 
2.7.5

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[PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600 Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:20 +0200
  [PATCH v5 13/19] coresight tmc: Detect support for scatter gather Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:20 +0200
  [PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600 TMC Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:20 +0200
    Re: [PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600 TMC Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-07-24 19:20 +0200
      Re: [PATCH v5 18/19] coresight tmc: Add support for Coresight SoC 600  TMC Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-07-25 11:40 +0200
  [PATCH v5 08/19] coresight tmc: Add helpers for accessing 64bit registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:20 +0200
    Re: [PATCH v5 08/19] coresight tmc: Add helpers for accessing 64bit registers Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-07-24 19:20 +0200
      Re: [PATCH v5 08/19] coresight tmc: Add helpers for accessing 64bit  registers Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-07-25 11:30 +0200
  [PATCH v5 07/19] coresight: Use the new helper for defining registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:30 +0200
  [PATCH v5 06/19] coresight: Add support for reading 64bit registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:30 +0200
  [PATCH v5 05/19] coresight: Extend the PIDR mask to cover relevant bits in PIDR2 Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:30 +0200
  [PATCH v5 10/19] coresight replicator: Expose replicator management registers Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:30 +0200
  [PATCH v5 04/19] arm64: qcom-msm8916: dts: Update coresight replicator Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:30 +0200
  [PATCH v5 03/19] arm: qcom-msm8974: dts: Update coresight replicator Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:30 +0200
    Re: [PATCH v5 03/19] arm: qcom-msm8974: dts: Update coresight  replicator Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-07-27 13:20 +0200
      Re: [PATCH v5 03/19] arm: qcom-msm8974: dts: Update coresight  replicator Andy Gross <andy.gross@linaro.org> - 2017-07-27 23:10 +0200
  [PATCH v5 09/19] coresight tmc: Expose DBA and AXICTL Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:30 +0200
  [PATCH v5 02/19] arm64: juno: dts: Use the new coresight replicator string Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:30 +0200
    Re: [PATCH v5 02/19] arm64: juno: dts: Use the new coresight  replicator string Liviu Dudau <liviu.dudau@arm.com> - 2017-07-20 15:00 +0200
      Re: [PATCH v5 02/19] arm64: juno: dts: Use the new coresight  replicator string Sudeep Holla <sudeep.holla@arm.com> - 2017-07-27 13:30 +0200
  [PATCH v5 01/19] coresight replicator: Cleanup programmable replicator naming Suzuki K Poulose <suzuki.poulose@arm.com> - 2017-07-20 12:30 +0200
  Re: [PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600 Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-07-24 19:20 +0200
    Re: [PATCH v5 00/19] coresight: Support for ARM Coresight SoC-600 Suzuki K Poulose <Suzuki.Poulose@arm.com> - 2017-07-25 11:50 +0200

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